Integrated Device Technology, Inc.
CMOS STATIC RAM
1 MEG (128K x 8-BIT)
IDT71024S70
FEATURES:
• 128K x 8 CMOS static RAM
• Equal access and cycle times
— Commercial: 70ns
• Two Chip Selects plus one Output Enable pin
• Bidirectional inputs and outputs directly TTL-compatible
• Low power consumption via chip deselect
• Available in 300 and 400 mil Plastic SOJ packages
FUNCTIONAL BLOCK DIAGRAM
A0
•
•
•
A16
ADDRESS
DECODER
DESCRIPTION:
The IDT71024 is a 1,048,576-bit medium-speed static
RAM organized as 128K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology. This stateof-the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
The IDT71024 has an output enable pin which operates as
fast as 30ns, with address access times as fast as 70ns
available. All bidirectional inputs and outputs of the IDT71024
are TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used; no clocks or
refreshes are required for operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ
and 32-pin 400 mil Plastic SOJ packages.
•
•
1,048,576-BIT
MEMORY ARRAY
•
I/O0 – I/O7
8
¥
8
I/O CONTROL
8
WE
OE
CONTROL
LOGIC
CS1
CS2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE MAY 1996
1996 Integrated Device Technology, Inc. DSC-3568/-
3568 drw 01
1
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Com'L. Unit
NC
A
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
1
16
2
3
4
5
6
7
8
9
10
11
12
13 20
14 19
15 18
16GND 17
S032-3
SO32-3
32
31
30
29
28
27
26
25
24
23
22
21
3568 drw 02
VCC
A15
CS2
WE
13
A
A8
A9
A11
OE
A
10
CS1
I/O
I/O6
I/O5
I/O4
I/O3
7
SOJ
TOP VIEW
TRUTH TABLE
(1,2)
INPUTS
WEWECS1
X H X X High-Z Deselected–Standby (I
XV
X X L X High-Z Deselected–Standby (I
XXV
CS2
CS1
HC
(3)
OE
OE
X X High-Z Deselected–Standby (ISB1)
(3)
LC
X High-Z Deselected–Standby (ISB1)
I/O FUNCTION
SB)
SB)
H L H H High-Z Outputs Disabled
H L H L DATA
L L H X DATA
NOTES: 3568 tbl 01
1. H = VIH, L = VIL, X = Don't care.
2. V
LC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥V
HC or ≤VLC.
OUT Read Data
IN Write Data
NOTES: 3568 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
2. V
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
NOTE: 3568 tbl 03
1. This parameter is guaranteed by device characterization, but is not prod-
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
NOTE: 3568 tbl 04
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
(2)
V
TERM
Terminal Voltage with –0.5 to +7.0 V
Respect to GND
T
A Operating Temperature 0 to +70 °C
BIAS Temperature Under Bias –55 to +125 °C
T
STG StorageTemperature –55 to +125 °C
T
P
T Power Dissipation 1.25 W
OUT DC Output Current 50 mA
I
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TERM must not exceed VCC + 0.5V.
Symbol Parameter
IN Input Capacitance VIN = 3dV 8 pF
C
I/O I/O Capacitance VOUT = 3dV 8 pF
C
uction tested.
CC Supply Voltage 4.5 5.0 5.5 V
V
(1)
Conditions Max. Unit
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.2 — Vcc+0.5 V
V
IL Input Low Voltage –0.5
V
(1)
— 0.8 V
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT71024
Symbol Parameter Test Condition Min. Max. Unit
LI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA
|I
LO| Output Leakage Current VCC = Max.,
|I
OL Output LOW Voltage IOL = 8mA, VCC = Min. — 0.4 V
V
OH Output HIGH Voltage IOH = –4mA, VCC = Min. 2.4 — V
V
.
CS1
= VIH, CS2 = VIL, VOUT = GND to VCC — 5 µA
3568 tbl 05
2
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
71024S70
Symbol Parameter Com'l. Mil. Unit
CC Dynamic Operating Current, CS2 ≥ VIH and 140 — mA
I
CS2 ≥ V
V
IH and
CS1
CC = Max., f = fMAX
≤ VIL, Outputs Open,
(2)
ISB Standby Power Supply Current (TTL Level) 35 — mA
CS1
V
IH or CS2 ≤ VIL, Outputs Open,
≥ V
CC = Max., f = fMAX
(2)
ISB1 Full Standby Power Supply Current 10 — mA
(CMOS Level)
or CS2 ≤ VLC Outputs Open,
V
CC = Max., f = 0
NOTES: 3568 tbl 06
1.All values are maximum guaranteed values.
MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
2.f
CS1
≥ V
HC,
(2)
, VIN ≤ VLC or VIN ≥ VHC
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
3568 tbl 07
DATA
OUT
30pF
Figure 1. AC Test Load
5V
480Ω
255Ω
3568 drw 03
DATA
5V
480Ω
OUT
5pF*
*Including jig and scope capacitance.
Figure 2. AC Test Load
CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
(for t
255Ω
3568 drw 04
3
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Commercial Temperature Range)
71024S70
Symbol Parameter Min. Max. Unit
Read Cycle
tRC Read Cycle Time 70 — ns
tAA Address Access Time —70 ns
tACS Chip Select Access Time —70 ns
(2)
tCLZ
tCHZ
tOE Output Enable to Output Valid — 30 ns
tOLZ
tOHZ
tOH Output Hold from Address Change 4 — ns
tPU
tPD
Write Cycle
tWC Write Cycle Time 70 — ns
tAW Address Valid to End-of-Write 60 — ns
tCW Chip Select to End-of-Write 60 — ns
tAS Address Set-up Time 0— ns
tWP Write Pulse Width 45 — ns
tWR Write Recovery Time 0— ns
tDW Data Valid to End-of-Write 30 — ns
tDH Data Hold Time 0— ns
tOW
WHZ
t
NOTES: 3568 tbl 08
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
Chip Select to Output in Low-Z 3 — ns
(2)
Chip Deselect to Output in High-Z 0 30 ns
(2)
Output Enable to Output in Low-Z 0 — ns
(2)
Output Disable to Output in High-Z 0 30 ns
(2)
Chip Select to Power-Up Time 0 — ns
(2)
Chip Deselect to Power-Down Time — 70 ns
(2)
Output Active from End-of-Write 5 — ns
(2)
Write Enable to Output in High-Z 0 30 ns
4
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
ADDRESS
t
AA
OE
(5)
t
t
OLZ
CLZ
t
ACS
(5)
DATA
Vcc
SUPPLY
CURRENT
CS1
CS2
OUT
Icc
Isb
HIGH IMPEDANCE
t
PU
(1)
t
RC
OE
t
(3)
(5)
t
OHZ
(5)
t
CHZ
OUT
DATA VALID
t
PD
3568 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2
ADDRESS
t
AA
t
OH
OUT
DATA
OUT
NOTES:
1.WE is HIGH for Read Cycle.
2. Device is continuously selected,
3. Address must be valid prior to or coincident with the later of
4.OE is LOW.
5. Transition is measured ±200mV from steady state.
CS1
is LOW, CS2 is HIGH.
VALID
CS1
transition LOW and CS2 transition HIGH; otherwise t
(1, 2, 4)
t
RC
DATA
t
OH
OUT
VALIDPREVIOUS DATA
3568 drw 06
AA is the limiting parameter.
5
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
t
ADDRESS
tAW
tCW
tWHZ
tWP
(6)
DATA
DATAIN
CS1
CS2
tAS
WE
OUT
WEWE CONTROLLED TIMING)
WC
(3)
(7)
HIGH IMPEDANCE
tDW
DATAIN VALID
tWR
tOW
tDH
(6)
(1, 2, 5, 7)
(6)
tCHZ
(4)(4)
3568 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS1
AND CS2 CONTROLLED TIMING)
CS1
tWC
ADDRESS
tAW
CS1
CS2
tAS
tCW
WE
tDW
IN
DATA
NOTES:
1.WE must be HIGH,
2. A write occurs during the overlap of a LOW
3. t
WR is measured from the earlier of either
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. Transition is measured ±200mV from steady state.
7.OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
CS1
state.
turn off and data to be placed on the bus for the required t
minimum write pulse is the specified t
LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance
CS1
and CS2
CS1
must be HIGH, or CS2 must be LOW during all address transitions.
must both be active during the tCW write period.
CS1
, HIGH CS2, and a LOW WE.
CS1
or WE going HIGH or CS2 going LOW to the end of the write cycle.
WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to
WP.
DW. If
OE
is HIGH during a WE controlled write cycle, this requirement does not apply and the
tWR
DATAIN VALID
(1, 2, 5)
(3)
tDH
3568 drw 08
6
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
71024
Device
Type
S
PowerXXSpeedXPackage
X
Process/
Temperature
Range
Blank
TY
Y
70
Commercial (0
°C to +70°C)
300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
Speed in nanoseconds
3568 drw 09
7
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