Datasheet IDT71024S15Y, IDT71024S15YI, IDT71024S17LB, IDT71024S17TY, IDT71024S17Y Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

CMOS STATIC RAM
1 MEG (128K x 8-BIT)

IDT71024

FEATURES:

• 128K x 8 advanced high-speed CMOS static RAM

• Commercial (0° to 70°C), Industrial (-40° to 85°C) and
Military (-55° to 125°C) temperature options

• Equal access and cycle times
— Military: 15/17/20/25ns
— Industrial: 15/20ns
— Commercial: 12/15/17/20ns

• Two Chip Selects plus one Output Enable pin

• Bidirectional inputs and outputs directly TTL-compatible

• Low power consumption via chip deselect

• Available in 300 and 400 mil Plastic SOJ, and LCC pack­ages

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

A

0

DESCRIPTION:

The IDT71024 is a 1,048,576-bit high-speed static RAM
organized as 128K x 8. It is fabricated using IDT’s high­performance, high-reliability CMOS technology. This state­of-the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.

The IDT71024 has an output enable pin which operates as
fast as 6ns, with address access times as fast as 12ns
available. All bidirectional inputs and outputs of the IDT71024
are TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used; no clocks or
refreshes are required for operation.

The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ,
32-pin 400 mil Plastic SOJ, and 32-pin 400 x 820 mil LCC
packages.

A

I/O0 – I/O

16

7

WE

OE

CS1

CS2

•

•

•

•

ADDRESS
DECODER

8

8

CONTROL
LOGIC

•

•

1,048,576-BIT

MEMORY ARRAY

•

I/O CONTROL

8

2964 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES MAY 1997

1996 Integrated Device Technology, Inc. DSC-2964/08

1

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

1

NC

16

A7
A6
A5
A4
A3
A2
A1
A0

2
3
4
5
6

SO32-2

7

SO32-3

L32-2

8
9
10
11
12
13 20
14 19
15 18

A
A14
A12

I/O0
I/O1
I/O2

16GND 17

SOJ/LCC

TOP VIEW

TRUTH TABLE

(1,2)

INPUTS

WEWECS1

CS1

CS2

OE

OE

I/O FUNCTION

X H X X High-Z Deselected–Standby (I

(3)

HC

XV

X X High-Z Deselected–Standby (ISB1)

X X L X High-Z Deselected–Standby (I

(3)

LC

XXV

X High-Z Deselected–Standby (ISB1)

H L H H High-Z Outputs Disabled
H L H L DATA
L L H X DATA

NOTES: 2964 tbl 01

1. H = VIH, L = VIL, X = Don't care.

2. V

LC = 0.2V, VHC = VCC -0.2V.

3. Other inputs ≥V

HC or ≤VLC.

32

VCC
A15

31

CS2

30

WE

29

13

A

28

A8

27

A9

26

A11

25

OE

24

A10

23

CS1

22

I/O

21

I/O6
I/O5
I/O4
I/O3

2964 drw 02

OUT Read Data

IN Write Data

7

SB)

SB)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l, Ind'l Mil. Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
Relative to GND

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

P

T Power 1.25 1.25 W

Dissipation

I

OUT DC Output 50 50 mA

Current

NOTES: 2964 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM must not exceed VCC + 0.5V.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Grade Temperature GND VCC

Commercial 0°C to +70°C 0V 5.0V ± 0.5V
Industrial -40°C to +85°C 0V 5.0V ± 0.5V
Military -55°C to +125°C 0V 5.0V ± 0.5V

2964 tbl 03

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — Vcc+0.5 V

V

IL Input Low Voltage –0.5

V

NOTE: 2964 tbl 04

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

(1)

— 0.8 V

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT71024

Symbol Parameter Test Condition Min. Max. Unit

LI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA

|I

LO| Output Leakage Current VCC = Max.,

|I

OL Output LOW Voltage IOL = 8mA, VCC = Min. — 0.4 V

V

OH Output HIGH Voltage IOH = –4mA, VCC = Min. 2.4 — V

V

CS1

= VIH, CS2 = VIL, VOUT = GND to VCC — 5 µA

2964 tbl 05

2

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)

71024S12 71024S15 71024S17 71024S20 71024S25

Symbol Parameter Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit

CC Dynamic Operating Current, CS2 ≥ VIH and 160 — 155 180 150 170 140 160 — 145 mA

I

CS2 ≥ V
V

IH and

CS1

CC = Max., f = fMAX

≤ VIL, Outputs Open,

(2)

ISB Standby Power Supply Current (TTL Level) 35 — 35 40 35 40 35 40 — 35 mA

CS1

V

IH or CS2 ≤ VIL, Outputs Open,

≥ V

CC = Max., f = fMAX

(2)

ISB1 Full Standby Power Supply Current 10 — 10 15 10 15 10 15 — 15 mA

(CMOS Level)
or CS2 ≤ VLC Outputs Open,
V

CC = Max., f = 0

NOTES: 2964 tbl 06

1. All values are maximum guaranteed values.

MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

2. f

DC ELECTRICAL CHARACTERISTICS

CS1

≥ V

HC,

(2)

, VIN ≤ VLC or VIN ≥ VHC

(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)

71024S15 71024S20

Symbol Parameter Industrial Industrial Unit

CC Dynamic Operating Current, CS2 ≥ VIH and 180 160 mA

I

CS2 ≥ V
V

ISB Standby Power Supply Current (TTL Level) 45 45 mA

CS1

V

ISB1 Full Standby Power Supply Current 15 15 mA

(CMOS Level)
or CS2 ≤ VLC Outputs Open,
V

NOTES: 2964 tbl 07

1. All values are maximum guaranteed values.

2. f

MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

IH and

CS1

≤ VIL, Outputs Open,

CC = Max., f = fMAX

IH or CS2 ≤ VIL, Outputs Open,

≥ V

CC = Max., f = fMAX

CC = Max., f = 0

(2)

(2)

CS1

≥ V

(2)

, VIN ≤ VLC or VIN ≥ VHC

HC,

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

Symbol Parameter

IN Input Capacitance VIN = 3dV 7 pF

C

I/O I/O Capacitance V OUT = 3dV 8 pF

C

NOTE: 2964 tbl 08

1. This parameter is guaranteed by device characterization, but is not prod­uction tested.

(1)

Conditions Max. Unit

3

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

2964 tbl 09

DATA

5V

OUT

30pF

Figure 1. AC Test Load

480

255

Ω

Ω

2964 drw 03

5V

480

OUT

DATA

5pF*

*Including jig and scope capacitance.

Figure 2. AC Test Load

(for t

CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

255

Ω

Ω

2964 drw 04

4

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

71024S12

(1)

71024S15 71024S17

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle

tRC Read Cycle Time 12 — 15 — 17 — 20 — 25 — ns
tAA Address Access Time — 12 — 15 — 17 — 20 — 25 ns
tACS Chip Select Access Time — 12 — 15 — 17 — 20 — 25 ns

(4)

tCLZ
tCHZ

Chip Select to Output in Low-Z 3 — 3 — 3 — 3 — 3 — ns

(4)

Chip Deselect to Output in High-Z 0 6 0 7 0 8 0 8 0 10 ns

tOE Output Enable to Output Valid — 6 — 7 — 8 — 8 — 10 ns

(4)

tOLZ
tOHZ

Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — 0 — ns

(4)

Output Disable to Output in High-Z 0 5 0 5 0 6 0 7 0 10 ns

tOH Output Hold from Address Change 4 — 4 — 4 — 4 — 4 — ns

(4)

tPU
tPD

Chip Select to Power-Up Time 0 — 0 — 0 — 0 — 0 — ns

(4)

Chip Deselect to Power-Down Time — 12 — 15 — 17 — 20 — 25 ns

Write Cycle

tWC Write Cycle Time 12 — 15 — 17 — 20 — 25 — ns
tAW Address Valid to End-of-Write 10 — 12 — 13 — 15 — 15 — ns
tCW Chip Select to End-of-Write 10 — 12 — 13 — 15 — 15 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 10 — 12 — 13 — 15 — 15 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
tDW Data Valid to End-of-Write 7 — 8 — 9 — 9 — 10 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns

(4)

tOW

WHZ

t

NOTES: 2964 tbl 010

1. 0°C to +70°C temperature range only.

2. –55°C to +125°C temperature range only.

3. 0°C to +70°C and –55°C to +125°C temperature ranges only.

4. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.

Output Active from End-of-Write 3 — 3 — 3 — 4 — 4 — ns

(4)

Write Enable to Output in High-Z 0 5 0 5 0 7 0 8 0 9 ns

(3)

71024S20 71024S25

(2)

5

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1

ADDRESS

t

AA

OE

(5)

t

t

CLZ

OLZ

t

ACS

(5)

DATA

Vcc
SUPPLY
CURRENT

CS1

CS2

OUT

Icc
Isb

HIGH IMPEDANCE

t

PU

(1)

RC

t

OE

t

(3)

(5)

t

OHZ

(5)

t

CHZ

DATA VALID

OUT

t

PD

2964 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 2

ADDRESS

tAA

tOH tOH

DATAOUT

NOTES:

1.WE is HIGH for Read Cycle.

2. Device is continuously selected,

3. Address must be valid prior to or coincident with the later of

4.OE is LOW.

5. Transition is measured ±200mV from steady state.

CS1

is LOW, CS2 is HIGH.

CS1

transition LOW and CS2 transition HIGH; otherwise t

(1, 2, 4)

tRC

DATAOUT VALIDPREVIOUS DATAOUT VALID

2964 drw 07

AA is the limiting parameter.

6

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WC

t

ADDRESS

tAW

tCW

tWHZ

tWP

(6)

DATA

DATAIN

CS1

CS2

tAS

WE

OUT

WEWE CONTROLLED TIMING)

(3)

(7)

HIGH IMPEDANCE

tDW

DATAIN VALID

tWR

tDH

tOW

(6)

(1, 2, 5, 7)

(4)(4)

tCHZ

(6)

2964 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS1

AND CS2 CONTROLLED TIMING)

CS1

tWC

ADDRESS

tAW

CS1

CS2

tAS

tCW

WE

tDW

DATA

IN

NOTES:

1.WE must be HIGH,

2. A write occurs during the overlap of a LOW

3. t

WR is measured from the earlier of either

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

6. Transition is measured ±200mV from steady state.

7.OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t

CS1

state.

turn off and data to be placed on the bus for the required t
minimum write pulse is the specified t

LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance

CS1

and CS2

CS1

must be HIGH, or CS2 must be LOW during all address transitions.

must both be active during the tCW write period.

CS1

, HIGH CS2, and a LOW WE.

CS1

or WE going HIGH or CS2 going LOW to the end of the write cycle.

WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to

WP.

DW. If

OE

is HIGH during a WE controlled write cycle, this requirement does not apply and the

tWR

DATAIN VALID

(1, 2, 5)

(3)

tDH

2964 drw 10

7

IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT) MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

IDT

71024

Device

Type

71024

Device

Type

S

PowerXXSpeedXPackage

S

PowerXXSpeedXPackage

X

Process/

Temperature

Range

X

Process/

Temperature

Range

Blank

TY
Y

Commercial (0°C to +70°C)

300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)

12
15
17

Speed in nanoseconds

20

I

Industrial (–40°C to +85°C)

Y 400-mil SOJ (SO32-3)

2964 drw 11

IDT

71024

Device

Type

S

PowerXXSpeedXPackage

X

Process/

Temperature

Range

15
20

B

Speed in nanoseconds

Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B

L 400 x 820 mil LCC package (L32-2)

15
17
20

Speed in nanoseconds

25

2964 drw 12

2964 drw 13

8