1
I
CMOS Static RAM
1 Meg (128K x 8-Bit)
IDT71024
Features
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128K x 8 advanced high-speed CMOS static RAM
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Commercial (0°C to +70°C), Industrial (–40°C to +85°C)
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Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
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Two Chip Selects plus one Output Enable pin
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Bidirectional inputs and outputs directly
TTL-compatible
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Low power consumption via chip deselect
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Available in 300 and 400 mil Plastic SOJ.
Functional Block Diagram
A
0
•
•
•
ADDRESS
DECODER
Description
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs.
The IDT71024 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32pin 400 mil Plastic SOJ.
•
•
1,048,576-BIT
MEMORY ARRAY
•
A
16
/O0–I/O
7
¥
8
I/O CONTROL
8
8
WE
OE
CS
CS
1
2
CONTROL
LOGIC
2964 drw 0
JANUARY 2004
©2004 Integrated Device Technology, Inc.
1
DSC-2964/15
IDT71024 CMOS Static RAM
G
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Pin Configuration
NC
A
A
A
I/O
I/O
I/O
ND 17
Truth Table
Inputs
WE CS
X H X X High-Z Deselected – Sta ndby (I
XV
X X L X High-Z Deselected – Standby (I
XXV
1
CS2OE
(3)
HC
X X High-Z Deselected – Sta ndby (I
LC
16
14
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
1
2
1
2
3
4
5
6
SO32-2
7
SO32-3
8
9
10
11
12
13 20
14 19
15 18
32
31
30
29
28
27
26
25
24
23
22
21
16
SOJ
2964 drw 02
Top View
(1,2)
I/O Function
(3)
X High-Z Deselected – Sta ndby (I
V
CC
A
15
CS
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
I/O
I/O
I/O
I/O
2
1
7
6
5
4
3
SB
SB1
SB
SB1
Absolute Maximum Ratings
Symbol Rating Value Unit
(2)
V
TERM
BIAS
T
T
STG
P
T
OUT
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
Termin al Voltage with Respect to GND –0.5 to +7. 0 V
Temperature Under Bias –55 to +125oC
Storage Temperat ure –55 to +125oC
Pow er Dissipation 1.25 W
DC Out put Current 50 m A
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol Parameter
C
IN
Input Ca pacitance VIN = 3dV 7 pF
C
I/O
)
)
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
)
I/O Capa citance V
)
(1)
Conditions Max. Unit
OUT
= 3dV 8 pF
(1)
2964 tbl 02
2964 tbl 03
H L H H High-Z Output s Disabled
HLHLDATA
LLHXDATA
NOTES:
1. H = VIH, L = VIL, X = Don't care.
2. VLC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥VHC or ≤VLC.
OUT
IN
Read Data
Write D ata
2964 tbl 01
Recommended Operating
Temperature and Supply Voltage
Grade Temperature GND V
Commercial 0°C to +70°C 0V 5.0V ± 0.5V
Indust rial –4 0° C to + 85° C 0V 5. 0V ± 0. 5V
CC
2964 t bl 05
Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit
CC
Supply Voltage 4.5 5.0 5.5 V
V
GND Ground 0 0 0 V
V
IH
Input H igh Voltage 2.2
IL
Input Low Voltage –0.5
V
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
____
VCC+0.5 V
(1)
____
0.8 V
2964 tbl 04
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2
IDT71024 CMOS Static RAM
D
5
V
D
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
IDT71024
Symbol Parameter Test Condition
LI
| I nput Leakage Current VCC = Max., VIN = GND to V
|I
LO
| Output Leakage Current VCC = Max., CS1 = VIH, V
|I
OL
V
OH
V
Output Low Voltage IOL = 8mA, VCC = Min.
Output High Voltage IOH = –4m A, VCC = M in. 2.4
DC Electrical Characteristics
(1)
CC
OUT
= GND to V
CC
___
___
___
5µA
5µA
0.4 V
___
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
71024S12 71024S15 71 024S20
Symbol Parameters Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit
CC
I
I
SB
SB1
I
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Dynamic Operating Current,
2
≥ VIH and CS1 ≤ VIL, Outp uts Op en,
CS
CC
= Max., f = f
V
MAX
(2)
Standby Power Supply Current (TTL Level)
1
≥ VIH or CS2 ≤ VIL, Outp uts Op en,
CS
CC
= Max., f=f
V
MAX
(2)
Full Standby Power Supply Current
(CMOS Le v el ), CS
CS
2
≤ VLC, Outputs Ope n,
CC
= Max., f = 0
V
1
≥ VHC or
(2)
, VIN ≤ VLC or VIN ≥ V
160 160 155 155 140 140 mA
40 40 40 40 40 40 mA
10 10 10 10 10 10 mA
HC
UnitMin. Max.
V
2964 tbl 06
2964 t bl 07
AC Test Conditions
Input Pu lse Levels GND to 3. 0V
Input R ise/Fall Times 3ns
Input Tim ing Reference Lev els 1.5V
Output Reference Lev els 1.5V
AC Test Load See Figures 1 and 2
2964 tbl 08
OUT
ATA
480Ω
OUT
ATA
255Ω30pF
2964 drw 03
Figure 1. AC Test Load
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3
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
5V
480Ω
255Ω5pF*
2964 drw 04
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71024S12 7 1024S15 71024S20
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
Read Cy cle
RC
t
AA
t
ACS
t
(1)
CLZ
t
(1)
CHZ
t
OE
t
(1)
OLZ
t
(1)
OHZ
t
OH
t
(1)
PU
t
(1)
PD
t
Wri t e C yc le
WC
t
AW
t
CW
t
AS
t
WP
t
Re ad Cyc l e Time 12 — 15 — 20 — ns
Address Access Time — 12 — 15 — 20 ns
Chip Selec t Access Time — 12 — 15 — 20 ns
Chip Selec t to Output in Low-Z 3 — 3 — 3 — ns
Chip Desele ct to Outp ut in High-Z 0 6 0 7 0 8 ns
Output Enable to Output Valid — 6 — 7 — 8 ns
Output Enable to Output in Low-Z 0 — 0 — 0 — ns
Output Disable to Output in High-Z 050507ns
Output Hold from Address Change 4 — 4 — 4 — ns
Chip Selec t to Power-Up Time 0 — 0 — 0 — ns
Chip De s e le c t to Po we r-Do wn Time — 12 — 15 — 20 ns
Write Cycle Time 12 — 15 — 20 — ns
Address Valid to End-of-Write 10 — 12 — 15 — ns
Chip Selec t to End-of-Write 10 — 12 — 15 — ns
Address Set-Up Time 0— 0—0—ns
Write Pulse Width 8 — 12 — 15 — ns
WR
t
DW Data Valid to End -o f-Write 7 — 8 — 9 — ns
t
DH
t
(1)
OW
t
(1)
WHZ
t
Write Recovery Time 0— 0— 0—ns
Data Ho ld Tim e 0 — 0 — 0 — ns
Outp ut Ac tiv e fro m E nd -o f-Wri te 3 — 3 — 4 — ns
Write Enable to Output in High-Z 050508ns
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2964 tb l 09
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4
IDT71024 CMOS Static RAM
t
C
A
6
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
RC
ADDRESS
t
AA
OE
t
OE
(5)
t
t
CLZ
OLZ
(3)
t
ACS
t
CHZ
VALID
t
OHZ
(5)
(5)
(5)
DATA
OUT
t
PD
DATA
Vcc
CS
OUT
CS
1
2
HIGH IMPEDANCE
t
Icc
PU
SUPPLY
I
URRENT
SB
2964 drw 05
Timing Waveform of Read Cycle No. 2
t
RC
(1,2,4)
DDRESS
t
AA
t
OH
DATA
DATA
OUT
OUT
VALID
OUT
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
t
OH
VALIDPREVIOUS DATA
2964 drw 0
6.42
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IDT71024 CMOS Static RAM
A
A
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
DDRESS
CS
1
2
CS
t
AS
WE
DATA
OUT
DATA
IN
(1,4,6)
t
t
WHZ
CW
WC
t
t
AW
(6)
t
WP
(5)
HIGH IMPEDANCE
t
DW
DATAINVALID
(2)
t
WR
(5)
t
(5)
t
OW
t
DH
CHZ
(3)(3)
2964 drw 07
Timing Waveform of Write Cycle No. 2
tAW
(1,4)
tWC
tCW
tDW
DATAINVALID
tWR
(2)
tDH
2964 drw 08
1 AND CS2 Controlled Timing)
(CS
DDRESS
CS1
2
CS
tAS
WE
DATAIN
NOTES:
1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.
2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must
both be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
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IDT71024 CMOS Static RAM
I
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Ordering Information
DT
71024
Device
Type
S
PowerXXSpeedXPackage
X
X
Process/
Temperature
Range
Blank
Commercial(0°C to +70°C)
I
Industrial (–40°C to +85°C)
G
Restricted hazardoussubstance device
TYY300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
12
15
Speedin nanoseconds
20
2964 drw 09
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IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Datasheet Document History
9/30/99 Updated to new format
Pg. 1, 3, 4, 7 Added 12ns industrial speed grade offering
Pg. 1–4, 7 Removed military temperature offerings
Removed 17ns and 25ns speed grades
Pg. 3 Revised ICC and ISB1 for 15ns and 20ns industrial speed grades
Pg. 6 Removed Note 1, reordered notes and footnotes
Pg. 8 Added Datasheet Document History
1/6/2000 Pg. 4 Changed tWP(min) for 12ns speed grade from 10ns to 8ns.
2/18/00 Pg. 3 Revised Icc and ISB for Industrial Temperature offerings to meet commercial specifications
3/14/00 Pg. 3 Revised ISB to accomidate speed functionaility
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
01/30/04 Pg. 7 Added "Restricted hazardous substance device" to the ordering information.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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