Datasheet IDT70V3599-89S Datasheet (IDT)

BE

查询IDT70V3589供应商

HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous
access of the same memory location

◆

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)

◆

Selectable Pipelined or Flow-Through output mode

◆

Counter enable and repeat features

◆

Dual chip enables allow for depth expansion without
additional logic

◆

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time

IDT70V3599/89S

◆

Separate byte controls for multiplexed bus and bus
matching compatibility

◆

Dual Cycle Deselect (DCD) for Pipelined Output mode

◆

LVTTL- compatible, 3.3V (±150mV) power supply
for core

◆

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port

◆

Industrial temperature range (-40°C to +85°C) is
available at 133MHz.

◆

Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)

◆

Supports JTAG features compliant with IEEE 1149.1

Functional Block Diagram

BE

3L

BE

2L

BE

1L

BE

0L

FT/PIPE

CE

CE

FT/PIPE

R/W

OE

L

L

0L
1L

L

L

1/0

abcd

1

0

1/0

I/O0L-I/O

CLK

L

REPEAT

NOTE:

16 is a NC for IDT70V3589.

1. A

©2003 Integrated Device Technology, Inc.

A

CNTEN

ADS

0d 1d0c 1c0b 1b0a 1a

1d 0d 1c 0c

abcd

1b 0b 1a 0a

Counter/
Address

Reg.

0/1

35L

(1)

16L

A

0L

L

L

L

TDO

3R

BE

2R

BE

1R

BE

0R

1a 0a1b 0b1c 0c1d 0d

dcba

B

B

B

B

B

B

B

B

W

W

W

W

W

W

W

W

0

1

2

3

2

3

1

0

L

L

L

L

R

R

R

R

Dout0-8_L
Dout9-17_L
Dout18- 26_L
Dout27- 35_L

Din_L

ADDR_L

TDI

Dout18 -26_R
Dout27 -35_R

128Kx 36
MEMORY

ARRAY

JTAG

Dout0-8_R

Dout9-17_R

Din_R

ADDR_R

TCK
TMS

TRST

0b 1b0a 1a

Counter/
Address

Reg.

dcba

0d 1d0c 1c

0/1

I/O0R- I/O

35R

(1)

A

16R

A

0R

REPEAT

R

ADS

R

CNTEN

R

1/0

1

0

1/0

CLK

,

R

5617 tbl 01

FT/PIPE

R/W

CE

CE

OE

FT/PIPE

R

R

0R
1R

R

R

MAY 2003

1

DSC 5617/6

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3599/89 has been optimized for applications having unidirectional

or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE

0 and CE1, permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70V3599/89 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V

DD) remains at 3.3V.

A2

B2

C2

I/O

D2

E2

I/O

F2

I/O

G2

H2

I/O

J2

K2

L2

M2

N2

P2

R2

I/O

T2

U2

I/O

IO

I/O

I/O

I/O

I/O

18L

V

SS

19R

V

SS

22R

23R

V

SS

26R

V

DD

V

SS

V

SS

32L

33L

35L

(1,2,3,4,5)

A3

V

SS

B3

I/O

18R

C3

V

DDQR

D3

I/O

21L

E3

V

DDQR

F3

I/O

24L

G3

I/O

H3

V

DDQR

J3

V

SS

K3

I/O

27R

L3

V

DDQR

28L

M3

29L

I/O

30R

N3

I/O

31R

P3

V

DDQR

R3

I/O

34R

T3

34L

V

DDQL

U3

PL/

FT

25L

A8

A7

A

8L

A

12L

B7

B8

A

9L

BE

2L

C8

C7

BE

10L

3L

D8

BE

0L

7L

A

D7

A

70V3599/89BF

BF-208

208-Pin fpBGA

Top View

P8

P7

A

8R

A

12R

R7

R8

BE

A

T7

A

U7

2R

9R

T8

BE

3R

10R

U8

A

7R

BE

0R

A9

A10

BE

1L

V

DD

B9

B10

CE

0L

V

SS

C10

C9

V

SS

CE

1L

D9

D10

V

DD

OE

L

(6)

(7)

P9

P10

BE

1R

V

DD

R10

R9

CE

0R

V

SS

T9

T10

CE

1R

V

SS

U10

U9

OE

V

R

DD

L

A5

NC

B5

NC

C5

NC

D5

A

15L

P5

TRST

R5

NC

T5

NC

U5

A

15R

A6

(1)

A

16L

B6

A

13L

C6

A

14L

D6

A

11L

P6

(1)

A

16R

R6

A

13R

T6

A

14R

U6

A

11R

A4

TDO

B4

TDI

C4

PL/

FT

D4

I/O

20L

E4

I/O

21R

F4

V

SS

G4

I/O

24R

H4

I/O

25R

J4

V

SS

K4

V

SS

L4

I/O

27L

M4

V

SS

N4

I/O

30L

P4

I/O

35R

R4

TCK

T4

TMS

U4

R

NC

A11

CLK

B11

ADS

C11

R/W

D11

REPEAT

P11

CLK

R11

ADS

T11

R/W

L

L

L

L

R

R

R

A12

CNTEN

B12

A

5L

C12

A

6L

D12

A

3L

P12

CNTEN

R12

A

5R

T12

A

6R

U12

A

3R

A14

A13

A

L

B13

C13

D13

P13

R

R13

T13

U13

0L

A

4L

B14

A

1L

V

SS

C14

A

2L

V

DD

D14

I/O

17R

V

DD

E14

I/O

12L

F14

V

SS

G14

I/O

9L

H14

V

DD

J14

V

SS

K14

I/O

7R

L14

I/O

6R

M14

V

SS

N14

I/O

3R

P14

I/O

A

A

A

A

2L

4R

R14

1R

V

SS

T14

2R

V

SS

U14

0R

V

DD

Pin Configuration

06/28/0 2

A1

IO

19L

B1

I/O

20R

C1

V

DDQL

D1

I/O

22L

E1

I/O

23L

F1

V

DDQL

G1

I/O

26L

H1

V

DD

J1

V

DDQL

K1

I/O

28R

L1

I/O

29R

M1

V

DDQL

N1

I/O

31L

P1

I/O

32R

R1

V

SS

T1

I/O

33R

U1

V

SS

NOTES:

1. A

16 is a NC for IDT70V3589.

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

3. All V

4. All V

IL (0V).

set to V

SS pins must be connected to ground supply.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

2

A15

OPT

B15

V

DDQR

C15

I/O

D15

V

E15

I/O

F15

I/O

G15

V

DDQL

H15

IO

J15

V

K15

V

L15

I/O

M15

I/O

N15

V

P15

I/O

R15

V

T15

I/O

U15

OPT

16R

DDQL

13R

12R

9R

DD

DDQL

7L

6L

DDQL

3L

DDQL

0R

L

R

A16

I/O

B16

I/O

C16

I/O

D16

I/O

E16

F16

I/O

G16

I/O

H16

J16

K16

I/O

L16

M16

N16

I/O

P16

R16

T16

U16

I/O

I/O

I/O

17L

16L

15L

14L

V

SS

11L

10L

V

SS

V

SS

V

SS

4R

V

SS

V

SS

A17

V

SS

B17

I/O

15R

C17

V

SS

D17

I/O

14R

E17

I/O

13L

F17

V

DDQR

G17

I/O

11R

H17

I/O

10R

J17

V

DDQR

K17

8R

V

SS

L17

I/O

8L

M17

V

DDQR

5R

N17

I/O

P17

I/O

4L

R17

1R

V

DDQR

T17

I/O

2R

U17

I/O

1L

0L

5617 drw 02c

5L

,

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,5)

(con't.)

06/2 8/02

A1

NC

B1

I/O

18L

C1

I/O

18R

D1

I/O

20R

E1

I/O

21R

F1

I/O

23L

G1

I/O

24R

H1

I/O

26L

J1

I/O

27L

K1

I/O

29R

L1

I/O

30L

M1

I/O

32R

N1

I/O

33L

P1

I/O

35R

R1

I/O

35L

T1

NC

A3

A2

NC

TDI

B3

B2

TDO

NC

C2

C3

V

19L

19R

21L

22R

24L

25R

28R

29L

31R

32L

34R

34L

SS

D3

I/O

20L

E3

I/O

22L

F3

I/O

23R

G3

I/O

25L

H3

I/O

26R

J3

I/O

27R

K3

I/O

28L

L3

I/O

30R

M3

I/O

31L

N3

I/O

33R

P3

TMSP4A

I/O

D2

I/O

E2

I/O

F2

I/O

G2

I/O

H2

I/O

J2

I/O

K2

I/O

L2

I/O

M2

I/O

N2

I/O

P2

I/O

R2

NCR3TRSTR4NC

T2

TCKT3NC

A4

NC

B4

NC

C4

A

16L

D4

PIPE/

E4

V

DDQL

F4

V

DDQL

G4

V

DDQR

H4

V

DDQR

J4

V

DDQL

K4

V

DDQL

L4

V

DDQR

M4

V

DDQR

N4

PIPE/

16R

T4

NC

FT

FT

70V3599/89BC

BC-256

(6)

256-Pin BGA

2L

3L

DDQR

V

SS

SS

SS

SS

SS

V

SS

V

SS

V

SS

DDQL

1R

3R

2R

(7)

A12

B12

C12

D12

V

E12

F12

G12

H12

J12

K12

L12

M12

N12

V

P12

R12

T12

A

A

A

DDQR

V

V

DD

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

DDQL

A

A

A

DD

6R

4R

A13

A14

A

2L

A

1L

A

3L

DD

DDQL

DDQR

DDQL

DDQL

DD

3R

1R

2R

B14

V

C14

OPT

D14

I/O

E14

I/O

F14

I/O

G14

I/O

H14

I/O

J14

I/O

K14

I/O

L14

I/O

M14

I/O

N14

I/O

P14

I/O

R14

OPT

T14

A

0L

DD

L

15R

13L

12R

10L

9R

8R

6R

5L

3R

2L

0L

R

0R

5L

A

B13

4L

C13

6L

D13

V

E13

V

DDQR

F13

V

DDQR

G13

V

H13

V

DDQL

J13

V

DDQR

K13

V

L13

V

M13

V

N13

V

P13

A

R13

A

T13

5R

A

A16

A15

NC

B15

B16

I/O

17L

C16

C15

I/O

17R

D15

D16

I/O

15L

E16

E15

I/O

14L

F15

F16

I/O

13R

G15

G16

I/O

I/O

11L

H16

H15

I/O

IO

9L

J15

J16

I/O

7R

K15

K16

I/O

6L

L15

L16

I/O

4R

M16

M15

I/O

3L

N16

N15

I/O

1R

P15

P16

I/O

0R

R16

R15

NC

T15NCT16

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

NC

NC

NC

NC

16L

16R

14R

12L

11R

10R

8L

7L

5R

4L

2R

1L

,

A10

OE

B10

R/W

C10

CLK

D10

V

DDQL

E10

V

F10

V

G10

V

H10

V

J10

V

K10

V

L10

V

M10

V

N10

V

DDQR

P10

CLK

R10

R/W

T10

OE

A11

CNTEN

L

L

B11

REPEA T

L

L

C11

ADS

L

L

D11

V

DDQR

E11

SS

V

DD

F11

SS

V

SS

G11

SS

V

SS

H11

V

SS

SS

J11

SS

V

SS

K11

SS

V

SS

L11

V

SS

SS

M11

SS

V

DD

N11

V

DDQL

P11

R

ADS

R

R11

REPEAT

R

R

T11

CNTEN

R

R

A9

CE

1L

B9

CE

0L

C9

1L

BE

0L

D9

V

DDQL

E9

V

SS

F9

V

SS

G9

V

SS

H9

V

SS

J9

V

SS

K9

V

SS

L9

V

SS

M9

V

SS

N9

V

DDQR

P9

BE

0R

R9

CE

0R

T9

CE

1R

Top View

A7

B7

C7

D7

V

E7

F7

G7

H7

J7

K7

L7

M7

N7

V

P7

R7

T7

A

8L

A

9L

A

7L

DDQR

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQL

A

7R

A

9R

A

8R

A8

BE

B8

BE

C8

BE

D8

V

E8

F8

V

G8

V

H8

V

J8

V

K8

L8

M8

N8

V

P8

BE

R8

BE

T8

BE

A6

A5

A

11L

A

14L

B6

B5

A

12L

A

15L

C6

C5

(1)

L

R

(1)

D5

V

E5

F5

G5

H5

J5

K5

L5

M5

N5

V

P5

R5

T5

A

DDQL

V

V

V

V

V

V

V

V

DDQR

A

13R

A

A

13L

DD

DD

SS

SS

SS

SS

DD

DD

15R

14R

D6

V

E6

F6

G6

H6

J6

K6

L6

M6

N6

V

P6

R6

T6

A

10L

DDQL

V

V

V

V

V

V

V

V

DDQR

A

10R

A

12R

A

11R

DD

SS

SS

SS

SS

SS

SS

DD

NOTES:

1. A

16 is a NC for IDT70V3589.

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

3. All V

4. All V

IL (0V).

set to V

SS pins must be connected to ground supply.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

3

5617 drw 02d

,

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

R

R

Q

8
1

D
D

O

/

V

I

6

7

0

0

2

2

5

4

5

5

L

R
5

Q

3

D

O

D

/

I

V

(1,2,3,4,5)

L

L

T

8

F

I

1

/

S
S

L

D

O

/

I

V

P

T

4

5

2

3

0

0

0

0
2

2

2

2

9

8

7

6

5

5

5

5

L

R

K

S

5

T

3

C

M

F

T

/

O

T

/

L

I

P

(con't.)

)

1

(

L

L

L

L

L

L

O

6

5

C

C

C

1

D
T

1
0
2

1

A

A

N

N

N

6

7

8

9

0

9

9

9

9

0
2

1

1

1

1

L

4

3

2

1

0

L

L

1

1

1

A

A

A

5

3

4

9

9

9

1

1

1

L

1

1

9

8

7

A

A

A

A

A

0

1

2

8

9

9

9

9

8

8

1

1

1

1

1

L

L
3

E
B

7
8
1

L

L

L

L

1

0

2

1

0

E

E

E

E

E

B

B

B

C

C

2

3

4

5

6

8

8

8

8

8
1

1

1

1

1

70V3599/89DR

DR-208

208-Pin PQFP

Top View

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

6

6

6

6

6

)

T

1

C

C

C

(

S

R

N

N

N

6

R

1

T

A

6

6

6

6

6

R

R

R

R

R

5

4

3

2

1

1

1

1

1

1

A

A

A

A

A

7

7

7

7

7

R

R

R

R

R

0

9

8

7

3

1

E

A

A

A

A

B

7

7

7

7

7

R

R

R

R

R

2

1

0

1

0

E

E

E

E

E

B

B

B

C

C

L

K

D

D

S

S

L

D

D

S

S

V

V

V

V

C

9

0

1

7

8

7

8

8

7

7
1

1

1

1

1

(6)

(7)

4

3

2

1

0

8

8

8

8

8

S

S

D

D

R

S

S

D

D

K

V

V

V

V

L
C

L

L

T
A

N

L

E

E

L

L

T

P

S

L

L

W

E

/

D

O

R

A

6

4

5

7

7

7
1

1

1

7

6

5

8

8

8

R

R

R

E

S

W

/

D

O

R

A

L

N

E

6

5

4

C

R

A

A

A

3

1

2

0

9

7

7

7

7

6

1

1

1

1

1

2

1

0

9

8

9

9

9

8

8

R

R

R

R

R

6

5

4

T

N

A

A

A

A

E

E

T

P

N

E

C

R

D

L
3

A

8
6
1

3
9

R
3

A

D

L

L

L

2

1

0

D

D

A

A

A

V

V

3

4

5

6

7

6

6

6

6

6

1

1

1

1

1

8

7

6

5

4

9

9

9

9

9

S

D

R

R

R

2

1

0

S

D

A

A

A

V

V

R

L

R

L

Q

7

7

T

1

1

D

S
S

V

2
6
1

9
9

S
S

V

S

P

D

S

O

O

/

/

O

I

I

V

V

9

0

1

7

8

5

6

6

5

5

1

1

1

1

1

I/O

16L

156

I/O

16R

155

I/O

15L

154

I/O

15R

153

V

SS

152

V

DDQL

151

I/O

14L

150

I/O

14R

149

I/O

13L

148

I/O

13R

147

V

SS

146

V

DDQR

145

I/O

12L

144

I/O

12R

143

I/O

11L

142

I/O

11R

141

V

SS

140

V

DDQL

139

I/O

10L

138

I/O

10R

137

I/O

9L

136

I/O

9R

135

V

SS

134

V

DDQR

133

V

DD

132

V

DD

131

V

SS

130

V

SS

129

V

SS

128

V

DDQL

127

I/O

8R

126

I/O

8L

125

I/O

7R

124

I/O

7L

123

V

SS

122

V

DDQR

121

I/O

6R

120

I/O

6L

119

I/O

5R

118

I/O

5L

117

V

SS

116

V

DDQL

115

I/O

4R

114

I/O

4L

113

I/O

3R

112

I/O

3L

111

V

SS

110

V

DDQR

109

I/O

2R

108

I/O

2L

107

I/O

1R

106

I/O

1L

105

4

3

2

1

0

0

0

0

0

0

1

1

1

1

1

L

R

0

T

O

P

/

I

O

5617 drw 02a

L

S

R
0

Q

S

D

V

O

/

D

I

V

,

Pin Configuration

S
S

06/2 8/02

V

8
0
2

1

I/O

19L

2

I/O

19R

3

I/O

20L

4

I/O

20R

5

V

DDQL

6

V

SS

7

I/O

21L

8

I/O

21R

9

I/O

22L

10

I/O

22R

I/O

I/O

I/O
I/O
V

I/O
I/O

I/O
I/O

V

I/O

I/O
I/O

I/O

I/O

I/O
I/O

I/O
V

I/O

I/O
I/O

I/O

I/O

I/O
I/O

I/O

DDQR

V

DDQL

V

DDQR

V
V
V
V
V

DDQL

V

DDQR

V

DDQL

V

DDQR

V

11
12

SS

13

23L

14

23R

15

24L

24R

16
17
18

SS

25L

19

25R

20

26L

21

26R

22
23

SS

24

DD

25

DD

26

SS

27

SS

28
29

SS

30

27R

31

27L

32

28R

33

28L

34
35

SS

36

29R

37

29L

38

30R

39

30L

40
41

SS

42
43

31R

44

31L

32R

45
46

32L

47
48

SS

49

33R

50

33L

51

34R

52

34L

3
5

S
S

V

V

V

V

V

NOTES:

1. A16 is a NC for IDT70V3589.

2. All VDD pins must be connected to 3.3V power supply.

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).

3. All V

SS pins must be connected to ground supply.

4. All V

5. Package body is approximately 28mm x 28mm x 3.5mm.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

4

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

0L

,

CE

CE

R/W

L

L

OE

0L

- A

16 L

A

0L

- I/O

I/O

L

CLK

L

PL/FT

L

ADS

CNTEN

L

REPEAT

BE0L - BE

V

OPT

1L

(1)

35L

L

3L

DD Q L

CE

0R

,

CE

1R

R/ W

R

OE

R

A0R - A

I/O0R - I/O

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0R - BE

L

V

DD

V

SS

(1 )

16R

35R

R

R

R

R

R

3R

V

DDQR

OPT

R

TDI Test Data Inp ut

TDO Test Data Output

TCK Test Logic Clock (10MHz)

TMS Test Mode Select

TRST

Chip Enables

Read/ Write Enable

Output Enable

Address

Data Input/Outp ut

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat

Byte Enables (9-bit bytes)

Po wer (I/O Bus) (3.3V o r 2.5V)

Op tio n for selecti ng V

Po wer (3.3V)

Ground (0V)

Re se t (Initialize TAP Co ntrol le r)

(5)

(4)

(5)

(2)

NOTES:

(2,3)

DDQX

(2 )

16 is a NC for IDT70V3589.

1. A

2. V

DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

X selects the operating voltage levels for the I/Os and controls on that port.

3. OPT

X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

If OPT
levels and V

DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.

X is asserted, the counter will reset to the last valid address loaded

X.

IH, i.e., the

56 17 tbl 01

4. When REPEAT
via ADS

5. Chip Enables and Byte Enables are double buffered when PL/FT = V
signals take two cycles to deselect.

6.42

5

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control

CE

OE

CLK

CE

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

L

↑

L

↑

L

↑

L

↑

L

↑

L

↑

L

↑

H

↑

1

0

HXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down

XLXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down

L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected

L H H H H L L High-Z High-Z High-Z D

LHHHLHLHigh-ZHigh-Z D

LHHLHHLHigh-Z D

LHLHHHL D

L H H H L L L Hig h-Z Hig h-Z D

LHLLHHL D

LHLLLLL D

L H H H H L H High-Z High-Z High-Z D

LHHHLHHHigh-ZHigh-Z D

LHHLHHHHigh-ZD

LHLHHHH D

LHHHLLHHigh-ZHigh-ZD

LHLLHHH D

LHLLLLH D

LHLLLLXHigh-ZHigh-ZHigh-ZHigh-ZOutputs Disabled

NOTES:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT = V

BE3BE2BE1BE

IH.

Byte 3

R/W

0

I/O

OUT

OUT

OUT

Byte 2

I/O

27-35

IN

IN

IN

18-26

IN

High-Z High-Z High-Z Write to Byte 3 Only

D

IN

D

IN

OUT

High-Z High-Z High-Z Read Byte 3 Only

D

OUT

D

OUT

(1,2,3,4)

Byte 1
I/O

Byte 0

I/O

9-17

IN

0-8

IN

High-Z Write to Byte 1 Only

MODE

Write to Byte 0 Only

High-Z High-Z Write to Byte 2 Only

IN

D

IN

Write to Lower 2 Bytes Only

High-Z High-Z Write to Upper 2 bytes Only

D

IN

OUT

D

IN

Write to All By tes

OUT

Rea d B yte 0 Only

Hig h-Z Rea d B yte 1 Only

High-Z High-Z Read Byte 2 Only

OUT

D

OUT

Rea d Lowe r 2 B yte s Only

High-Z High-Z Read Upper 2 Bytes Only

D

OUT

D

OUT

Read All Bytes

5617 tb l 02

3. OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II—Address Counter Control

External

Addr ess

Internal

Addr ess

XXAn

An X An

An Ap Ap

XApAp + 1↑H L

NOTES:

Previ ous

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE

Internal

Addr ess

Used CLK

ADS CNTEN REPEAT

XX L

↑

(4)

L

↑

↑

XHD

HH H D

(5)

(6)

(4)

HD

(1,2)

(3)

I/O

D

I/O

(0) Counter Reset to last valid ADS load

I/O

(n) External Address Used

I/O

(p) External Address Blocked—Counter disabled (Ap reused)

I/ O

(p+1) Counter Enabled—Internal Address generation

0, CE1, BEn and OE.

MODE

5617 tb l 03

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE

5. The address counter advances if CNTEN = V

IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

0, CE1 and BEn

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

6.42

6

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

DD

Unit

o

o

o

(1)

5617 tbl 04

C

C

C

5617 tbl 06

Temperature and Supply Voltage

Ambient

Grade

Commercial 0OC to +70OC0V3.3V + 150mV

Industrial -40

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

Absolute Maximum Ratings

Symbol Rating Comm ercial

(2 )

TERM

V

(3)

BIAS

T

STG

T

T

JN

I

OUT

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

TERM must not exceed VDD + 150mV for more than 25% of the cycle time or

2. V
4ns maximum, and is limited to

3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.

Terminal Voltage
with Resp ect to GND

Temperature Under Bias -55 to +125

Sto rag e Tempe rature -65 to +150

Junction Temperature +150

DC Outp ut Current 50 mA

Temperature GND V

O

C to +85OC0V3.3V + 150mV

(1)

& Industrial

-0.5 to +4.6 V

< 20mA for the period of VTERM > VDD + 150mV.

Recommended DC Operating
Conditions with V

Symbol Parameter Min. Typ. Max. Unit

DD

Core Sup ply Voltage 3.15 3.3 3.45 V

V

DDQ

I/O S upply Voltage

V

SS

Ground 0 0 0 V

V

Input Hig h Vo lta ge

IH

V

(Ad dre ss & Co ntrol Inp uts)

V

IH

Input High Voltage - I/O

IL

Input Lo w Voltag e -0. 3

V

NOTES:

1. Undershoot of V

TERM must not exceed VDDQ + 100mV.

2. V

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
as indicated above.

IL > -1.5V for pulse width less than 10ns is allowed.

DDQ at 2.5V

(3 )

2.4 2.5 2.6 V

____

V

DDQ

V

DDQ

+ 100mV

+ 100mV

0.7 V

1.7

(3)

IL (0V), and VDDQX for that port must be supplied

1.7

____

(1)

____

(2 )

(2 )

5617 tb l 05a

V

V

Recommended DC Operating
Conditions with V

Symbol Parameter Min. Typ. Max. Unit

DD

Core Supply Voltage 3.15 3.3 3.45 V

V

V

DDQ

I/O Supply Voltage

SS

Ground 0 0 0 V

V

Inp ut Hig h Vo ltage

IH

V

(Address & Control Inputs)

IH

Inp ut Hig h Vo ltage - I/O

V

V

IL

Input Lo w Voltage -0.3

NOTES:

1. Undershoot of V

TERM must not exceed VDDQ + 150mV.

2. V

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
supplied as indicated above.

IL > -1.5V for pulse width less than 10ns is allowed.

DDQ at 3.3V

(3)

3.15 3. 3 3. 45 V

____

2.0

(3)

(3)

2.0

(1)

IH (3.3V), and VDDQX for that port must be

V

DDQ

+ 150mV

____

V

DDQ

+ 150mV

____

0.8 V

(2)

(2)

5617 tbl 05b

V

V

6.42

7

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Capacitance

(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions

C

IN

Input Capacitance VIN = 3dV 8 pF

(3)

C

OUT

Outp ut Capacitance V

NOTES:

1. These parameters are determined by device characterization, but are not
production tested.

2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.

OUT also references CI/O.

3. C

(2)

Max. Unit

OUT

= 3dV 10.5 pF

5617 tbl 07

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

LI

| Input Le akage Current

|I

LO

| Output Leak age Current

|I

OL

(3.3V) Output Lo w Voltage

V

OH

(3.3V) Output High Voltage

V

OL

(2.5V) Output Lo w Voltage

V

OH

(2.5V) Output High Voltage

V

NOTE:

DD < 2.0V leakages are undefined.

1. At V

DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

2. V

(1)

(1)

(2)

(2)

(2)

(2)

V

DDQ

= Max., VIN = 0V to V

CE0 = VIH or CE1 = VIL, V

IOL = +4mA, V

IOH = -4mA, V

IOL = +2mA, V

IOH = -2mA, V

DDQ

= Min.

DDQ

= Min. 2.4

DDQ

= Min.

DDQ

= Min. 2.0

(VDD = 3.3V ± 150mV)

DDQ

OUT

= 0V to V

DDQ

70V3599/89S

___

___

___

___

10 µA

10 µA

0.4 V

___

0.4 V

___

5617 tbl 0 8

UnitMin. Max.

V

V

6.42

8

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(3)

Temperature and Supply Voltage Range

Symbol P arameter Test Condition Versi on Typ.

DD

Dynami c Operating

I

Current (Both
Ports Active)

SB1

Standby Current

I

(Both Ports - TTL
Lev el Inputs)

I

SB2

Standby Current
(One Po rt - TTL
Lev el Inputs)

I

SB3

Full Standby Curre nt
(Both Ports - CMOS
Lev el Inputs)

I

SB4

Full Standby Curre nt
(One Po rt - CMOS
Lev el Inputs)

NOTES:

1. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

4. V

X = VIL means CE0X = VIL and CE1X = VIH

5. CE

CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V

CE

"X" represents "L" for left port or "R" for right port.

L

and CER= VIL,

CE

Outputs Disabled,

(1)

MAX

f = f

L

= CER = V

CE

Outputs Disabled,
f = f

MAX

CE

"A"

= VIL and CE
Active Port Outputs Disabled,
f=f

MAX

IH ,

(1)

(5)

"B"

= V

IH

(1)

Both Ports Outputs Disabled

CE

L

and CER > VDD - 0.2V,

V

IN

> VDD - 0.2V

or V

IN

< 0.2V, f = 0

CE

"A"

< 0.2V and CE

(2)

"B"

> VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = f

MAX

(5)

(1)

(VDD = 3.3V ± 150mV)

COM' L S 370 500 320 400

IND S

COM'L S 125 200 115 160

IND S

COM' L S 250 350 220 290

IND S

COM' L S 15 30 15 30

IND S

COM' L S 250 350 220 290

IND S

70V3599/89S166

Com'l Only

(4)

Max. Typ.

____ ____

____ ____

____ ____

____ ____

____ ____

70V3599/89S133

Com 'l

& Ind

(4)

Max. Unit

320 480

115 195

220 350

15 40

220 350

mA

mA

mA

mA

mA

5617 tb l 09

6.42

9

IDT70V3599/89S

,

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ - 3.3V/2.5V)

Input Pulse Levels (Address & Controls)

Inp ut Pul se Level s (I/ Os )

Inp ut Ris e /Fall Times

Inp ut Timing Reference Level s

Output Reference Levels

Output Lo ad

50Ω

DATA

OUT

Figure 1. AC Output Test load.

.

GND to 3

0V/GND to 2.4V

GND to 3.0V/GND to 2.4V

2ns

1.5V/1.25V

1.5V/1.25V

Fig ures 1 and 2

5617 tbl 10

50Ω

10pF
(Tester)

1.5V/1.25

5617 drw 03

DATA

DATA

OUT

770Ω

OUT

435Ω

Figure 2. Output Test Load

CKLZ, tCKHZ, tOLZ, and tOHZ).

(For t

*Including scope and jig.

2.5V

833Ω

3.3V

590Ω

5pF*

5617 drw 04

5pF*

,

,

∆tCD
(Typical, ns)

10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.

7
6

5
4

3
2

1

•

•

•

•

20.5

-1

Figure 3. Typical Output Derating (Lumped Capacitive Load).

50 80 100 200

30

Capacitance (pF)

,

5617drw 05

6.42

10

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(2,3)

(Read and Write Cycle Timing)

Symbol Parameter Min. Max. Min. Max. Unit

t

CYC1

t

CYC2

CH1

t

CL1

t

CH2

t

CL2

t

t

SA

HA

t

t

SC

HC

t

SB

t

HB

t

SW

t

HW

t

SD

t

t

HD

SAD

t

HAD

t

SCN

t

t

HCN

SRPT

t

HRPT

t

OE

t

OLZ

t

OHZ

t

t

CD1

CD2

t

DC

t

CKHZ

t

CKLZ

t

Clock Cycle Time (Flow-Through)

Clock Cycle Time (Pipelined)

Cloc k Hig h Time (Flow-Through)

Clo ck Lo w Time (F lo w-Throu gh)

Clock High Time (Pipelined)

Clock Low Time (Pipelined)

Address Setup Time 1.7

Address Hold Time 0.5

Chip Enable Setup Time 1.7

Chip Enable Hold Time 0.5

Byte Enable Setup Time 1.7

Byte Enable Hold Time 0.5

R/W Se tup Tim e 1.7

R/W Hold Time 0.5

Input Data Se tup Time 1.7

Input Data Hold Time 0.5

ADS Setup Time

ADS Hold Time

CNTEN Setup Time

CNTEN Hold Time

REPEAT Setup Time

REPEAT Hold Time

Output Enable to Data Valid

Output Enable to Output Low-Z 1

Output Enable to Output High-Z 1 3.6 1 4.2 ns

Clock to Data Valid (Flow-Through)

Clock to Data Valid (Pipelined)

Data Outp ut Ho ld Afte r Cl ock Hig h 1

Clo ck Hi gh to Output High-Z 1 3 1 3 ns

Clo ck Hi gh to Output Lo w-Z 1

Port-to-Port Delay

CO

t

Clock-to-Clock Offset 5

NOTES:

1. The Pipelined output parameters (t

FT/PIPE = V

IL for that port.

CYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a

DC signal, i.e. steady state during operation.

3. These values are valid for either level of V

(1)

(1)

(1)

(1)

(2)

(1)

(1)

(1)

DDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.

(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)

70V3599/89S166

Com'l Only

20

6

6

6

2.1

2.1

1.7

0.5

1.7

0.5

1.7

0.5

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

4.0

____

12

3.6

____

____

____

70V3599/89S133

Com 'l
& Ind

25

7.5

7

7

2.6

2.6

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

____

1

____

____

1

1

6

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

4.2 ns

____

15 ns

4.2 ns

____

____

____

5617 tbl 11

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

6.42

11

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE

CLK

CE

0

CE

1

BE

n

R/

W

ADDRESS

DATA

OUT

OE

'X' = VIH)

tSCt

t

t
tSAt

(4)

(1)

(2)

t

CYC2

t

CH2

HC

t

HB

SB

t

HW

SW

HA

An An + 1 An+ 2 An + 3

(1 Latency)

t

CKLZ

t

CL2

tSCt

(3)

tSBt

HB

(5)

t

t

CD2

(1)

DC

Qn Qn + 1 Qn + 2

t

OHZ

HC

(5)

t

OLZ

t

OE

5617drw 06

Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE

"X" = VIL)

CLK

CE

0

CE

1

BEn

R/

W

OUT

OE

(4)

(1)

ADDRESS

DATA

NOTES:

1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

2. ADS = V

IL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = V

are for reference use only.

n was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

5. If BE

6. "x" denotes Left or Right port. The diagram is with respect to that port.

(2,6)

t

CYC1

t

CH1

tSCt

HC

tSBt

HB

t

SW

t

HW

tSAt

HA

An An + 1 An + 2 An + 3

t

CKLZ

t

CL1

tSCt

t

t

t

CD1

DC

Qn Qn + 1 Qn + 2

t

OHZ

0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to

IL constantly loads the address on the rising edge of the CLK; numbers

t

OLZ

t

OE

(3)

SB

HC

t

HB

t

CKHZ

(5)

t

DC

5617drw 07

6.42

12

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of a Multi-Device Pipelined Read

t

CYC2

t

CH2

t

CL2

(1,2)

CLK

tSAt

HA

A

ADDRESS

CE

DATA

OUT(B1)

ADDRESS

CE

(B1)

0(B1)

(B2)

0(B2)

tSCt

tSAt

tSCt

A

A

A

A

tSCt

Q

A

tSCt

2

HC

t

CD2

0

t

DC

2

HC

A

0

HC

HA

A

0

HC

A

1

t

CD2

A

1

3

t

CKHZ

Q

1

t

DC

A

3

4

t

CD2

t

CKLZ

A

4

5

Q

3

t

CKHZ

A

5

6

A

6

DATA

OUT(B2)

t

CKLZ

t

CD2

t

CKHZ

Q

2

Timing Waveform of a Multi-Device Flow-Through Read

t

CYC1

t

CH1

t

CL1

CLK

tSAt

HA

A

A

ADDRESS

CE

DATA

OUT(B1)

ADDRESS

CE

DATA

OUT(B2)

(B1)

0(B1)

(B2)

0(B2)

A

tSCt

tSAt

A

tSCt

A

tSCt

D

A

tSCt

2

HC

(1)

t

CKHZ

1

t

DC

2

HC

t

CD1

(1)

t

CKLZ

0

HC

t

CD1

HA

0

HC

A

1

t

CD1

D

0

t

DC

A

1

3

t

CD1

(1)

t

CKLZ

A

3

(1)

t

CKHZ

D

2

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3599/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS

n, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

2. BE

(B1) = ADDRESS(B2) in this situation.

4

D

3

t

CKHZ

A

4

t

t

CKLZ

(1,2)

(1)

CD1

(1)

t

CD2

Q

5617 drw 08

(1)

4

A

6

D

5

A

6

t

CKLZ

A

5

t

CD1

(1)

t

CKLZ

A

5

t

CKHZ

D

4

5617 drw 09

6.42

13

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Left Port Write to Pipelined Right Port Read

CLK

"A"

tSWt

HW

R/W

"A"

tSAt

HA

ADDRESS

DATA

CLK

R/W

ADDRESS

IN"A"

"A"

"B"

"B"

"B"

MATCH

tSDt

VALID

tSWt

tSAt

MATCH

HD

(3)

t

CO

HW
HA

NO

MATCH

t

CD2

NO

MATCH

(1,2,4)

DATA

OUT"B"

NOTES:

0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

1. CE

2. OE = V

3. If t

IL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.

CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port

t

CO + tCYC2 + tCD2).

will be t

VALID

t

DC

5617drw 10

4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

t

CD1

(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read

CLK

"A"

tSWt

HW

R/W

"A"

tSAt

HA

ADDRESS

DATA

CLK

R/W

ADDRESS

IN "A"

"A"

"B"

"B"

"B"

MATCH

tSDt

VALID

t
t

MATCH

SW
SA

HD

(3)

t

CO

t

CD1

t

HW

t

HA

NO

MATCH

MATCH

NO

DATA

OUT "B"

t

DC

NOTES:

0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

1. CE

2. OE = V

3. If t

IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

CO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will

t

CO + tCD1).

be t

VALID

VALID

t

DC

5617 drw 11

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

14

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = V

IL)

(2)

CLK

CE

0

tSCt

CE

1

tSBt

BE

n

R/

ADDRESS

DATA

DATA

OUT

W

IN

tSWt

(3)

tSAt

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

0, BEn , and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

2. CE

3. Addresses do not have to be accessed sequentially since ADS = V
are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

t

CYC2

t

CH2tCL2

HC

HB

tSWt

HW

HW

An An +1 An + 2 An + 2

HA

t

SD

t

Dn + 2

t

(1)

CD2

t

CKHZ

Qn

READ NOP READ

IL constantly loads the address on the rising edge of the CLK; numbers

(4)

HD

WRITE

An + 3 An + 4

CKLZ

t

t

CD2

Qn + 3

5617drw 12

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

t

CYC2

t

CH2tCL2

CLK

CE

0

tSCt

HC

CE

1

tSBt

HB

BE

n

tSWt

HW

R/

W

ADDRESS

DATA

IN

DATA

OUT

OE

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. CE

3. Addresses do not have to be accessed sequentially since ADS = V

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

tSWt

HW

(3)

An An +1 An + 2 An + 3

tSAt

HA

t

(1)

CD2

Qn

t

OHZ

tSDt

(4)

HD

Dn + 3Dn + 2

READ WRITE READ

IL constantly loads the address on the rising edge of the CLK; numbers are for reference

An + 4

t

CKLZ

An + 5

t

CD2

Qn + 4

5617 drw 13

(2)

6.42

15

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)

t

CYC1

t

CH1tCL1

(2)

CLK

CE

0

tSCt

HC

CE

1

tSBt

HB

BEn

tSWt

HW

R/

W

tSWt

HW

ADDRESS

DATA

DATA

OUT

(3)

IN

(1)

An

tSAt

An +1 An + 2 An + 2

HA

tSDt

HD

An + 3

Dn + 2

t

CD1

Qn

READ

t

CD1

t

CD1

Qn + 1

t

DC

t

NOP

CKHZ

(5)

WRITE

t

CKLZ

An + 4

Qn + 3

READ

t

CD1

t

DC

6517drw 14

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)

t

CYC1

t

CH1

t

CL1

CLK

CE

0

tSCt

HC

CE

1

tSBt

HB

BEn

tSWt

HW

tSWt

R/

W

HW

(2)

ADDRESS

DATA

DATA

OUT

(3)

IN

(1)

An

tSAt

HA

t

t

CD1

DC

tSDt

Dn + 2

HD

Dn + 3

An +1 An + 2 An + 3

An+ 4

t

OE

t

CD1

Qn

t

t

OHZ

CKLZ

An + 5

Qn + 4

t

t

DC

OE

READ WRITE READ

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. CE

3. Addresses do not have to be accessed sequentially since ADS = V

IL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

16

CD1

5617drw 15

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read with Address Counter Advance

t

CYC2

t

CH2tCL2

(1)

CLK

tSAt

HA

ADDRESS An

t

SADtHAD

ADS

t

SADtHAD

CNTEN

DATA

OUT

Qx - 1

(2)

READ

EXTERNAL

ADDRESS

Qx

t

CD2

Qn

t

DC

READ WITH COUNTER

t

SCNtHCN

Qn + 1

COUNTER

HOLD

Qn + 2

(2)

READ
WITH

COUNTER

Qn + 3

5617 drw 16

Timing Waveform of Flow-Through Read with Address Counter Advance

t

CYC1

t

CH1tCL1

CLK

tSAt

HA

ADDRESS

ADS

CNTE N

An

t

SADtHAD

t

SADtHAD

t

SCNtHCN

(1)

t

CD1

(2)

DATA

OUT

Qx

t

DC

READ

EXTERNAL

ADDRESS

NOTES:

0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.

1. CE

2. If there is no address change via ADS = V

IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

Qn

Qn + 1 Qn + 2

Qn + 3

READ WITH COUNTER COUNTER

HOLD

6.42

17

(2)

Qn + 4

READ
WITH

COUNTER

5617drw17

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)

t

CYC2

t

CH2tCL2

CLK

tSAt

HA

ADDRESS

An

(1)

INTERNAL
ADDRESS

ADS

CNTEN

DATA

(3)

t

SADtHAD

tSDt

HD

IN

Dn

WRITE

EXTERNAL

ADDRESS

An

(7)

t

SCNtHCN

Dn + 1

WRITE

WITH COUNTER

An + 1

Dn + 1 Dn + 2

WRITE

COUNTER HOLD

Timing Waveform of Counter Repeat

t

CYC2

t

CH2tCL2

CLK

ADDRESS

INTERNAL
ADDRESS

(3)

Ax

R/

W

LAST ADS LOAD

tSWt

HW

(2)

An + 2

tSAt

LAST ADS +1

An + 3

Dn + 3

Dn + 4

WRITEWITHCOUNTE R

HA

An

(4)

An + 1

An An+ 1

An + 4

5617drw18

An + 2

ADS

CNTEN

t

SRPT

t

HRPT

REPEAT

DATA

IN

(5)

DATA

OUT

EXECUTE

NOTES:

1. CE

0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
0, BEn = VIL; CE1 = VIH.

CE

2.

3. The "Internal Address" is equal to the "External Address" when ADS = V

4. Addresses do not have to be accessed sequentially since ADS = V

REPEAT

t

SADtHAD

t

SCNtHCN

t

SD

D

(6)

t

HD

0

LAST ADS
ADDRESS

WRITE

Q

Q

LAST

READ
LAST ADS
ADDRESS

IL and equals the counter output when ADS = VIH.

IL constantly loads the address on the rising edge of the CLK; numbers are for reference

READ

LAST AD S

ADDRESS + 1

READ

ADDRESSn

LAST+1

READ

ADDRESS n+1

Qn

5617 drw 19

use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.

7. CNTEN = V

IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6.42

18

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V3599/89 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.

An asynchronous output enable is provided to ease asyn­chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3599/89s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.

(1)

A17/A

16

IDT70V3599/89

Control Inputs

CE

CE

0
1

Depth and Width Expansion

The IDT70V3599/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.

The IDT70V3599/89 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 72-bits or wider.

IDT70V3599/89

V

DD

Control Inputs

CE

CE

0
1

V

DD

NOTE:

1. A

17 is for IDT70V3599, A16 is for IDT70V3589.

IDT70V3599/89

CE

CE

1
0

Control Inputs

Figure 4. Depth and Width Expansion with IDT70V3599/89

IDT70V3599/89

Control Inputs

CE

1

CE

0

5617 drw 20

BE,
R/W,
OE,
CLK,

ADS,
REPEAT,
CNTEN

6.42

19

IDT70V3599/89S

,

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

JTAG Timing Specifications

t

JCYC

t

t

JCL

JR

t

JCH

TCK

t

JF

Device Inputs

(1)

/

TDI/TMS

t

JStJH

(2)

TDO

/

t

JRSR

Device Outputs

TRST

t

JRST

Figure 5. Standard JTAG Timing

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical
Characteristics

Symbol Parameter Min. Max. Units

JCYC

t

JCH

t

JCL

t

JR

t

JF

t

JRST

t

JRSR

t

JCD

t

JDC

t

JS

t

JH

t

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.

JTAG Clock Input Period 100

JTAG Clock HIGH 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data Output

JTAG Data Output Ho ld 0

(1,2,3,4)

JTAG Clock Low 40

____

____

JTAG Reset 50

____

JTAG Setup 15

JTAG Hold 15

70V3599/89

____

____

____

(1)

3

(1)

3

____

____

25 ns

____

____

____

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

5617 tbl 12

t

JDC

t

JCD

5617 drw 21

6.42

20

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Fi eld Value Description

Revision Number (31:28) 0x0 Reserved for version number

IDT Device ID (27:12)

0x0312

(1)

Defines IDT part numb er

IDT JEDEC ID (11:1) 0x33 Allows unique identif ication of device vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

NOTE:

1. Device ID for IDT70V3589 is 0x0313.

5617 tbl 13

Scan Register Sizes

Register Name Bit Size

Instruction (IR) 4

Bypass (BYR) 1

Identific ati o n (IDR) 32

Boundary Scan (BSR) Note (3)

5617 tbl 14

System Interface Parameters

Instruction Code Description

EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs

Places the boundary scan registe r (BSR) be tween TDI and TDO.

BYPA SS 1111 P l aces the by p ass registe r (BY R) b e twe en TDI a nd TDO .

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ

0011 Places the bypass register (BYR) between TDI and TDO. Forces all

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

RESERVED All othe r codes Sev eral co mbinations are reserv ed. Do no t use cod e s o ther than thos e

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.

register between TDI and TDO.

device output drivers to a High-Z state.

(2)

SAMPLE allows data from device inputs

to be captured in the
boundary scan cells and shifted se rially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.

identified above.

5617 tbl 15

(1)

.

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IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

BlankICommercial (0°C to +70°C)

BF
DR
BC

166
133

S Standard Power

70V3599
70V3589

Industrial (-40°C to +85°C)

208-pin fpBGA (BF-208)
208-pin PQFP (DR-208)
256-pin BGA (BC-256)

Commercial Only
Commercial & Industrial

4Mbit (128Kx 36-Bit)SynchronousDual-Port RAM
2Mbit (64K x 36-Bit) Synchronous Dual-Port RAM

Speed in Megahertz

5617 drw 22

IDT Clock Solution for IDT70V3599/89 Dual-Port

Dual-Port I/O Specitications Clock Specifications

IDT Dual-Por t

Part Number

Voltage I/O

Input

Capacitance

70V3599/89 3.3/2.5 LVTTL 8pF 40% 166 75ps IDT5V2528

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Input Duty

Cycle

Requirement

Maximum

Frequency

Jitter

Tolerance

Clock Device

IDT
PLL

5617 tbl16a

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Datasheet Document History:

6/2/00: Initial Public Offering
7/12/00: Added mux to functional block diagram
7/30/01: Page 20 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns

Page 9 Added Industrial Temperature DC Parameters

11/20/01: Page 2, 3 & 4 Added date revision for pin configurations

Page 11 Changed t
Page 1 & 22 Replaced TM logo with ® logo
Page 10 Changed AC Test Conditions Input Rise/Fall Times

7/1/02: Consolidated multiple devices into one datasheet

Page 1 & 5 Added DCD capability for Pipelined Outputs
Page 7 Clarified T
Page 9 Changed DC Electrical Parameters
Page 11 Removed Clock Rise & Fall Time from AC Electrical Characteristics Table
Removed Preliminary status

05/19/03: Page 11 Added Byte Enable SetupTime & Byte Enable Hold Time to AC Elecctrical Characteristics Table

Page 22 Added IDT Clock Solution Table

OE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05

BIAS and added TJN

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: [phone] [e-mail]

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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