Datasheet IDT70V3379S Datasheet (IDT)

查询IDT70V3379S供应商

HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous access of the same memory location

◆

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.) – Industrial: 5/6ns (max)

◆

Pipelined output mode

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without additional logic

◆

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and

Functional Block Diagram

L

UB

IDT70V3379S

address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus matching compatibility

◆

LVTTL- compatible, single 3.3V (±150mV) power supply for core

◆

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port

◆

Industrial temperature range (-40°C to +85°C) is available for selected speeds

◆

Available in a 128-pin Thin Quad Plastic Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array

R

UB

R

CE

OE

LB

R

W

R/

0R 1R

R

L

LB

L

W

R/

0L

CE

1L

CE

L

OE

B

W

0

1

L

Dout0-8_L Dout9-17_L

B

W

1

0

R

Dout0-8_R

Dout9-17_R

32K x 18

MEMORY

ARRAY

,

.

17R

R

CLK

R

CLK

I/O0L-I/O

L

A

14L

A

CNTRST

ADS

CNTEN

17L

0L

L L L

Counter/

Address

Reg.

Din_L

ADDR_L

Din_R

ADDR_R

Counter/ Address

Reg.

I/O0R-I/O

A

14R

A

0R

CNTRST ADS

CNTEN

4833 tbl 01

APRIL 2001

1

DSC 4833/8

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V3379 is a high-speed32K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3379 has been optimized for applications having unidirectional or bidirectional data flow

in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.

The 70V3379 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V

DD) remains at 3.3V.

Pin Configuration

21

I/O

9L

NC

SS

V

NC

V

NC

SS

I/O9RV

V

SS

NC

11R

I/O

SS

V

NC

V

DD

V

SS

14LVDDQR

DDQRVDD

I/O

10L

DDQR

V

NC V

12L

V

DDQR

V

SS

I/O

13R

DDQL

V

NC

11L

I/O

DDQL

V

NC I/O

V

DD

V

DDQL

I/O

14R

NC I/O

(1,2,3,4)

9876543

A

NC

NC OPT

NC

V

SS

NC

A

I/O

NC

10R

SS

12L

A

9L

13L

A

14L

10L

A

11L

7L

A

UB

A

NC

LB

NC

8L

CE

0L

L

1L

CE

DD

V

L

NC

I/O

12R

70V3379BF

BF-208

SS

V

208-Pin fpBGA

Top View

I/O

SS

V

13L

10

(5)

V

OE

(6)

11

DD

L

CNTEN

CLK

SS

ADS

L

5L

A

SS

R/

L

CNTRST

6L

A

L

W

3L

A

L

1412 13

15

A

4L

A

V

SS

1L

A

DD

V

2L

A

NC

DD

V

I/O

SS

V

NC

DD

V

SS

I/O

NC

L

0L

V

DDQR

8R

I/O

DDQL

V

6L

6R

I/O

V

DDQL

NC

V

DD

3R

V

DDQL

3L

I/O

NC

V

NC

V

1716

V

SS

A

NC

8L

7L

SS

5L

SS

4R

SS

V

I/O

NCNC

I/O

V

I/O

SS

DDQR

NC

DDQR

SS

B C

7R

D E

F G

5R

H J K

4L

L

DDQL

I/O

V

NC

16R

SS

V

NC

SS

V

I/O

NC

V

NC

I/O

15R

V

SS

16L

V

I/O

17L

V

NC

DDQR

DDQL

V

15L

I/O

8R

A

12R

NC

V

NC

SS

NC

17R

DD

13R

A

14RA10R

A

11R

A

9R

A

7R

A

UB

NC

DD

V

0R

CE

NC

R

LB

CE

V

SS

1R

SS

V

DD

V

OE

R

CLK

ADS

W

R/

CNTRST

R

CNTEN

R

A

5R

6R

A

R

3R

R

A

SS

NC

V

DDQL

V

1R

I/O

1L

I/O

NC

A

4R

V

DDQL

V

SS

A

1R

SS

NC

V

2R

A

DD

V

0R

A

OPT

R

NOTES:

DD pins must be connected to 3.3V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

2. All V

3. All V

IL (0V).

set to V

SS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

2

I/O

V

I/O

NC

V

NC

2R

DDQR

V

M

2L

I/O

N

NC

SS

0R

SS

DDQR

V

NC

0L

I/O

4833 tbl 02

P R T U

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

A2

A1

NC

B1

NC

C1

NC

D1

NC

E1

I/O

10R

F1

I/O

11L

G1

NC

H1

NCH2I/O

J1

I/O

13L

K1

NC

L1

I/O

15L

M1

I/O

16R

N1NCN2

P1

NCP2I/O

R1NCR2NCR3NCR4

T1

NC

B2

NC

C2

I/O

9L

D2

I/O

9R

E2

I/O

10L

F2

NCF3I/O

G2

NC

12R

J2

I/O

14R

K2

NC

L2

NC

M2

I/O

16L

17R

I/O

17L

T2NCT3

A3

NC

B3

NC

C3

V

SS

D3

NC

E3

NCE4V

11R

G3

12L

I/O

H3NCH4

J3

I/O

13R

K3

14L

I/O

L3

I/O

15R

M3

NCM4V

N3

NC

P3

NCP4NC

NC

A4

B4

C4

D4

F4

V

G4

V

J4

V

K4

V

L4

V

N4

T4

NC

V

DD

DDQL

DDQR

DDQL

DDQR

DD

V

NC

A5

B5

C5

D5

V

E5

F5

G5

H5

J5

K5

L5

M5

N5

V

P5

R5

T5

A

14L

NC

A

DDQL

V

DDQR

A

13R

NC

A

13L

DD

SS

DD

14R

A6

A

B6

C6

D6

V

E6

F6

G6

H6

J6

K6

L6

M6

N6

V

P6

R6

T6

11L

A

DDQL

V

DDQR

A

12R

A

12L

10L

DD

SS

DD

10R

11R

70V3379BC

BC-256

256-Pin BGA

Top View

A8

A7

B7

C7

D7

V

E7

F7

G7

H7

J7

K7

L7

M7

N7

V

P7

R7

T7

A

8L

A

9L

A

7L

DDQR

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQL

A

7R

A

9R

8R

A

B8

C8

D8

V

E8

F8

G8

H8

J8

K8

L8

M8

N8

V

P8

R8

T8

NC

UB

NC

DDQR

V

SS

V

SS

V

DDQL

NC

UB

NC

SS

(5)

(6)

A14

A10

B10

R/

C10

CLK

D10

V

E10

F10

G10

H10

J10

K10

L10

M10

N10

V

P10

CLK

R10

R/

T10

OE

W

DDQL

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQR

W

OE

L

R

A11

CNTEN

B11

CNTRST

C11

ADS

D11

V

DDQR

E11

V

DD

F11

V

SS

G11

SS

V

H11

V

SS

J11

V

SS

K11

V

SS

L11

V

SS

M11

V

DD

N11

DDQL

V

P11

ADS

R11

CNTRST

T11

CNTEN

L

R

A9

CE

1L

B9

CE

0L

L

C9

LB

L

D9

V

DDQL

E9

V

SS

F9

V

SS

G9

V

SS

H9

V

SS

J9

V

SS

K9

V

SS

L9

V

SS

M9

V

SS

N9

DDQR

V

P9

LB

R

R9

CE

R

0R

T9

1R

CE

A12

B12

C12

D12

V

E12

F12

G12

H12

J12

K12

L12

M12

N12

V

P12

R12

T12

A

DDQR

V

DD

SS

V

SS

V

SS

V

SS

V

DD

V

DD

DDQL

A

DD

6R

4R

5R

A13

A

5L

B13

4L

C13

6L

D13

V

E13

V

DDQR

F13

V

DDQR

G13

V

H13

V

DDQL

J13

V

DDQR

K13

V

L13

V

M13

V

N13

V

P13

A

R13

A

T13

A

2L

A

1L

A

3L

DD

DDQL

DDQR

DDQL

DD

3R

1R

2R

B14

V

C14

OPT

D14

NC

E14

F14

I/O

G14

I/O

H14

NC

J14

I/O

K14

NC

L14

I/O

M14

I/O

N14

NC

P14

R14

OPT

T14

A

0L

DD

L

NC

6R

5L

4R

2L

1R

NC

R

0R

A16

A15

NC

B16

B15

NC

C16

C15

NC

D16

D15

NC

E15

I/O

7L

F15

F16

NC

G16

G15

NC

H16

H15

NC

J16

J15

I/O

3R

K16

K15

NC

L15

L16

NC

M16

M15

I/O

1L

N16

N15

0R

I/O

P15

P16

NC

R16

R15

NC

T15NCT16

I/O

E16

I/O

NC

I/O

NC

I/O

NC

8L

8R

7R

6L

5R

4L

3L

2R

0L

,

NOTES:

DD pins must be connected to 3.3V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

2. All V

3. All V

IL (0V).

set to V

SS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

3

4833drw 02c

,

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

V

A

IO

DDQL

V

IO

DDQR

IO

DDQL

IO

DDQR

V

IO

A

(1,2,3,4)

14L

NC

V

SS

NC

9L

9R

SS

10L 10R

V

SS

11L 11R 12L 12R

V

DD

V

DD

V

SS

V

SS

13R

13L 14R

14L 15R

15L

V

SS

16R

16L

SS 17R

17L

NC NC NC

14R

(con't.)

L

3

2

1

A

8

7

2

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

9

0

38

3

4

L

T S

N

L

E

L

0

L

1 1

A

6

2

1

L

1

9

8

7

A

5

4

3

2

1

L

1

0

D

L

B

E

D

B

U

L

C

V

1

0

9

8

2

1

7

2

1

L

K

D

S

E

L

D

S

V

6

1

O

V

C

5

4

3

2

1

70V3379PRF

PK-128

(5)

128-Pin TQFP

Top View

1

4

2

3

5

6

7

8

4

9

4

(6)

0

1

4

2

3

5

R

L

T

S

L

W

N

/ R

1

5

6

D A

C

A

0

9

8

7

1

0

1

6

7

8

9

5

L

5

4

3

2

A

6

5

4

3

0

102

1

101

100

85

82

78

76

74

0

1

2

3

6

4

6

A

1L

A

0L

OPT

L

SS DDQL

7L

7R SS DDQR

DD DD SS SS

SS DDQL

SS DDQR

OPT

0R 1R

(7)

8L 8R

(7)

6L 6R 5L 5R

4R 4L 3R 3L 2R 2L

1R 1L

0R 0L

R

99

NC (VSS) IO

98 97

IO NC (VSS)

96

V

95

V

94

IO

93

IO

92 91

V

90

V

89

IO

88

IO

87

IO

86

IO V V

84

V

83

V

81

IO

80

IO

79

IO IO

77

IO IO

75

V V

73

IO

72

IO

71

V

70

V

69

IO

68

IO 67 66

A 65

A

Pin Configuration

.

S

R

R 3 1

A

R

2

1

0

9

1

A

R

8

7

A

R

1

0

B

E

L

U

C

NOTES:

DD pins must be connected to 3.3V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

2. All V

3. All V

IL (0V).

set to V

SS pins must be connected to ground supply.

4. Package body is approximately 14mm x 20mm x 1.4mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is needed, the pins can be treated as NC.

S

R

D

S

D

V

E

K

V

L

O

C

R

6

5

4

T

S

N

W

/

S

E

D

R

T

R

A

T

N

C

3

A

2

A

4833 drw 02a

6.42

4

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

0L

CE

,

L

W

R/

L

OE

0L

- A

A I/O0L - I/O

L

CLK

L

ADS

CNTEN

CNTRST

L

- LB

UB

V

14L

L

DDQL

OPT

1L

17L

L

CE

R/

OE

A0R - A I/O0R - I/O CLK

ADS

CNTEN

CNTRST

UBR - LB

DD

V

SS

V

0R

1R

CE

,

R

W

R

14R

17R

R

DDQR

V

OPT

Chip Enables Read/ Write Enab le Output Enable Address Data In pu t/O utp ut Clock Address Strobe Enable Co unte r En ab l e Coun te r Re se t Byte Enables (9-bit bytes) Po we r (I/O Bus ) (3.3V or 2.5V )

R

Op tio n fo r se l e ct ing V Po we r (3.3V ) Ground (0V)

NOTES:

DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

1. V applying inputs on the I/Os and controls for that port.

(1)

(1,2)

DDQX

(1)

X selects the operating voltage levels for the I/Os and controls on that port.

2. OPT

X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

If OPT levels and V port's I/Os and controls will operate at 2.5V levels and V

DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

DDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

48 33 tb l 01

with the other at 2.5V.

Truth Table IRead/Write and Enable Control

OE

CLK

X X X X

H

↑ ↑ ↑ ↑

L

↑

L

↑

L

↑ ↑

0

CE

L H H H X High-Z High-Z All By tes Des ele c ted LHHL LHigh-Z D LHLHL DINHigh-Z Write to Upper Byte Only LHLLL D LHHLHHigh-Z D LHLHH D LHLLHD L H L L X H ig h-Z Hig h-Z Outp uts Dis ab le d

CE

1

NOTES:

1. "H" = V

2. ADS, CNTEN, CNTRST = V

IH, "L" = VIL, "X" = Don't Care.

IH.

3. OE is an asynchronous input signal.

UB LB

R/

W

Upper Byte

I/O

9-18

IN

OUT

Lower Byte

0-8

I/O

IN

D

OUT

Hig h-Z Read Upp e r By te Onl y

OUT

D

(1,2,3)

MODE

Write to Lower Byte Only

Wri te to B o th B y te s

Read Lo wer By te Only

Read Both Bytes

4833 t bl 02

6.42

5

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Truth Table IIAddress Counter Control

Address

XX0↑XX L An X An An Ap Ap

XApAp + 1↑H L

NOTES:

IH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE

Addr Used CLK

(6)

ADS CNTEN CNTRST

(4)

L

↑ ↑

XHD

HH H D

(5)

(4)

HD

(1,2)

(3)

I/O

D

(0) Counter Reset to Address 0

I/O

(n) External Address Used

I/O

(p) External Address Blocked—Counter disabled (Ap reused)

I/O

(p+1) Counter Enable d —Internal Address generation

0, CE1, BEn and OE.

MODE

4833 tbl 03

3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other memory control signals including CE

5. The address counter advances if CNTEN = V

IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

0, CE1 and BEn

Recommended Operating

DD

(1,2)

4833 tbl 04

Unit

o

C

o

C

48 33 tb l 06

Temperature and Supply Voltage

Ambient

Grade

Commercial 0OC to +7 0OC0V3.3V + 150mV Industrial -40OC to +8 5OC0V3.3V + 150mV

NOTES:

1. Industrial temperature: for specific speeds, packages and powers contact your sales office.

2. This is the parameter T

Absolute Maximum Ratings

Symbol Rat ing Commercial

(2)

TERM

V

BIAS

T

STG

T

OUT

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TERM must not exceed VDD + 150mV for more than 25% of the cycle time or

2. V 4ns maximum, and is limited to

Terminal Voltage with Res pe c t to GND

Tempe rature Under Bias

Storage Tempe rature

DC Output Curre nt 50 mA

Temperature GND V

A. This is the "instant on" case tempereature.

(1)

& Industrial

-0.5 to +4.6 V

-55 to +125

-65 to +150

< 20mA for the period of VTERM > VDD + 150mV.

Recommended DC Operating Conditions with V

Symbol Parameter Min. Typ. Max. Unit

DD

Core S upp ly Vo ltage 3.15 3.3 3.45 V

V

DDQ

I/O Supply Voltage

V

SS

V

Ground 0 0 0 V Input High Vo ltage

IH

V

(Ad d re ss & Contro l Inputs )

IH

V

Input High Vo ltage - I/O

IL

Input Lo w Vol tage -0. 3

V

NOTES:

IL > -1.5V for pulse width less than 10 ns.

1. V

TERM must not exceed VDDQ + 125mV.

2. V

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V supplied as indicated above.

(3)

DDQ at 2.5V

(3)

2.375 2.5 2.625 V

____

1.7

(3)

____

1.7

(1)

____

IL (0V), and VDDQX for that port must be

V

DDQ

+ 125m V

(2)

0.7 V

4833 tbl 05a

V

Recommended DC Operating Conditions with V

Symbol Parameter Min. Typ. Max. Unit

Core S upp l y Voltag e 3.15 3.3 3.45 V

V

DD

V

I/O Supply Voltage

DDQ

Ground 0 0 0 V

V

SS

Inp ut Hi g h Vo l tag e

V

IH

(Ad d re ss & Contro l Inputs )

V

Inp u t Hig h Vo l tag e - I/O

IH

Input Lo w Vo ltag e -0.3

V

IL

NOTES:

IL > -1.5V for pulse width less than 10 ns.

1. V

TERM must not exceed VDDQ + 150mV.

2. V

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V supplied as indicated above.

(3)

DDQ at 3.3V

3.15 3.3 3.45 V

____

2.0

(3)

2.0

(1)

IH (3.3V), and VDDQX for that port must be

V

+ 150mV

DDQ

____

V

+ 150mV

DDQ

____

0.8 V

(2)

4833 t b l 0 5 b

V

6.42

6

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Capacitance

(1)

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol Parameter Conditions

C

Input Ca pa ci tanc e VIN = 3dV 8 pF

IN

(3)

C

NOTES:

1. These parameters are determined by device characterization, but are not

2. 3dV references the interpolated capacitance when the input and output switch

3. C

Output Capac itance V

OUT

production tested. from 0V to 3V or from 3V to 0V.

OUT also references CI/O.

(2)

Max . Unit

= 3d V 10. 5 p F

OUT

4833 tbl 07

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

|ILI| Inpu t Leak ag e Curre nt

LO

|I

| O utpu t Leak ag e Curre nt VOL (3.3V ) O utpu t Low Vo ltag e VOH (3.3V) Output High Voltage VOL (2.5V ) O utpu t Low Vo ltag e

OH

(2.5V) Output High Voltage

V

(1)

(2)

NOTE:

DD < - 2.0V input leakages are undefined.

1. At V

DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.

2. V

DDQ

V

= Max., VIN = 0V to V

0

CE

= VIH or CE1 = VIL, V IOL = +4mA, V IOH = -4mA, V IOL = +2mA, V IOH = -2mA, V

DDQ

= Min.

= Mi n. 2.4

= Min.

= Mi n. 2.0

(VDD = 3.3V ± 150mV)

DDQ

OUT

= 0V to V

DDQ

70V3379S

___

10 µA 10 µA

0.4 V

___

0.4 V

___

4833 t bl 08

UnitMin. Max.

V

6.42

7

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(3)

Temperature and Supply Voltage Range

Sym bo l Param eter Test Co nditi on Versi on Typ .

DD

I

Dynamic Ope rating Curre nt (Bo th Ports Active)

SB1

I

Stand by Current (Bo th P orts - TTL Le ve l Inp uts )

SB2

I

Stand by Current (On e P o rt - TTL Le ve l Inp uts )

SB3

I

Full Standby Current (Both Ports - CMOS Le ve l Inp uts )

SB4

I

Full Standby Current (On e P o rt - CM OS Le ve l Inp uts )

NOTES:

1. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

4. V

X = VIL means CE0X = VIL and CE1X = VIH

5. CE

CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V

CE

"X" represents "L" for left port or "R" for right port.

L

R

and

+-

Outputs Disabled, f = f

L

+-

f = f

"A"

+-

Active Port Outputs Disab led,

MAX

f=f Both Ports

R

+-

or V

"A"

+-

VIN > VDD - 0. 2V o r VIN < 0.2V, Ac tive Port, Outputs Disabled , f = f

= VIL,

+-

(1)

MAX

R

+-

IH

= V

(1)

(5)

"B"

IH

= V

+-

L

and

+-

(2)

"B"

> VDD - 0.2V

+-

(1)

MAX

=

MAX

= VIL and

(1)

> VDD - 0.2V, VIN > VDD - 0.2V

IN

< 0.2V, f = 0

< 0.2V and

CO M 'L S 375 46 0 285 360 245 31 0 IND S CO M 'L S 145 190 105 145 95 12 5 IND S CO M 'L S 265 32 5 19 0 260 17 5 225 IND S COM'LS615615615 IND S

(5)

CO M 'L S 265 32 5 18 0 260 17 0 225 IND S

(VDD = 3.3V ± 150mV)

70V3 379 S4

Com'l Only

(4)

____ ____

Max. Typ.

285 415 245 360

105 175 95 150

190 30 0 175 26 0

180 30 0 170 26 0

70V3 379 S5

Com 'l

& Ind

(4)

Max. Typ.

70V3 379 S6

Com 'l

& Ind

(4)

Max. Unit

mA

630630

mA

4833 tbl 0 9

6.42

8

IDT70V3379S

,

High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Inp u t P ul s e L e v e l s (A d d r e s s & Co n tro l s ) Input Pulse Levels (I/Os) Inpu t Rise / Fal l Time s Inpu t Timing Re fe re nce Le v e ls Output Reference Leve ls Output Load

Ω

50

OUT

DATA

Figure 1. AC Output Test load.

.

GND to 3 GND to 3.0V /GND to 2. 35V

0V/GND to 2.35V

3ns

1.5V/1.25V

F ig ure s 1, 2, and 3

Ω

50

4833 tbl 10

10pF (Tester)

1.5V/1.25

4833 drw 03

DATA

OUT

770

435

2.5V

Ω

833

Ω

5pF*

,

3.3V

Ω

590

Ω

5pF*

4833 drw 04

,

Figure 2. Output Test Load

CKLZ, tCKHZ, tOLZ, and tOHZ).

(For t

*Including scope and jig.

10.5pF is the I/O capacitanceof this device, and 10pF is the AC Test Load Capacitance.

7 6

5

∆

tCD

(Typical, ns)

4 3

2

•

1

•

20.5

-1

·

Figure 3. Typical Output Derating (Lumped Capacitive Load).

50 80 100 200

30

Capacitance(pF)

4833 drw 05

6.42

9

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)

(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)

70V3379S4

Com'l Only

CYC2

t

CH2

t

CL2

t

R

t

F

t

SA

t

HA

t

SC

t

HC

t

SB

t

HB

t

SW

t

HW

t

SD

t

HD

t

SAD

t

HAD

t

SCN

t t

HCN

SRST

t

HRST

t

OE

t

OLZ

t

OHZ

t

CD2

t

DC

t

CKHZ

t

CKLZ

t

Cloc k Cy cle Time (Pip e line d) 7.5 Clock High Time (Pipelined) 3 Cloc k Lo w Time (Pip el ined ) 3 Clock Rise Time Clock Fall Time

____

Address Setup Time 1.8 Address Hold Time 0.7 Chip Enab le S e tup Time 1.8 Chip Enab le Ho ld Time 0.7 By te E nab le Se tup Time 1.8 By te E nab le Ho ld Time 0.7 R/W Setup Time 1.8 R/W Hold Time 0.7 Inpu t Data Se tup Tim e 1.8 Inpu t Data Ho ld Time 0.7

Setup Time

ADS

Hold Time

ADS

Setup Time

CNTEN

Hold Time

CNTEN

Setup Time

CNTRST

Hold Time

CNTRST

(1)

Outp ut En ab le to D ata Vali d

1.8

0.7

1.8

0.7

1.8

0.7

____

Outp ut En ab le to O utp ut Lo w-Z 0 Outp ut En ab le to O utp ut Hig h-Z 1 4 1 4. 5 1 5 ns Clock to Data Valid (Pipelined)

____

Da ta Output Ho l d A fte r Clo ck Hi gh 1 Cloc k Hi gh to Ou tput High-Z 1 3 1 4.5 1.5 6 ns Cloc k Hi gh to Ou tput Low-Z 1

____

3 3

____

4

____

4.2

____

Port-to-P ort Dela y

CO

t

Clock-to-Clock Offset 6

____

NOTES:

1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).

2. These values are valid for either level of V

DDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.

70V3379S5

Com'l

& Ind

10

4 4

____

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

____

0

____

1

8

(1,2)

____

70V3379S6

Com'l

& Ind

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

12

5

5 3 3

____

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

5

____

0

5

____

1

10

____

ns ns

ns 3ns 3ns

____

ns

ns 6ns

____

ns

6ns

____

ns

4833 tb l 11

6.42

10

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for Pipelined Operation

t

CYC2

t

CH2

t

CL2

(2)

CLK

CE

UB,LB

(0-3)

R/

ADDRESS

0

1

W

(4)

tSCt

HC

tSBt

t

SB

t

SW

tSAt

t

HB

t

HW

HA

HB

(5)

An An + 1 An + 2 An + 3

tSCt

(3)

HC

DATA

OUT

OE

(1 Latency)

(1)

t

CKLZ

(1)

t

CD2

t

DC

Qn Qn + 1 Qn + 2

NOTES:

1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

2. ADS = V

3. The output is disabled (High-Impedance state) by CE

IL, CNTEN and CNTRST = VIH.

0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = V

IL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If UB or LB was HIGH, then the appropriate Byte of DATA

OUT for Qn + 2 would be disabled (High-Impedance state).

Timing Waveform of a Multi-Device Pipelined Read

t

CYC2

ADDRESS

CE

DATA

OUT(B1)

ADDRESS

CLK

(B1)

0(B1)

(B2)

tSAt

A

tSCt

tSAt

A

t

HA

0

HC

HA

0

CH2

t

CL2

A

tSCt

Q

A

2

HC

t

CD2

0

t

DC

2

1

A

t

CD2

1

A

3

t

CKHZ

Q

1

DC

t

A

3

A

t

OHZ

(1,2)

4

CKLZ

t

4

t

CD2

(5)

t

OLZ

t

OE

4833drw 06

6

A

5

Q

3

t

CKHZ

A

5

A

6

A

tSCt

HC

CKLZ

t

CD2

t

CKHZ

Q

2

DATA

CE

0(B2)

OUT(B2)

tSCt

HC

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform, and are setup for depth expansion in this example. ADDRESS

2. UB, LB, OE, and ADS = V

IL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.

(B1) = ADDRESS(B2) in this situation.

6.42

11

CKLZ

t

CD2

Q

4833 drw 07

4

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Left Port Write to Pipelined Right Port Read

L

CLK

HW

tSWt

L

W

R/

HA

tSAt

ADDRESS

DATA

CLK

R/

ADDRESS

L

INL

R

W

R

MATCH

tSDt

VALID

tSWt

tSAt

MATCH

HD

(3)

CO

t

HW

HA

NO

MATCH

t

CD2

NO

MATCH

(1,2)

DATA

OUTR

VALID

DC

t

NOTES:

0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

1. CE

2. OE = V

3. If t

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)

IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

CO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will

CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite

be t port will be t

CO + tCYC + tCD2).

(2)

t

CYC2

t

CH2tCL2

CLK

CE

0

tSCt

HC

CE

1

tSBt

HB

UB,LB

tSWt

HW

R/W

ADDRESS

tSWt

HW

(3)

An An +1 An + 2 An + 2

tSAt

HA

t

SD

t

HD

An + 3 An + 4

4833 drw 08

DATA

OUT

IN

(1)

t

CD2

Qn

READ NOP READ

t

CKHZ

Dn + 2

t

CKLZ

(4)

WRITE

CD2

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

2. CE

3. Addresses do not have to be accessed sequentially since ADS = V

IL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

12

Qn + 3

4833drw 09

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)

t

CYC2

t

CH2tCL2

CLK

CE

0

tSCt

HC

CE

1

tSBt

HB

UB,LB

tSWt

HW

R/

W

tSWt

HW

(2)

ADDRESS

DATA

OUT

(3)

IN

An An +1 An + 2 An + 3

tSAt

HA

t

(1)

CD2

Qn

OHZ

t

tSDt

(4)

HD

Dn + 3Dn +2

An + 4

t

CKLZ

An + 5

t

CD2

Qn + 4

OE

READ WRITE READ

4833 drw 10

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

2. CE

3. Addresses do not have to be accessed sequentially since ADS = V

IL constantly loads the address on the rising edge of the CLK; numbers are for reference use

only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

Timing Waveform of Pipelined Read with Address Counter Advance

t

CYC2

t

CH2tCL2

CLK

tSAt

HA

ADDRESS

ADS

An

t

SADtHAD

t

SADtHAD

(1)

CNTEN

OUT

Qx - 1

READ

EXTERNAL

ADDRESS

DATA

(2)

NOTES:

0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.

1. CE

2. If there is no address change via ADS = V the data output remains constant for subsequent clocks.

t

SCNtHCN

t

CD2

(2)

Qn + 2

READ

WITH

COUNTER

13

Qn + 1

COUNTER

HOLD

Qx

Qn

t

DC

READ WITH COUNTER

IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

6.42

Qn + 3

4833 drw 11

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

t

CYC2

t

CH2tCL2

(1)

CLK

tSAt

HA

ADDRESS

An

INTERNAL ADDRESS

ADS

CNTEN

DATA

(3)

t

SADtHAD

tSDt

HD

IN

Dn

WRITE

EXTERNAL

ADDRESS

An

(7)

t

SCNtHCN

Dn + 1

Dn + 1 Dn+ 2

WRITE

WITHCOUNTER

An + 1

COUNTERHOLD

Timing Waveform of Counter Reset

t

CYC2

t

CH2tCL2

CLK

ADDRESS

INTERNAL ADDRESS

(3)

Ax

tSWt

R/

W

0

HW

WRITE

(2)

An + 2

An + 3

Dn + 3

An + 4

Dn + 4

WRITE WITH COUNTER

tSAt

HA

An

(4)

An + 1

1 An An + 1

4833 drw 12

An + 2

RESET

t

SADtHAD

t

SCNtHCN

t

SD

t

D

0

(6)

HD

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

Q

0

ADDRES Sn

READ

CNTEN

CNTRST

DATA

ADS

OUT

t

SRST

t

HRST

IN

(5)

COUNTER

NOTES:

1. CE

0,

, and R/W = VIL; CE1 and CNTRST = VIH.

UB, LB

CE

0,

2.

3. The "Internal Address" is equal to the "External Address" when ADS = V

4. Addresses do not have to be accessed sequentially since ADS = V

= VIL; CE1 = VIH.

UB, LB

IL and equals the counter output when ADS = VIH.

IL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: A

are shown here simply for clarification.

7. CNTEN = V

IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6.42

14

Q

1

READ

ADDRESSn+1

DDR 0 will be accessed. Extra cycles

Qn

4833 drw 13

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V3379 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal.

An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V3379s for depth expansion configurations. Two cycles are required with CE HIGH to re-activate the outputs.

A

15

IDT70V3379

Control Inputs

0 LOW and CE1

CE

0

CE

1

V

DD

Depth and Width Expansion

The IDT70V3379 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth.

The IDT70V3379 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider.

IDT70V3379

Control Inputs

CE

0 1

V

DD

IDT70V3379

Control Inputs

Figure 4. Depth and Width Expansion with IDT70V3379

CE

1 0

IDT70V3379

Control Inputs

CE

1 0

UB,LB

R/W,

,

OE

CLK,

4833 drw 14

ADS CNTRST

.

,

CNTEN

6.42

15

IDT70V3379S

s

High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

IDT

XXXXX

Device

Type

A

Power99SpeedAPackage

A

Process/

Temperature

Range

BlankICommercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

BF PRF BC

4 5 6

208-pin fpBGA (BF-208) 128-pin TQFP (PK-128) 256-pin BGA (BC-256)

CommercialOnly Commercial & Industrial Commercial & Industrial

Speed in nanosecond

S Standard Power

70V3379 576K (32K x 18-Bit) Synchrono usDual-Port RAM

4833 drw 15A

6.42

16

IDT70V3379S High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Datasheet Document History

1/18/98: Initial Public Release 3/15/99: Page 10 Additional Notes 4/28/99: Added fpBGA package 6/8/99: Page 2 Changed package body height from 1.5mm to 1.4mm 6/11/99: Page 5 Deleted note 6 for Table II 7/14/99: Page 2 Corrected pin to T3 to VDDQL 8/4/99: Page 6 Improved power numbers 10/4/99: Upgraded speed to 133MHz, added 2.5V I/O capability 11/12/99: Replaced IDT logo 2/28/00: Added new BGA package, added full 2.5V interface capability 5/1/00: Page 2 Added ball pitch

Page 3 Renamed pins Page 6 Made corrections to Truth Table Page 9 Changed Ω numbers in figure 2

6/7/00: Page 4 Added information to pin and pin notes

Page 6 Increated storage temperature parameter

Clarified TA Parameter

Page 8 DC Electrical parameters–changed wording from "open" to "disabled"

Removed note 7 on DC Electrical Characteristics table

1/10/01: Page 1 Changed 64K to 32K in block drawing

Removed Preliminary status

4/10/01: Added Industrial Temperature Ranges and removed related notes

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Datasheet IDT70V3379S Datasheet (IDT)

Specifications and Main Features

Frequently Asked Questions

User Manual