Datasheet IDT70V27S-L Datasheet (IDT)

查询DT70V27L供应商

HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM

Features:

◆

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

◆

High-speed access

– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)

◆

Low-power operation

– IDT70V27S

Active: 500mW (typ.)
Standby: 3.3mW (typ.)

– IDT70V27L

Active: 500mW (typ.)
Standby: 660µW (typ.)

◆

Separate upper-byte and lower-byte control for bus
matching capability

◆

Dual chip enables allow for depth expansion without
external logic

Functional Block Diagram

L

R/

W

L

UB

0L

CE

1L

CE

IDT70V27S/L

◆

IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device

◆

M/S = VIH for BUSY output flag on Master,

IL for BUSY input on Slave

M/S = V

◆

Busy and Interrupt Flags

◆

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling
between ports

◆

Fully asynchronous operation from either port

◆

LVTTL-compatible, single 3.3V (±0.3V) power supply

◆

Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)

◆

Industrial temperature range (-40°C to +85°C) is available
for selected speeds

R

W

R/

R

UB

0R

CE

1R

CE

L

OE

L

LB

8-15L

I/O

0-7L

I/O

(1,2)

BUSY

L

14L

A

SEM

INT

0L

A

L

(2)

L

Address
Decoder

14L

A

0L

A

0L

CE

1L

CE

OE

R/

W

L
L

NOTES:

1) BUSY is an input as a Slave (M/S=V

IL) and an output as a Master (M/S=VIH).

2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).

©2000 Integrated Device Technology, Inc.

I/O

Control

32Kx16

MEMORY

ARRAY

70V27

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/

6.01

1

R

OE

R

LB

8-15R

I/O

Control

Address
Decoder

14R

A

0R

A

0R

CE

1R

CE

R

OE

R

R/

W

(2)

S

I/O

I/O

BUSY

14R

A

0R

A

SEM
INT

3603 drw 01

0-7R

R

(2)

R

(1,2)

R

JANUARY 2001

DSC 3603/7

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Description:

The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32­bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for

Commercial and Industrial Temperature Range

reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (

CE0 and CE1) permits the on-chip

circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 500mW of power. The IDT70V27
is packaged in a 100-pin Thin Quad Flatpack (TQFP), a 108-pin ceramic
Pin Grid Array (PGA), and a 144-pin Fine Pitch BGA (fp BGA).

Pin Configurations

INDEX

A

9L

10L

A
A

11L
12L

A
A

13L

A

14L

NC
NC
NC

L

LB

L

UB

0L

CE

CE

1L

L

SEM

Vcc

R/

L

W

L

OE

GND
GND

15L

I/O
I/O

14L
13L

I/O
I/O

12L

I/O

11L
10L

I/O

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

(1,2,3)

L

L

L

L

7

5

6

8

A

A

A

A

1009998 979695 9493929190 8988 8786 8584 838281 8079 7877 76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

L

L

c

L

8

9

O

/

I

7

c
V

O

O

/

/

I

I

L

L

L

2

3

4

A

A

A

L

L

L

4

5

6

O

O

O

/

/

/

I

I

I

L

L

0

1

A

A

L

L

2

3

O

O

/

/

I

I

L

Y

L

D

S

T

C

N

I

N

IDT70V27PF

PN100-1

S

N

/

U

G

B

M

(4)

100-PIN TQFP

TOP VIEW

L

L

R

D
N
G

D

0

1
O

/

I

0

N

O

O

/

/

G

I

I

(5)

R

Y

R

S

R

R

R

T

U

0

2

1

N

I

B

A

A

A

R

R

1

2

O

O

/

/

I

I

R

R

R

5

4

3

O

O

O

/

/

/

I

I

I

R

R

R

5

4

3

A

A

A

c

R

R

c

6

7

V

O

O

/

/

I

I

R

R

R

7

8

6

A

A

A

9R

A

75

A

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

R

R

C

8

9

N

O

O

/

/

I

I

10R

A

11R

A

12R
13R

A
A

14R

NC
NC
NC

R

LB

R

UB

0R

CE

1R

CE

SEM

GND
R/

W

R

OE

GND
GND
I/O

15R
14R

I/O

13R

I/O
I/O

12R
11R

I/O
I/O

10R

3603 drw 02

R

R

2

IDT 70V27S/L

,

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Pin Configurations

A1

NCA2NCA3A

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

NC

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

10L

A

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13

14L

A

E1 E2 E3 E4 E10 E11 E12 E13

LB

F1 F2 F3 F4 F10 F11 F12 F13

SEM

G1 G2 G3 G4 G10 G11 G12 G13

V

CC

H1 H2 H3 H4 H10 H11 H12 H13

NC

J1 J2 J3 J4 J10 J11 J12 J13

GND

9L

13L

A

L

1L

CE

L

CC

V

R/

W

15L

I/O

(1,2,3)

(con't.)

A4

8L

5L

A

NCNC

A

6L

A

NCA

12L

A

7L

11L

A

NCNC

0L

CE

CC

V

OE

L

14L

I/O

L

UB

NC

L

NC

13L

I/0

A5

Commercial and Industrial Temperature Range

A6

A7

INT

1L

A

A

2L

3L

A

4L

A

L

GND

M/

NC

NC

BUSY

0L

A

IDT70V27BF

BF144-1

144-Pin fpBGA

Top View

S

L

(4)

(5)

A8

BUSY

INT

NCNC

A

0R

A9

R

1R

A

R

A

2RA6R

3R

A

A

4RA8RA12R

A10

5R

A

7RA9R

A

NC

UB

R

NC

NC

I/O

13R

A11

CE

NC

OE

I/O

NC

NC

0R

R

14R

A12NCA13

NCNC

A

10RA11R

13RA14R

A

LB

NCNC

SEM

CE

1R

GND

GND

GNDR/

W

R

5R

I/O1

GND

NC

NC

R

R

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13

NC NC

12L

I/O

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13

10L

11L

I/O

I/O

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13

9L

I/O

N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

NC NC

NC

I/O

NC

NC

NC

NC

V

CC

7L

I/O

8L

6L

I/O

5L

I/O

I/O

4L

NC I/O1LV

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. Package body is approximately 12mm x 12mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

I/O

I/O

GND

3L

2L

I/O

GND

I/O

CC

I/O

I/O

CC

V

I/O

I/O

I/O

2R

0L

NC V

1R

I/O

6R

5R

4R

I/O

I/O

11R

NC

NC

NC

I/O

7R

CC

NC NC NC

8R

NC

NC

NC

12R

I/O

10R

I/O

9R

I/O

3603 drw 02a

3R

0R

3

IDT 70V27S/L

3

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Pin Configurations

81 57 54

A

10R

12

A

11

A

10

A

09

INT

08

(1,2,3)

(con't.)

80 77 74 72 69 68 65 63 60

A

83 78 76 73 70 67 64 61 5984 56

7R

8687

4R

8890

1R

9192

R

A

11R

14R

A

A

A

A

A

13R

8R

82 79 75 71 66 62 58 50

A

9R

5R

85

6R

3R

89

A

2R

0R

A

NC

NC

12R

UB

LB

NC

Commercial and Industrial Temperature Range

SEM

CE

CE

R

1R

0R

R

R

GND

R/

W

OE

GND

GND

R

R

I/O

15R

I/O

I/O

NC

14R

11R

I/O

13R

I/O

12R

55 51

NC

52 49

I/O

I/O

I/O

NC

48 46

I/O

I/O4RI/O

6R

NC

10R

53

NC

9R

I/O

7R

8R

47

I/O

VccA

5R

45

3R

9495

93

07

06

05

04

03

02

01

GND

BUSY

A

A

A

107

A

108

A

M/

S

9796

L

L

INT

10099

0L

2L

5L

8L

9L

1L

A

103101

A

4L

105104

A

6L

2

11L

A

369111415182023

12L

BUSY

98

NC

102

3L

A

106

A

7L

1

A

10L

5

14L

A

NCA

R

4

A

13L

7

NC

L

LB

ABCDEFGHJK LM

NOTES:

INDEX

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.21in x 1.21in x .16in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

44 43

2R

IDT70V27G

(4)

G108-1

108-PIN PGA

TOP VIEW

(5)

I/O

39 40

1L

I/O

35 37

4L

I/O

31 34

Vcc

8

12

17

21

25

28

NC

10

13

L

UB

0L

CE

CE

SEM

Vcc

GND

1L

16

L

L

OE

R/

L

W

I/O

19

GND

14L

I/O

22

I/O

I/O

10L

13L

15L

24

I/O

I/O

NC

11L

12L

1R

I/O

I/O

0L

2L

I/O

5L

32

I/O

7L

29 30

NC

26 27

I/O

9L

42

I/O

41

GND

38

GNDI/O

36

I/O

33

I/O

I/O

NCNC

3603 drw 0

0R

3L

6L

8L

Pin Names

Left Port Right Port Names

CE

R/

0L

1L

, CE

L

W

CE

R/

0R

1R

, CE

R

W

Chip Enable
Re ad /Wri te E nab l e

4

L

OE

A0L - A

0L

I/O

- I/O

SEM

L

L

UB

LB

L

L

INT

BUSY

R

OE

14L

15L

L

M/
V

A0R - A
I/O0R - I/O

SEM

R

R

UB

LB

R

R

INT

BUSY

S

CC

14R

15R

R

Output Enabl e

Address
Data Inp ut/Ou tput
Semaphore Enable
Upper Byte Select
Lower Byte Select
Inte rru p t Fl ag
Busy Flag
Master or Slave Select
Power

GND Ground

3603 tbl 01

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Truth Table I  Chip Enable

Commercial and Industrial Temperature Range

(1,2,3)

NOTES:

CE CE

V

L

0.2V >VCC -0.2V Port Selected (CMOS Active)

<

V

H

VCC -0.2V X P o rt Des e le cte d (CMOS Inactiv e )

>

CE

0

IL

IH

XV

X<

1

V

IH

Po rt Se le cte d (TTL Activ e)

X Port Deselected (TTL Inactive)

IL

Port Deselected (TTL Inactive)

0.2V Port Deselected (CMOS Inactive)

Mode

1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.

2. Port "A" and "B" references are located where CE is used.

3. "H" = V

IH and "L" = VIL

Truth Table II  Non-Contention Read/Write Control

(1)

Inputs

CE

(2)

R/

W

OE UB LB SEM

HXXXXHHigh-ZHigh-ZDeselected: Power-Down
X X X H H H Hig h-Z Hig h-Z Bo th By tes De se le c ted
LLXLHHDATAINHigh-Z Write to Upper Byte Only

I/O

Outputs

8-15

I/O

0-7

Mode

3603 tbl 02

L L X H L H High-Z DATA

Write to Lo we r By te Onl y

IN

LLXLLHDATAINDATAINWri te to B o th B y te s
LHLLHHDATA

OUT

LHLHLHHigh-ZDATA
LHLLLHDATA

OUT

Hig h-Z Read Up p e r Byte Onl y

Read Lo we r By te Onl y

OUT

DATA

Read Both Bytes

OUT

X X H X X X High-Z High-Z Outputs Disabled

NOTES:

0L — A14L ≠ A0R — A14R.

1. A

2. Refer to Chip Enable Truth Table.

Truth Table III  Semaphore Read/Write Control

(1)

Inputs

CE

(2)

R/

W

OE UB LB SEM

HHLXXLDATA
XHLHHLDATA

H
X

↑
↑

XXXLDATAINDATAINWrite I/O0 into Semaphore Flag

XHHLDATAINDATAINWrite I/O0 into Semaphore Flag
LXXLXL
LXXXLL

NOTES:

1. There are eight semaphore flags written to I/O

2. Refer to Chip Enable Truth Table.

0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A0-A2.

Outputs

I/O

8-15

OUT

OUT

______ ______

______ ______

I/O

DATA
DATA

0-7

Read Data in S e map ho re F lag

OUT

Read Data in S e map ho re F lag

OUT

Not A llo we d
Not A llo we d

3603 tbl 03

Mode

3603 t bl 04

5

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Absolute Maximum Ratings

Symbol Rating

(2)

TERM

V

Terminal Voltage

Commercial

& Industri al

-0.5 to +4.6 V

(1)

Unit

with Respect
to GND

BIAS

T

Temperature

-55 to +125

o

C

Unde r B ia s

STG

T

Storage

-65 to +150

o

C

Temperature

OUT

I

DC Outp u t

50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

TERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

2. V
maximum, and is limited to

Capacitance

< 20mA for the period of VTERM > Vcc + 0.3V.

(1)

3603 tbl 05

(TA = +25°C, f = 1.0mhz)TQFP ONLY

Symbol Parameter Conditions

(2)

Max. Unit

Commercial and Industrial Temperature Range

Maximum Operating Temperature
and Supply Voltage

Grade

Commercial 0
Industrial -40

NOTES:

1. This is the parameter T

2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.

Ambient

Temperature GND Vcc

O

C to + 70OC0V3.3V + 0.3V

O

C to + 85OC0V 3.3V + 0.3V

A. This is the "instant on" case temperature.

(1,2)

3603 tbl 06

Recommended DC Operating
Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

V

Sup pl y Vo ltag e 3.0 3.3 3.6 V

GND Ground 0 0 0 V

IH

V

Inpu t Hig h Vo ltag e 2. 0

IL

Inp ut Lo w Vol tag e -0. 3

V

NOTES:

1. V

IL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.3V.

2. V

(1)

____

VCC+0.3V

(1)

____

(2)

0.8 V

3603 tbl 07

V

IN

C

Inp ut Ca p ac ita nc e VIN = 3dV 9 pF

C

OUT

Output

V

= 3dV 10 pF

OUT

Capacitance

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.

3603 tbl 08

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

|ILI| Input Le akag e Curre nt

LO

|

|I

Outp ut Lea kag e Curre nt

OL

V

Outp ut Low Vol tage IOL = 4mA

OH

V

Output High Voltag e IOH = -4mA 2.4

NOTE:

1. At Vcc

< 2.0V, input leakages are undefined.

(1)

VCC = 3.6V, VIN = 0V to V

IH

OUT

, V

CE

= V

= 0V to V

CC

CC

(VCC = 3.3V ± 0.3V)

70V27S 70V27L

___

___

___

10
10

0.4

___

___

___

___

2.4

UnitMin. Max. Min. Max.

5µA
5µA

0.4 V

___

V

3603 tbl 09

6

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

Symbol P arameter Test Condition Version

CC

I

Dynamic Op e rating
Current
(Bo th Po rts A ctiv e)

SB1

Standb y Current

I

(Bo th Po rts - TTL Lev el
Inputs)

SB2

Standb y Current

I

(On e Po rt - TTL Lev e l
Inputs)

SB3

Full S tandb y Curre nt

I

(Both Ports - All
CMOS Le v el Inp uts )

SB4

Full S tandb y Curre nt

I

(On e Po rt - A ll CM OS
Le v e l Inp u ts )

IL

, Outputs Disabled

= V

CE

IH

= V

SEM

(3)

MAX

f = f

L

R

CE

(3)

= V

SEM

L

= V

IH

IH

"B"

IH

= V

CE

CE
SEM

f = f

CE

"A"

=

R

=

MAX

= VIL and

Ac ti ve P o rt O utp uts Di sa b le d ,

(3)

MAX

f=f

R

L

SEM

SEM

SEM

= V

CE

L

L

IH

L

and

(4)

> VCC - 0.2V

(5)

> VCC - 0.2V

=

SEM

Both Ports

R

> VCC - 0.2V

CE

IN

> VCC - 0.2V o r

V

IN

< 0.2V, f = 0

V

=

R

SEM

"A"

< 0.2V and

CE

"B"

> VCC - 0.2V

CE

R

=

SEM

IN

> VCC - 0.2V or VIN < 0.2V

V
Active Port Outputs Disabled

(3)

MAX

f = f

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)

2. V

3. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

COM'L SL170

IND'L S

COM'L SL44

IND'L S

(5)

COM'L SL115

IND'L

COM'L SL1.0

IND'L

COM'L SL115

IND'L

(1,6,7)

(VCC = 3.3V ± 0.3V)

70V27X15

Com'l Only

(2)

Typ.

Max.

260

170

____
____

L

225

____
____

70

44

60

____
____

L

____
____

160

115

____

S

____

L

145

____
____

6

0.2

____

S

____

L

3

____
____

155

115

____

S

____

L

140

____
____

70V27X20

Com'l Only

(2)

Typ.

165
165

____
____

39
39

____
____

105
105

____
____

1.0

0.2

____
____

105
105

____
____

Max.

255
220

____
____

60
50

____
____

155
140

____
____

6
3

____
____

150
135

____
____

70V27X25

Com'l Only

(2)

Typ.

145
145

145
145

27
27

27
27

90
90

90
90

1.0

0.2

1.0

0.2
90

90
90

90

Max. Unit

245

mA

210
280

245

50

mA

40
60

50

mA

150
135

170
150

mA

6
3

10

6

mA

145
130

170
145

3603 tbl 10a

7

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

DC Electrical Characteristics Over the Operating

(1,6,7)

Temperature and Supply Voltage Range

Symbol Parameter Test Condition Version

CC

I

Dynamic Op e rating Curre nt
(Bo th Po rts A ctiv e)

SB1

Standb y Current

I

(Bo th Po rts - TTL Lev el
Inputs)

SB2

Standb y Current

I

(On e Po rt - TTL Lev e l
Inputs)

SB3

Full Stand b y Curre nt (B oth

I

Po rts - All CMO S Le ve l
Inputs)

SB4

Full S tandb y Curre nt

I

(On e Po rt - A ll CM OS
Le v e l Inp u ts )

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)

2. V

3. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

IL

, Outputs Disabled

= V

CE

IH

= V

SEM

(3)

MAX

f = f

L

R

=

CE

SEM

(3)

= V

L

IH

= V

CE

IH

"B"

IH

= V

CE
SEM

f = f

CE

"A"

=

R

MAX

= VIL and

Ac ti ve P o rt O utp uts Di sa b le d ,

(3)

MAX

f=f

R

L

=

SEM

SEM

Both Ports

R

> VCC - 0.2V

CE

IN

> VCC - 0.2V o r

V

IN

< 0.2V, f = 0

V

R

=

SEM

SEM

"A"

< 0.2V and

CE

"B"

> VCC - 0.2V

CE

R

=

SEM

SEM

IN

> VCC - 0.2V or VIN < 0.2V

V
Active Port Outputs Disabled

(3)

MAX

f = f

IH

= V

and

L

CE

(4)

L

> VCC - 0.2V

L

> VCC - 0.2V

(5)

(5)

(VCC = 3.3V ± 0.3V)

COM'L SL135

IND'L SL135

COM'L SL22

IND'L SL22

COM'L SL85

IND'L

COM'L SL1.0

IND'L

COM'L SL85

IND'L

Com 'l & I nd

Typ.

135

135

22

22

85

SL85

85

0.2

SL1.0

0.2

85

SL85

85

70V27X35

(2)

Max.

235
190

270
235

45
35

55
45

140
125

160
140

6
3

10

6

135
120

160
135

70V27X55

Com'l Only

(2)

Typ.

125
125

125
125

15
15

15
15

75
75

75
75

1.0

0.2

1.0

0.2
75

75
75

75

Max. Unit

225

mA

180
260

225

40

mA

30
50

40

mA

140
125

160
140

mA

6
3

10

6

mA

135
120

160
135

3603 tbl 10b

AC Test Conditions

Inp ut P ul s e Le v e ls
Inp ut Ri s e / Fal l Ti me s
Inp ut Ti mi ng Re fe re n c e Le v e ls
Outp ut Refe re nc e Le ve ls
Output Load

GND to 3.0V

5ns Max.

1.5V

1.5V

Fi gure s 1 and 2

3603 tbl 11

DATA

OUT

BUSY

INT

435

Ω

Figure 1. AC Output Test Load

8

3.3V

590

30pF

3.3V

Ω

DATA

OUT

435

Ω

590

Ω

5pF*

3603 drw 04

Figure 2. Output Test Load

LZ, tHZ, tWZ, tOW)

(for t

*Including scope and jig.

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

READ CYCLE

RC

t

AA

t

ACE

t
t

ABE

AOE

t

OH

t

LZ

t

HZ

t

PU

t
t

PD

SOP

t

SAA

t

READ CYCLE

RC

t

AA

t

ACE

t
t

ABE

AOE

t

OH

t

LZ

t

HZ

t

PU

t
t

PD

SOP

t

SAA

t

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. 'X' in part numbers indicates power rating (S or L).

5. Refer to Chip Enable Truth Table.

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

Read Cy cle Time 15
Address Access Time

Chip Enable Access Time
Byte Enable Access Time

(3)

(3)

Output Enab le A cc es s Time
Output Hold from Add re ss Change 3

Output Lo w-Z Tim e
Output High-Z Time
Chip Enable to Po wer Up Time
Ch ip Dis ab le to Po we r Do wn Tim e

Semaphore Flag Update Pulse (OE or

(1,2)

(1,2)

(2,5)

(2,5)

)10

SEM

Semaphore Address Access Time

Read Cy cl e Time 35
Address Access Time

Chip Enable Access Time
Byte Enable Access Time

(3)

(3)

Output Enab le A cc es s Time
Output Hold from Add re ss Change 3

Output Lo w-Z Tim e
Output High-Z Time
Chip Enable to Po wer Up Time
Ch ip Dis ab le to Po we r Do wn Tim e

Semaphore Flag Update Pulse (OE or

(1,2)

(1,2)

(2,5)

(2,5)

)15

SEM

Semaphore Address Access Time

IL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.

(4, 6)

70V27X15

Com'l Only

____

____

____

____

3

____

0

____

____

____

____

____

____

____

15
15
15
10

12

15

15

70V27X20

Com'l Only

____

20

____

____

____

____

____

____

____

20
20
20
12

____

3

____

3

12

____

0

20

____

10

20

70V27X35

Com'l & Ind

____

____

____

____

____

____

____

____

35
35
35
20

____

____

3

20

____

0

45

____

45

70V27X25

Com'l Only

25

____

____

____

____

3
3

____

0

____

15

____

70V27X55

Com'l Only

55

____

____

____

____

3
3

____

0

____

15

____

____

25 ns
25 ns
25 ns
15 ns

____

____

15 ns

____

25 ns

____

35 ns

3603 tbl 12a

____

55 ns
55 ns
55 ns
30 ns

____

____

25 ns

____

50 ns

____

65 ns

3603 tbl 12b

UnitSymbol Parameter Min. Max. Min. Max. Min. Max.

ns

ns
ns

ns

ns

UnitSymbol Parameter Min. Max. Min. Max.

ns

ns
ns

ns

ns

9

IDT 70V27S/L

,

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Waveform of Read Cycles

ADDR

(4)

t

AA

t

ACE

t

AOE

t

t

LZ

ABE

UB, LB

DATA

BUSY

CE

OE

R/W

OUT

OUT

(6)

Commercial and Industrial Temperature Range

(5)

t

RC

(4)

(4)

(4)

t

(1)

(4)

t

BDD

VALID DATA

(3,4)

OH

(2)

HZ

t

3603 drw 05

Timing of Power-Up Power-Down

(6)

CE

t

PU

I

CC

50% 50%

I

SB

NOTES:

1. Timing depends on which signal is asserted last: CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB.

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

3. t
BUSY has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t

5. SEM = V

6. Refer to Chip Enable Truth Table.

IH.

AOE, tACE, tAA or tBDD.

t

PD

3603 drw 06

10

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage

Symbol Parameter

WRI T E C YC L E

WC

t

EW

t

AW

t

AS

t

WP

t

WR

t

DW

t

HZ

t

DH

t

WZ

t

OW

t

SWRD

t

SPS

t

Symbol Parameter

WRI T E C YC L E

WC

t

EW

t

AW

t

AS

t

WP

t

WR

t

DW

t

HZ

t

DH

t

WZ

t

OW

t

SWRD

t

SPS

t

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM CE= V

4. The specification for t

5. 'X' in part numbers indicates power rating (S or L).

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

Write Cycle Time 15
Chip Enable to End-of-Write

(3)

Address Valid to End-of-Write 12
Address Set-up Time

(3)

Write Pulse Width 12
Write Re co v e ry Time 0
Data Val id to En d -o f-Wri te 10

Output High-Z Time
Data Hol d Tim e
Write Enable to Output in High-Z
Outp ut A cti v e fro m E nd -o f-Wr ite

SEM

Flag Write to Read Time

SEM

Flag Contention Window

(1,2)

(4)

(1,2)

(1, 2,4)

Write Cycle Time 35
Chip Enable to End-of-Write

(3)

Address Valid to End-of-Write 30
Address Set-up Time

(3)

Write Pulse Width 25
Write Re co v e ry Time 0
Data Val id to En d -o f-Wri te 20

Output High-Z Time
Data Hol d Tim e
Write Enable to Output in High-Z
Outp ut A cti v e fro m E nd -o f-Wr ite

SEM

Flag Write to Read Time

SEM

Flag Contention Window

(1,2)

(4)

(1,2)

(1, 2,4)

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable

Truth Table.

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t

DH will always be smaller than the actual tOW.

11

(5,6)

70V27X15

Com'l Only

12

0

____

0

____

0
5
5

70V27X20

Com'l Only

70V27X25

Com'l Only

UnitMin. Max. Min. Max. Min. Max.

____

____

____

____

____

____

____

10

____

10

____

____

____

20
15
15

0

15

0

15

____

0

____

0
5
5

70V27X35

Com'l & Ind

____

____

____

____

____

____

____

10

____

10

____

____

____

____

25
20
20

0

20

0

15

____

0

____

0
5
5

____

____

____

____

____

____

15 ns

____

15 ns

____

____

____

3603 tbl 13a

ns
ns
ns
ns
ns
ns
ns

ns

ns
ns
ns

70V27X55

Com'l Only

UnitMin. Max. Min. Max.

____

____

30

____

____

0

____

____

____

____

20

____

0

____

20

____

0

____

5

____

5

____

55
45
45

0

40

0

30

____

0

____

0
5
5

____

____

____

____

____

____

25 ns

____

25 ns

____

____

____

3603 tbl 13b

ns
ns
ns
ns
ns
ns
ns

ns

ns
ns
ns

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

t

WC

ADDRESS

(7)

t

HZ

OE

t

AW

CEorSEM

(9,10)

(1,5,8)

R/

DATA

OUT

W

(9)

(6)

t

AS

(7)

t

WZ

(4) (4)

IN

t

WP

(2)

t

DW

(3)

t

WR

t

OW

t

DH

UBorLB

DATA

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing

WC

t

ADDRESS

AW

t

CEorSEM

UBorLB

(9,10)

(9)

(6)

AS

t

t

EW

(2)

t

WR

(3)

3603 drw 07

(1,5)

W

R/

DATA

DW

t

IN

DH

t

3603 drw 08

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

3. t

EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t
on the bus for the required t
specified t

WP.

9. To access RAM, CE = V

DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

10 . Refer to Chip Enable Truth Table.

12

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

Timing Waveform of Semaphore Read after Write Timing, Either Side

SAA

t

2

A0-A

VALID ADDRESS

VALID ADDRESS

(1)

SEM

I/O

W

R/

AW

t

EW

t

DATA VALID

AS

t

t

WP

t

DW

IN

t

WR

t

DH

SWRD

t

SOP

t

ACE

t

DATA

AOE

t

t

OUT

VALID

OE

Write Cycle

NOTES:

1.

CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.

2. "DATA

OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention

0"A"-A2"A"

SIDE

A

(2)

“A”

R/

W

"A"

MATCH

Read Cycle

(1,3,4)

OH

(2)

3603 drw 09

"A"

SEM

SPS

t

0"B"-A2"B"

A

(2)

SIDE

NOTES:

OR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).

1. D

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W

SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

4. If t

“B”

"B"

W

R/

"B"

SEM

"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

MATCH

13

3603 drw 10

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

AC Electrical Characteristics Over the

70V27X15

5

0

(6,7)

15
15
15
15

____

17

____

____

____

30
25

70V27X20

Com'l Only

____

20

____

20

____

20

____

20

____

5

____

35

____

15

____

0

____

15

____

45

____

30

70V27X 35 Com 'l

& Ind

____

35

____

35

____

35

____

35

____

5

____

40

____

25

____

0

____

25

____

65

____

60

70V27X25

Com'l Only

____

____

____

____

5

____

20

0

20

____

____

70V27X55

Com'l Only

____

____

____

____

5

____

25

0

25

____

____

25 ns
25 ns
25 ns
25 ns

____

35 ns

____

____

____

55 ns
50 ns

45 ns
45 ns
45 ns
45 ns

____

50 ns

____

____

____

85 ns
80 ns

Operating Temperature and Supply Voltage Range

Com'l Only

BUSY TIM ING (M/S=V

BAA

t

BDA

t

BAC

t

BDC

t

APS

t

BDD

t

WH

t

BUSY

BUSY

BUSY

BUSY

Arb i tra tio n P rio r ity S e t- up Ti me

BUSY

Wri te Ho l d A fte r

BUSY TIM ING (M/S=V

WB

t

WH

t

BUSY

Wri te Ho l d A fte r

PORT-TO -PORT DELAY TI MI NG

WDD

t

DDD

t

Write Pulse to Data Delay
Write Data Valid to Rea d Da ta De lay

BUSY TIM ING (M/S=V

BAA

t

BDA

t

BAC

t

BDC

t

APS

t

BDD

t

WH

t

BUSY

BUSY

BUSY

BUSY

Arb i tra tio n P rio r ity S e t- up Ti me

BUSY

Wri te Ho l d A fte r

BUSY TIM ING (M/S=V

WB

t

WH

t

BUSY

Wri te Ho l d A fte r

PORT-TO -PORT DELAY TI MI NG

WDD

t

DDD

t

Write Pulse to Data Delay
Write Data Valid to Rea d Da ta De lay

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

IH

)

Access Time from Address Match
Disable Time from Address Not Matched
Acce ss Time from Chip Enable Low
Disable Time from Chip Enable High

(2)

Disable to Valid Data

BUSY

IL

)

Inp ut to W ri te

BUSY

IH

)

(3)

(5)

(4)

(5)

(1)

(1)

Access Time from Address Match
Disable Time from Address Not Matched
Acce ss Time from Chip Enable Low
Disable Time from Chip Enable High

(2)

Disable to Valid Data

BUSY

IL

)

Inp ut to W ri te

BUSY

(3)

(5)

(4)

(5)

(1)

(1)

____

____

____

____

____

12

12

____

____

14

UnitSymbol Parameter Min. Max. Min. Max. Min. Max.

ns

ns

ns
ns

3603 tb l 14a

UnitSymbol Parameter Min. Max. Min. Max.

ns

ns

ns
ns

3603 tbl 14b

IH)".

IDT 70V27S/L

,

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

Timing Waveform of Write with Port-to-Port Read and BUSY

WC

t

"A"

ADDR

W

"A"

R/

IN "A"

DATA

(1)

APS

t

"B"

ADDR

"B"

BUSY

OUT "B"

DATA

NOTES:

1. To ensure that the earlier of the two ports wins. t

L = CER = VIL (refer to Chip Enable Truth Table).

2. CE

3. OE = V

4. If M/S = V

IL for the reading port.

IL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= VIH and BUSY "B"= input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

APS is ignored for M/S = VIL (SLAVE).

BAA

t

MATCH

t

WP

DW

t

MATCH

WDD

t

VALID

DDD

t

(3)

(2,5)

(M/S = V IH)

DH

t

BDA

t

BDD

t

VALID

3603 drw 11

(4)

Timing Waveform Write with BUSY (M/S = VIL)

t

WP

R/W

"A"

(3)

t

WB

"B"

BUSY

R/

W

"B"

NOTES:

WH must be met for both BUSY input (SLAVE) and output (MASTER).

1. t

2. BUSY is asserted on port "B" blocking R/W

WB is only for the "Slave" version.

3. t

"B", until BUSY"B" goes HIGH.

(2)

t

WH

(1)

3603 drw 12

,

15

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Commercial and Industrial Temperature Range

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)

ADDR

and

CE

CE

BUSY

"A"
"B"

"A"

(2)

t

APS

"B"

"B"

ADDRESSES MATCH

t

BAC

t

BDC

3603 drw 13

(1,3)

Wavefor m of BUSY Arbitration Cycle Controlled by Address Match
Timing

ADDR

ADDR

BUSY

(M/S = VIH)

"A"

"B"

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2. If t

3. Refer to Chip Enable Truth Table.

(1)

t

APS

ADDRESS "N"

(2)

MATCHINGADDRESS "N"

t

BAA

t

BDA

3603 drw 14

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

70V27X15

Com'l Only

Symbol Parameter

IN TERR UP T TIM ING

AS

t

WR

t

INS

t

INR

t

Symbol Parameter

IN TERR UP T TIM ING

AS

t

WR

t

INS

t

INR

t

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. Industrial temperature: for other speeds, packages and powers contact your sales office.

Address Set-up Time 0
Write Recovery Time 0
In terr upt S et Time
Interr upt Re s et Time

____

____

Address Set-up Time 0
Write Recovery Time 0
In terr upt S et Time
Interr upt Re s et Time

(1,2)

____

____

15

25

70V27X20

Com'l Only

____

0

____

0

____

____

20
20

70V27X35

Com'l &Ind

____

____

____

____

30
35

70V27X25

Com'l Only

0
0

____

____

70V27X55

Com'l Only

0
0

____

____

UnitMin. Max. Min. Max. Min. Max.

____

____

25 ns
35 ns

3603 tbl 15a

UnitMin. Max. Min. Max.

____

____

40 ns
45 ns

3603 tbl 15b

ns
ns

ns
ns

16

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Waveform of Interrupt Timing

ADDR

CE

R/

INT

ADDR

CE

W

"B"

"B"

"A"

"A"

"A"

"B"

(3)

t

AS

(3)

AS

t

INTERRUPT SET ADDRESS

(3)

INS

t

INTERRUPT CLEAR ADDRESS

(1,5)

Commercial and Industrial Temperature Range

WC

t

(2)

(4)

t

WR

3603 drw 15

RC

t

(2)

OE

"B"

(3)

INR

t

"B"

INT

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE

or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

Truth Table IV  Interrupt Flag

(1,4)

Left Port Right Port

L

CE

L

OE

L

L L X 7FFF X X X X X
XXXXXXLL7FFF
XXX X
X L L 7FFE

14L-A0L

A

INT

L
H

L

(3)

(2)

L L X 7FFE X Set Left
X X X X X Reset Left

CE

R

OE

R

R

R/W

14R-A0R

A

INT

R

(2)

L

(3)

H

NOTES:

1. Assumes BUSY

2. If BUSY

3. If BUSY

L = BUSYR =VIH.
L = VIL, then no change.
R = VIL, then no change.

4. Refer to Chip Enable Truth Table.

Se t Ri g ht
Res e t Rig ht

INT

FunctionR/W

INT

INT

R

INT

L

Flag

Flag

R

L

Flag

3603 drw 16

Flag

36 03 tbl 16

17

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Truth Table V  Address BUSY Arbritration

Inputs Outputs

14L

A0L-A

14R

L

CE

CE

X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal

L L MATCH (2) (2) Wri te Inhib it

NOTES:

1. Pins BUSY
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t

3. Writes to the left port are internally ignored when BUSY
when BUSY

4. Refer to Chip Enable Truth Table.

A0R-A

R

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V27 are

R outputs are driving LOW regardless of actual logic level on the pin.

(1)

L

BUSY

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

BUSY

(1)

R

Function

(3)

3603 tbl 17

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

Commercial and Industrial Temperature Range

(4)

Truth Table VI  Example of Semaphore Procurement Sequence

(1,2)

Funct ion s D0 - D15 Left D0 - D15 Righ t Status

No Action 1 1 Semaphore free
Le ft Po rt Wri tes " 0" to Se m ap ho re 0 1 Le ft po r t has se m ap ho re to k e n
Rig ht Port Write s " 0" to Se map ho re 0 1 No ch ange . Rig ht si de has no write ac c es s to s e map hor e
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Le ft Po rt Wri tes " 0" to Se m ap ho re 1 0 No c hang e . Le ft p o rt has no write a cc e s s to s e ma p ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Le ft Po rt Wri tes " 0" to Se m ap ho re 0 1 Le ft po r t has se m ap ho re to k e n
Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27.

2. There are eight semaphore flags written to via I/O

0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

Functional Description

The IDT70V27 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70V27 has an automatic power down feature
controlled by CE0 and CE1. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.

7FFE when CE
port interrupt flag (INTR) is asserted when the left port writes to memory
location 7FFF (HEX) and to clear the interrupt flag (INTR), the
right port must read the memory location 7FFF. The message (16 bits) at
7FFE or 7FFF is user-defined since it is an addressable SRAM location.
If the interrupt func-tion is not used, address locations 7FFE and 7FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table IV for the interrupt operation.

L = OEL = VIL, R/W is a "don't care". Likewise, the right

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per the Truth Table
IV. The left port clears the interrupt through access of address location

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on

3603 tbl 18

18

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT 70V27 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.

Width Expansion with BUSY Lo gi c
Master/Slave Arrays

When expanding an IDT70V27 RAM array in width while using BUSY

A

15

CE

BUSY

BUSY

CE

0

R

1

R

SLAVE
Dual Port RAM

L

BUSY

SLAVE
Dual Port RAM

L

BUSY

MASTER
Dual Port RAM

L

BUSY

MASTER
Dual Port RAM

L

BUSY

L

BUSY

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70V27 RAMs.

CE

BUSY

CE

BUSY

0

R

1

R

BUSY

R

3603 drw 17

logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the busy signal as a write inhibit signal. Thus on the IDT70V27 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part is used as a slave (M/S pin = VIL) as
shown in Figure 3.

If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.

Semaphores

The IDT70V27 is a fast Dual-Port 32K x 16 CMOS Static RAM with

Commercial and Industrial Temperature Range

an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non­semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where CE

and SEM are both HIGH.

Systems which can best use the IDT70V27 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V27's hardware sema­phores, which provide a lockout mechanism without requiring complex
programming.

Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V27 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.

An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high­speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.

The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes

19

IDT 70V27S/L

8

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

a one to that latch.

The eight semaphore flags reside within the IDT70V27 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.

A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as a
one, a fact which the processor will verify by the subsequent read (see
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during the subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the

Commercial and Industrial Temperature Range

gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed

LPORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

D

WRITE

SEMAPHORE

READ

SEMAPHO RE

REQUEST FLIP FLOP

Q

Figure 4. IDT70V27 Semaphore Logic

Q

RPORT

0

D

D
WRITE

SEMAPHORE
READ

3603 drw 1

into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low and the other
side high. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta­neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.

20

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Ordering Information

Commercial and Industrial Temperature Range

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

NOTE:

1. Industrial temperature range is available on selected TQFP packages in low power.
For other speeds, packages and powers contact your sales office.

Blank

(1)

I

BF
PF
G

15
20
25
35
55

S
L

Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)

144-pin fpBGA(BF144-1)
100-pin TQFP(PN100-1)
108-pin PGA(G108-1)

Commercial
Commercial
Commercial
Commercial & Industrial
Commercial

Standard Power
Low Power

512K (32K x 16) 3.3V Dual-Port RAM70V27

Speed in nanoseconds

3603 drw 19

Preliminary Datasheet:

"PRELIMINARY' datasheets contain descriptions for products that are in early release.

21

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Datasheet Document History

12/3/98: Initiated Document History

Converted to new format
Typographical and cosmetic changes
Added fpBGA information
Added 15ns and 20ns speed grades
Updated DC Electrical Characteristics

Added additional notes to pin configurations
4/2/99: Page 5 Fixed typo in Table III
8/1/99: Page 3 Changed package body height from 1.1mm to 1.4mm
8/30/99: Page 1 Changed 660mW to 660µW
4/25/00: Replaced IDT logo

Page 2 Made pin correction

Changed ±200mV to 0mV in notes
1/12/01: Page 1 Fixed page numbering; copywright

Page 6 Increated storage temperature parameter

Clarified TA Parameter
Page 7 and8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed Preliminary status

Commercial and Industrial Temperature Range

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-5116 831-754-4613
Santa Clara, CA 95054 fax: [phone] [e-mail]

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

22