Datasheet IDT70V25L25J, IDT70V25L25PF, IDT70V25L35G, IDT70V25L35J, IDT70V25L35PF Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

HIGH-SPEED 3.3V
8K x 16 DUAL-PORT
STATIC RAM

IDT70V25S/L

FEATURES:

• True Dual-Ported memory cells which allow simulta­neous access of the same memory location

• High-speed access
— Commercial: 25/35/55ns (max.)

• Low-power operation
— IDT70V25S

Active: 230mW (typ.)
Standby: 3.3mW (typ.)

— IDT70V25L

Active: 230mW (typ.)
Standby: 0.66mW (typ.)

• Separate upper-byte and lower-byte control for
multiplexed bus compatibility

• IDT70V25 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device

FUNCTIONAL BLOCK DIAGRAM

R/

W

L

UB

L

•M/S = H for
M/S = L for

BUSY

output flag on Master

BUSY

input on Slave

• Busy and Interrupt Flags

• Devices are capable of withstanding greater than 2001V
electrostatic charge.

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling
between ports

• Fully asynchronous operation from either port

• LVTTL-compatible, single 3.3V (±0.3V) power supply

• Available in 84-pin PGA, 84-pin PLCC, and 100-pin
TQFP

DESCRIPTION:

The IDT70V25 is a high-speed 8K x 16 Dual-Port Static
RAM. The IDT70V25 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-

R/

W

R

UB

R

NOTES:

1. (MASTER):

BUSY

is output;
(SLAVE):
is input.

2.

BUSY

outputs

and

INT

outputs
are non-tri-stated
push-pull.

I/O8L-I/O

BUSY

LB
CE
OE

I/O0L-I/O

BUSY

L

A

A

SEM

INT

15L

(1,2)

12L

0L

(2)

L

L
L
L

I/O

13

Control

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/

S

7L

Address
Decoder

CE

L

OE

L

R/

W

L

L

I/O

Control

Address
Decoder

13

CE

R

OE

R

R/

W

R

LB

R

CE

OE

I/O8R-I/O

I/O0R-I/O

BUSY

A

12R

A

0R

SEM

INT

R

2944 drw 01

R
R

15R

7R

(1,2)

R

R

(2)

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2944/3

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.39

1

IDT70V25S/L

INDEX

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT70V25

PN100-1

100-PIN

TQFP

TOP VIEW

(3)

N/C
N/C
N/C
N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

I/O

3R

V

CC

I/O

4R

I/O

5R

I/O

6R

N/C
N/C
N/C
N/C

2944 drw 03

N/C
N/C
N/C
N/C
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

GND
M/

S

BUSY

R

INT

R

A

0R

N/C
N/C
N/C
N/C

BUSY

L

A

1R

A

2R

A

3R

A

4R

I/O

9L

I/O

8L

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

GND

I/O

1L

I/O

0L

OE

L

V

CC

R/

W

L

SEM

L

CE

L

UB

L

LB

L

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

I/O

7R

I/O

8R

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

OE

R

R/

W

R

SEM

R

CE

R

UB

R

LB

R

GND

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

12L

A

12R

HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

Port RAM for 32-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in

1L

GND

I/O

84-PIN PLCC
TOP VIEW

15R

GND

I/O

(1,2)

L

0L

OE

I/O

IDT70V25

J84-1

R

R

W

OE

GND

R/

L

L

L

L

W

CC

V

CE

UB

SEM

R/

82 81 80 79 78 77 76 75

(3)

46 47 48 49 50 51 52 53

R

R

R

R

12R

LB

CE

UB

SEM

A

L

LB

11R

A

12L

A

10R

A

11L

A

9L

8L

10L

A

A

A

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

8R

7R

A

A

2944 drw 02

9R

A

PIN CONFIGURATIONS

5L

4L

7L

6L

3L

12R

I/O

I/O

13R

I/O

I/O

2L

I/O

14R

I/O

INDEX

I/O

I/O
I/O
I/O
I/O
I/O

GND
I/O
I/O

V

GND
I/O
I/O
I/O

V
I/O
I/O
I/O
I/O
I/O
I/O

10L
11L
12L
13L

14L
15L
CC

CC

8L

12

9L

13
14
15
16
17
18
19
20
21
22

0R

23

1R

24

2R

25
26

3R

27

4R

28

5R

29

6R

30

7R

31

8R

32

I/O

I/O

I/O

11109876543218483

33 34 35 36 37 38 39 40 41 42 43 44 45

9R

10R

11R

I/O

I/O

I/O

memory. An automatic power down feature controlled by
permits the on-chip circuitry of each port to enter a very low
standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 350mW of power.

The IDT70V25 is packaged in a ceramic 84-pin PGA, an

84-Pin PLCC and a 100-pin Thin Quad Plastic Flatpack.

A

7L

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

BUSY

L

GND
M/

S

BUSY

R

INT

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

CE

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate the actual part marking.

6.39 2

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS (CONT'D)

63 61 60 58 55 54 51 48 46 45

11

I/O

7L

5L

I/O4LI/O2LI/O

I/O

66

64

10

I/O

10L

67

09

I/O

11L

69

08

I/O

13L

72

07

I/O

15L

75

06

I/O

0R

76

05

I/O

1R

79

04

I/O

3R

81

03

I/O

5R

82

02

I/O6RI/O

84346915131618

01

I/O8RI/O

62

I/O8LI/O6LI/O3LI/O

65

I/O

9L

68

I/O

12L

71

73

I/O

14L

V

CC

70

74

GND

GND

77

78

V

2R

4R

7R

9R

11R

I/O

I/O

CC

10R

12R

I/O

80

I/O

83

I/O

125

(1,2)

A

0L

OE

L

59 56 49 50 40

1L

UBLCE

57 53 52

GND

V

CC

IDT7V025

G84-3

84-PIN PGA

TOP VIEW

7

GNDGND

81110

I/O

13R

I/O

15R

R/

W

I/O

14R

OERLB

R

L

SEM

47 44

L

R/

W

L

(3)

12

SEM

R

14 17 20

R

UB

R

CE

R

LB

A

A

A

L

12L

11R

12R

11L

A

9L

33 35

BUSY

L

32 31

GND

28 29

A

0R

A

8R

A

10R

A

10L

43

A

41

A

6L

38

A

3L

A

0L

M/

INT

26

A

2R

23

A

5R

22 24

A

19 21

A

42

A

7L

8L

A

5L

39

A

4L

37

A

2L

34

INT

L

36

S

A

1L

30

R

BUSY

R

27

A

1R

25

A

3R

6R

A

4R

9R

A

7R

ABCDEFGHJKL

Index

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. This text does not indicate orientation of the actual part- marking.

PIN NAMES

Left Port Right Port Names

CE

L

R/

W

L R/WR Read/Write Enable

OE

L

A

0L – A12L A0R – A12R Address

I/O

0L – I/O15L I/O0R – I/O15R Data Input/Output

SEM

L

UB

L

LB

L

INT

L

BUSY

L

CE

R Chip Enable

OE

R Output Enable

SEM

R Semaphore Enable

UB

R Upper Byte Select

LB

R Lower Byte Select

INT

R Interrupt Flag

BUSY

R Busy Flag

M/

S

V

CC Power

Master or Slave Select

GND Ground

2944 drw 04

2944 tbl 01

6.39 3

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

(1)

CECE

CE

CECE

R/

Inputs

WW

W

OEOE

OE

WW

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

Outputs

8-15 I/O0-7 Mode

I/O

H X X X X H High-Z High-Z Deselected: Power Down
X X X H H H High-Z High-Z Both Bytes Deselected

L L X L H H DATA
L L X H L H High-Z DATA
L L X L L H DATA
L H L L H H DATA
L H L H L H High-Z DATA
L H L L L H DATA

IN High-Z Write to Upper Byte Only

IN Write to Lower Byte Only

IN DATAIN Write to Both Bytes

OUT High-Z Read Upper Byte Only

OUT Read Lower Byte Only

OUT DATAOUT Read Both Bytes

X X H X X X High-Z High-Z Outputs Disabled

NOTE:

1. A0L — A12L ≠ A0R — A12R.

2944 tbl 02

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

Inputs Outputs

CECE

CE

CECE

H H L X X L DATA
X H L H H L DATA
H
X X H H L DATA

L X X L X L — — Not Allowed
L X X X L L — — Not Allowed

NOTE:

1. There are eight semaphore flags written to via I/O

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

V

TERM

T

A Operating 0 to +70 °C

BIAS Temperature –55 to +125 °C

T

T

STG Storage –55 to +125 °C

I

OUT DC Output 50 mA

NOTES: 2944 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

2. V
or 10ns maximum, and is limited to

> Vcc + 0.5V.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Grade Temperature GND V

Commercial 0°C to +70°C 0V 3.3V ± 0.3

R/

WW

W

WW

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

X X X L DATAIN DATAIN Write DIN0 into Semaphore Flag

0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.

(1)

(2)

Terminal Voltage –0.5 to +4.6 V
with Respect
to GND

Temperature

Under Bias

Temperature

Current

< 20 mA for the period over VTERM

Ambient

8-15 I/O0-7 Mode

I/O

OUT DATAOUT Read Data in Semaphore Flag
OUT DATAOUT Read Data in Semaphore Flag

IN DATAIN Write DIN0 into Semaphore Flag

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 3.0 3.3 3.6 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — Vcc+0.3 V

V

IL Input Low Voltage –0.3

V

NOTES: 2944 tbl 06

1. VIL≥ -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

(1)

CC

2944 tbl 05

CAPACITANCE

(TA = +25°C, f = 1.0MHz)TQFP ONLY

Symbol Parameter Conditions

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output VOUT = 3dV 10 pF

C

Capacitance

NOTES: 2944 tbl 07

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

(1)

— 0.8 V

(2)

2944 tbl 03

Max. Unit

6.39 4

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V

V

NOTE:

1. At Vcc ≤ 2.0V input leakages are undefined.

(1)

VCC = 3.6V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

(VCC = 3.3V ± 0.3V)

IDT70V25S IDT70V25L

2944 tbl 08

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

70V25X25 70V25X35 70V25X55

Test

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

ISB1 Standby Current

(Both Ports — TTL
Level Inputs) f = f

ISB2 Standby Current

(One Port — TTL Active Port Outputs Open L 40 72 35 62 35 62
Level Inputs) f = f

ISB3 Full Standby Current Both Ports

(Both Ports — All

CMOS Level Inputs) V

I

SB4 Full Standby Current One Port CEL or COM’L. S 50 81 45 71 45 71 mA

(One Port — All
CMOS Level Inputs)

NOTES:

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. Icc dc = 70mA (typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

CE

= VIL, Outputs Open COM’L. S 80 170 70 115 70 115 mA

SEM

= V

IH L 80 120 70 100 70 100

(3)

MAX

CE

R = CEL = VIH COM’L. S 12 25 10 25 10 25 mA

SEM

R =

SEM

L = VIH L1020 8 20 8 20

(3)

MAX

CE

L or CER = VIH

(3)

MAX

SEM

R =

SEM

CE

R ≥ VCC - 0.2V L 0.2 2.5 0.2 2.5 0.2 2.5

IN ≥ VCC - 0.2V or

V

IN ≤ 0.2V, f = 0

SEM

R =

SEM

CE

R ≥ VCC - 0.2V

R =

SEM

V
V

SEM

IN ≥ VCC - 0.2V or
IN ≤ 0.2V

(5)

L = VIH

CE

L and COM’L. S 1.0 5 1.0 5 1.0 5 mA

(4)

L ≥ VCC - 0.2V

(5)

L ≥ VCC - 0.2V

COM’L. S 40 82 35 72 35 72 mA

L5071 45 61 4561

Active Port Outputs Open,

MAX

(3)

f = f

(1)

(2)

Max. Typ.

(VCC = 3.3V ± 0.3V)

(2)

Max. Typ.

(2)

Max. Unit

2683 tbl 09

6.39 5

IDT70V25S/L

2944 drw 05

590Ω

30pF435Ω

3.3V

DATA

OUT

BUSY

INT

590Ω

5pF435Ω

3.3V

DATA

OUT

HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2

2944 tbl 11

Figure 1. AC Output Load Figure 2. Output Test Load

(For t
Including scope and jig.

LZ, tHZ, tWZ, tOW)

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT70V25X25 IDT70V25X35 IDT70V25X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

RC Read Cycle Time 25 — 35 — 55 — ns

t

AA Address Access Time — 25 — 35 — 55 ns

t

(1, 2)

(1, 2)

(3)
(3)

—25—35 — 55ns
—25—35 — 55ns

3—3— 3 —ns

—15—20 — 25ns

(2)

(2)

OE

or

SEM

)15—15—15—ns

SEM

= VIH. To access semephore, CE = VIH or UB & LB = VIH, and

0—0— 0 —ns

—25—55 — 50ns

ACE Chip Enable Access Time

t

ABE Byte Enable Access Time

t

AOE Output Enable Access Time — 15 — 20 — 30 ns

t

OH Output Hold from Address Change 3 — 3 — 3 — ns

t

t

LZ Output Low-Z Time
HZ Output High-Z Time

t
t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

SOP Semaphore Flag Update Pulse (

t
t

SAA Semaphore Address Access Time — 35 — 45 — 65 ns

NOTES: 2944 tbl 12

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM,

4. "X" in part numbers indicates power rating (S or L).

CE

= V

IL,

UB

or LB = VIL, and

(4)

SEM

= VIL.

TIMING OF POWER-UP POWER-DOWN

CE

t

I

CC

I

SB

PU

t

PD

50% 50%

6.39 6

2944 drw 06

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

WAVEFORM OF READ CYCLES

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

CE

ACE

t

AOE

(4)

OE

(4)

t

ABE

UB, LB

R/

W

t

OH

(2)

t

HZ

2944 drw 07

NOTES:

DATA

BUSY

OUT

OUT

(1)

t

LZ

VALID DATA

(3, 4)

t

BDD

(4)

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. t

BDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations

BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last

5.

SEM

= V

IH.

tABE, tAOE, tACE, tAA or tBDD.

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 25 — 35 — 55 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 20 — 30 — 45 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 20 — 25 — 40 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

DW Data Valid to End-of-Write 15 — 20 — 30 — ns

t

HZ Output High-Z Time

t

DH Data Hold Time

t
t

WZ Write Enable to Output in High-Z

OW Output Active from End-of-Write

t

t

SWRD

t

SPS

SEM

Flag Write to Read Time 5 — 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — 5 — ns

(1, 2)

(4)

NOTES: 2944 tbl 13

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

IL,

UB

3. To access RAM, CE = V
valid for the entire t

EW time.

or LB = VIL,

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t
over voltage and temperature, the actual t

5. "X" in part numbers indicates power rating (S or L).

(3)

(3)

(1, 2)

(1, 2, 4)

SEM

= VIH. To access semaphore, CE = VIH or UB & LB = VIH, and

DH will always be smaller than the actual tOW.

(5)

IDT70V25X25 IDT70V25X35 IDT70V25X55

20 — 30 — 45 — ns

0— 0—0—ns

—15 — 20 — 25ns

0— 0—0—ns

—15 — 20 — 25ns

0— 0—0—ns

SEM

= VIL. Either condition must be

DH and tOW values will vary

6.39 7

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

tWC

ADDRESS

OE

tWZ

tAW

(2)

(7)

CE

or

SEM

CE

or

SEM

R/

DATAOUT

DATA

W

(9)

(9)

(6)

tAS tWP

(4) (4)

IN

WW

W

CONTROLLED TIMING

WW

(3)

tWR

tOW

tDW tDH

(1,5,8)

tHZ

(7)

2944 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

t

WC

CECE

CE

CECE

,

UBUB

UB

UBUB

LBLB

,

LB

CONTROLLED TIMING

LBLB

(1,5)

ADDRESS

t

AW

CE

or

UB

or

DATA

NOTES:

1. R/W or

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or

6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output

Test Load (Figure 2).

8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of t

to be placed on the bus for the required t
be as short as the specified t

9. To access RAM, CE = V

condition.

(9)

SEM

(6)

t

AS

(9)

LB

R/

W

IN

CE

or UB & LB must be High during all address transitions.

SEM

Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

IL,

EW or tWP) of a Low

CE

WP.

UB

or LB = VIL, and

or R/W (or

DW. If

OE

SEM

SEM

is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can

= VIH. To access Semaphore, CE = VIH or UB & LB = VIL, and

(2)

t

EW

t

DW

UB

or LB and a Low CE and a Low R/W for memory array writing cycle.

or R/W) going High to the end-of-write cycle.

(3)

t

WR

t

DH

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data

SEM

= VIL. tEW must be met for either

2944 drw 09

6.39 8

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

t

t

SAA

A0-A

SEM

I/O

R/

W

2

0

VALID ADDRESS

t

AW

t

EW

DATA

VALID

t

AS

t

WP

t

t

WR

DW

VALID ADDRESS

t

ACE

t

SOP

IN

t

DH

t

SWRD

OE

Read CycleWrite Cycle

NOTES:

1.CE = V

2. "DATA

IH or

UB

& LB = VIH for the duration of the above timing (both write and read cycle).

OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION

DATA

t

AOE

(1,3,4)

OUT

VALID

OH

(2)

2944 drw 10

(1)

A

0"A"-A2"A"

(2)

SIDE

SIDE

NOTES:

1. D

OR = DOL = VIL, CER = CEL = VIH, or both

2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/

SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

4. If t

(2)

“A”

“B”

R/

SEM

A

0"B"-A2"B"

R/

SEM

A" or

W"

W

"A"

"A"

W

"B"

"B"

UB

& LB = VIH.

SEM"

A" going High to R/W"B" or

MATCH

MATCH

t

SPS

SEM"

2944 drw 11

B" going High.

6.39 9

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT70V25X25 IDT70V25X35 IDT70V25X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

t

APS Arbitration Priority Set-up Time

t

BDD

WH Write Hold After

t

BUSY TIMING (M/

WB

t

WH Write Hold After

t

PORT-TO-PORT DELAY TIMING

WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND

(M/S = V

2. To ensure that the earlier of the two ports wins.

3. t

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. "X" is part numbers indicates power rating (S or L).

IH)".

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 25 — 35 — 45 ns

BUSY

Disable Time from Address Not Matched — 25 — 35 — 45 ns

BUSY

Access Time from Chip Low — 25 — 35 — 45 ns

BUSY

Disable Time from Chip High — 25 — 35 — 45 ns

BUSY

Disable to Valid Data

SS

S

= VIL)

SS

BUSY

Input to Write

BUSY

(4)

BUSY

(2)

(3)

(5)

(5)

(1)

(1)

5—5—5 —ns

—35—35— 45ns

20 — 25 — 25 — ns

0—0—0 —ns

20 — 25 — 25 — ns

—55—60— 80ns
—50—55— 75ns

(6)

2944 tbl 14

BUSY

DDD

(3)

(2,4,5)

t

BDA

t

DH

TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND

t

WC

t

BAA

MATCH

t

WP

ADDR

DATA

ADDR

DATA

R/

W

IN "A"

BUSY

OUT "B"

"A"

"A"

"B"

"B"

t

APS

(1)

BUSYBUSY

BUSY (M/

BUSYBUSY

t

DW

MATCH

t

WDD

VALID

SS

S

= VIH)

SS

t

NOTES:

1. To ensure that the earlier of the two ports wins. t

2.

CE

L = CER = VIL.

3.OE = V

4. If M/S = V

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

IL for the reading port.

IL (slave),

BUSY

is an input. Then for this example

APS is ignored for M/

BUSY

S

= VIL (slave).

"A" = VIH and

BUSY

"B" input is shown above.

t

BDD

VALID

2944 drw 12

6.39 10

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

BUSY

BUSYBUSY

BUSY

BUSYBUSY

(3)

t

WB

"B" goes High.

t

WP

(2)

TIMING WAVEFORM OF WRITE WITH

R/

W

"A"

BUSY

"B"

"B"

R/

W

NOTES:

WH must be met for both

1. t

2. Busy is asserted on port "B" Blocking R/

WB is only for the slave version.

3. t

BUSY

input (slave) output master.

W

"B", until

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

and

"A"
"B"

ADDRESSES MATCH

CECE

CE

TIMING

CECE

t

WH

(M/

(1)

2944 drw 13

SS

S

= VIH)

SS

(1)

CE

"A"

(2)

t

APS

CE

"B"

t

BUSY

BAC

"B"

t

BDC

2944 drw 14

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING

"A"

"B"

"B"

IH)

(1)

t

APS

ADDRESS "N"

(2)

MATCHING ADDRESS "N"

t

BAA

t

BDA

2944 drw 15

SS

(M/

S

= V

SS

ADDR

ADDR

BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2. If t

6.39 11

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE

t

WR

(1)

(4)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT70V25X25 IDT70V25X35 IDT70V25X55
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING

AS Address Set-up Time 0 — 0 — 0 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

INS Interrupt Set Time — 25 — 30 — 40 ns

t

INR Interrupt Reset Time — 30 — 35 — 45 ns

t

NOTE: 2944 tbl 15

1. "X" in part numbers indicates power rating (S or L).

WAVEFORM OF INTERRUPT TIMING

ADDR

"A"

(3)

t

AS

CE

"A"

R/

W

"A"

(3)

t

INS

(1)

t

WC

INTERRUPT SET ADDRESS

(2)

INT

"B"

2944 drw 16

t

RC

ADDR

"B"

t

AS

CE

"B"

OE

"B"

INT

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Flag truth table.

3. Timing depends on which enable signal ( CE or R/W ) is asserted last.

4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.

INTERRUPT CLEAR ADDRESS

(3)

(3)

t

INR

(2)

2944 drw 17

TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG

Left Port Right Port

CECE

WW

CE

L

R/

W

CECE

WW

L L X 1FFF XXXXXL
X X X X X X L L 1FFF H
XXXXL
X L L 1FFE H

NOTES: 2944 tbl 16

1. Assumes

2. If

3. If

BUSY

L = VIL, then no change.

BUSY

R = VIL, then no change.

BUSY

L

L =

OEOE

OE

OEOE

BUSY

L A12L-A0L

R = VIH.

INTINT

INT

INTINT

(3)

L R/

(2)

(1)

CECE

WW

CE

W

R

CECE

WW

L L X 1FFE X Set Left

OEOE

OE

R

R A12R-A0R

OEOE

INTINT

INT

R Function

INTINT

(2)

Set Right

(3)

Reset Right

INT

XXXXXReset Left

INT

INT

R Flag

INT

L Flag

L Flag

R Flag

6.39 12

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A12L

A

CECE

CECE

CE

CE

L

CECE

XX
HX
XH
LL

NOTES: 2944 tbl 17

1. Pins
IDT70V25 are push pull, not open drain outputs. On slaves the

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If t
simultaneously.

3. Writes to the left port are internally ignored when
internally ignored when

R A0R-A12R

CECE

BUSY

L and

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs when the part is configured as a master. Both are inputs when configured as a slave.

BUSY

(1)

BUSYBUSY

BUSY

L

BUSYBUSY

R outputs are driving low regardless of actual logic level on the pin.

(1)

BUSYBUSY

BUSY

R

BUSYBUSY

APS is not met, either

BUSY

Function

(3)

BUSY

input internally inhibits writes.

BUSY

L or

BUSY

R = Low will result.

L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are

BUSY

L and

BUSY

outputs on the

BUSY

R outputs cannot be low

TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE

(1,2)

Functions D0 - D15 Left D0 - D15 Right Status

No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Right port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES: 2944 tbl 18

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V25.

2. There are eight semaphore flags written to via I/O

0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

FUNCTIONAL DESCRIPTION

The IDT70V25 provides two ports with separate control,

address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V25 has an
automatic power down feature controlled by CE. The
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE High). When a port is enabled, access to the entire
memory array is permitted.

memory location 1FFF (HEX) and to clear the interrupt flag
(

INT

R), the right port must read the memory location 1FFF.

The message (16 bits) at 1FFE or 1FFF is user-defined, since

CE

it is an addressable SRAM location. If the interrupt function is
not used, address locations 1FFE and 1FFF are not used as
mail boxes, but as part of the random access memory. Refer
to Truth Table for the interrupt operation.

BUSY LOGIC

INTERRUPTS

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location 1FFE (HEX), where a write is
defined as the

CE

R = R/WR = VIL per the Truth Table. The left

port clears the interrupt by an address location 1FFE access
when

CE

L = OEL = VIL, R/WL is a "don't care". Likewise, the

right port interrupt flag (

INT

L) is asserted when the right port

INT

R) is set when the left port writes to

Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all

6.39 13

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

MASTER

CE

Dual Port
RAM

BUSY

L

BUSY

R

MASTER

CE

Dual Port
RAM

BUSY

L

BUSY

BUSY

L

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V25 RAMs.

applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
pin operates solely as a write inhibit input pin. Normal opera­tion can be programmed by tying the
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.

The busy outputs on the IDT 70V25 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.

BUSY

pins high. If

R

BUSY

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an IDT70V25 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V25 RAM the busy pin
is an output if the part is used as a master (M/S pin = H), and
the busy pin is an input if the part used as a slave (M/S pin =
L) as shown in Figure 3.

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write

SLAVE

CE

Dual Port
RAM

BUSY

SLAVE

L

BUSY

R

CE

DECODER

Dual Port
RAM

BUSY

BUSY

L

BUSY

R

inhibit signal and corrupted data in the slave.

R

2944 drw 18

SEMAPHORES

The IDT70V25 is an extremely fast Dual-Port 8K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the sema­phore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.

The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and

SEM

Systems which can best use the IDT70V25 contain mul­tiple processors or controllers and are typically very high­speed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V25's hardware semaphores,
which provide a lockout mechanism without requiring com­plex programming.

Software handshaking between processors offers the maxi­mum in system flexibility by permitting shared resources to be
allocated in varying configurations. The IDT70V25 does not
use its semaphore flags to control any resources through

SEM

, the semaphore enable. The CE and

are both high.

SEM

CE

6.39 14

IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

hardware, thus allowing the system designer total flexibility in
system architecture.

An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be a
major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be used
to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphores provide a
hardware assist for a use assignment method called “Token
Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in
use. If the left processor wants to use this resource, it requests
the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful,
it proceeds to assume control over the shared resource. If it
was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and
is using the shared resource. The left processor can then
either repeatedly request that semaphore’s status or remove
its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the
set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.

The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.

The eight semaphore flags reside within the IDT70V25 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica­tions. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read

SEM

value is latched into one side’s output register when that side's
semaphore select (

SEM

) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (

SEM

or OE)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the sema­phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.

It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema­phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.

One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.

Initialization of the semaphores is not automatic and must

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IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.

USING SEMAPHORES—SOME EXAMPLES

Perhaps the simplest application of semaphores is their
application as resource markers for the IDT70V25’s Dual-Port
RAM. Say the 8K x 16 RAM was to be divided into two 4K x 16
blocks which were to be dedicated at any one time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.

To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success­fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 4K. Mean­while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore

0. At this point, the software could choose to try and gain
control of the second 4K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.

Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of Dual-Port RAM with each

other.

The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.

Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces­sors can access their assigned RAM segments at full speed.

Another application is in the area of complex data struc­tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.

L PORT

SEMAPHORE

REQUEST FLIP FLOP

D

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT70V25 Semaphore Logic

6.39 16

Q

R PORT

D0

D

WRITE

SEMAPHORE
READ

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HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank

PF
G
J

25
35
55

S
L

Commercial (0°C to +70°C)

100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)

Speed in nanoseconds

Standard Power
Low Power

128K (8K x 16) 3.3V Dual-Port RAM70V25

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