Datasheet IDT70V07L25G, IDT70V07L25J, IDT70V07L25PF, IDT70V07L35J, IDT70V07L35PF Datasheet (Integrated Device Technology Inc)
...
Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
IDT70V07S/L
FEATURES:
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
— IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
•M/S = H for
M/S = L for
BUSY
output flag on Master
BUSY
input on Slave
• Busy and Interrupt Flags
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
OE
R
CE
R
R/
W
R
I/O0L- I/O
NOTES:
1. (MASTER):
2.
BUSY
and
7L
(1,2)
BUSY
L
A
14L
A
0L
SEM
L
(2)
INT
L
BUSY
is output; (SLAVE):
INT
outputs are non-tri-stated push-pull.
Address
Decoder
CE
OE
R/
W
BUSY
L
L
L
is input.
15
I/O
Control
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/
S
I/O
Control
I/O0R-I/O
BUSY
Address
Decoder
15
CE
R
OE
R
R/
W
R
A
A
SEM
INT
2943 drw 01
14R
0R
7R
(1,2)
R
R
(2)
R
COMMERCIAL TEMPERATURE RANGE OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2943/3
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.37
1
IDT70V07S/L
INDEX
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
GND
M/
S
OE
L
I/O
1L
R/
W
L
CE
L
SEM
L
V
CC
OE
R
CE
R
R/
W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2943 drw 03
A
13R
A
13L
70V07
PN80-1
TQFP
TOP
VIEW
(3)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
56
55
54
53
52
51
50
47
48
49
32
31
30
29
28
27
26
25
24
23
22
21
63
62
61
64
33
34
35
36
37
38
39
40
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
N/C
N/C
A
14L
N/C
N/C
N/C
N/C
A
14R
N/C
N/C
17
18
19
20
57
58
5960A
5L
N/C
INT
L
INT
R
N/C
N/C
N/C
I/O
6R
N/C
N/C
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
L
L
SEM
CE
IDT70V07
J68-1
PLCC
TOP
VIEW
R
CE
A14R
A13R
(1,2)
A14L
A13L
(3)
A12R
GND
VCC
A12L
A11R
A10L
A11L
40 41 42 43
A9R
A10R
A8L
A9L
A7L
64 63 62 61
A7R
A8R
A6R
A6L
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2943 drw 02
A5R
PIN CONFIGURATIONS
L
L
INDEX
I/O2L
I/O3L
I/O
4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
0R
I/O
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
0L
I/O
I/O1L
98765432168676665
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39
N/C
I/O7R
R
OE
N/C
R
W
R/
OE
W
R/
R
SEM
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 450mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68-
pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).
A5L
4L
A
A3L
A2L
A1L
A0L
INT
L
BUSY
L
GND
M/
S
R
BUSY
INT
R
A0R
A1R
A2R
A3R
A4R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.37 2
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D)
(1,2)
11
10
09
08
07
06
05
04
03
02
01
51 50 48 46 44 42 40 38 36
M/
L
BUSY
S
R
53
55
57
59
A
4L
A
2L
A
0L
INT
L
BUSY
GND
A
5L
52
A
7L
A
6L
47 45 43 41 34
49 39 37
A
3L
A
1L
54
A
9L
A
8L
56
A
11L
A
10L
58
V
CC
A
12L
IDT70V07
G68-1
60
61
A
14L
13L
62
L
CE
L
64
L
R/
W
L
A
63
SEM
65
OE
676866
I/O
0L
N/C
13579
I/O
1L
I/O
2L
I/O
GND GND
4L
2 4 6 8 10 12 14 16
I/O
5L
I/O
I/O
3L
6L
68-PIN PGA
TOP VIEW
I/O
7L
I/O
V
CC
0R
(3)
11 13 15
I/O
1R
I/O2RI/O3RI/O5RI/O
INT
A
V
0R
CC
1R
A
A
R
3R
35
A
2R
4R
32
A
7R
30
A
9R
28
A
11R
26
GND
24
A
14R
22
SEM
20
OE
A
5R
33
A
6R
31
A
8R
29
A
10R
27
A
12R
25
A
13R
23
R
CE
R
21
R
R/
W
R
A
18 19
I/O
7R
I/O
4R
N/C
17
6R
ABCDEFGHJ
INDEX
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port Right Port Names
CE
L
R/
W
L R/WR Read/Write Enable
OE
L
A
0L – A14L A0R – A14R Address
I/O
0L – I/O7L I/O0R – I/O7R Data Input/Output
SEM
L
INT
L
BUSY
L
CE
R Chip Enable
OE
R Output Enable
SEM
R Semaphore Enable
INT
R Interrupt Flag
BUSY
R Busy Flag
M/
S
V
CC Power
Master or Slave Select
GND Ground
2943 tbl 01
K
L
2943 drw 04
6.37 3
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
CECE
CE
CECE
R/
WW
W
WW
H X X H High-Z Deselected: Power-Down
L L X H DATA
L H L H DATA
X X H X High-Z Outputs Disabled
NOTE:
1. A0L — A14L ≠ A0R — A14R.
(1)
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
Outputs
0-7 Mode
I/O
IN Write to Memory
OUT Read Memory
2943 tbl 02
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs Outputs
CECE
CE
CECE
H H L L DATA
H X L DATA
R/
WW
W
WW
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
0-7 Mode
I/O
OUT Read Data in Semaphore Flag
IN Write I/O0 into Semaphore Flag
L X X L — Not Allowed
NOTE: 2943 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial Unit
(2)
V
TERM
T
A Operating 0 to +70 °C
BIAS Temperature –55 to +125 °C
T
T
STG Storage –55 to +125 °C
OUT DC Output 50 mA
I
NOTES: 2943 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TERM must not exceed Vcc + 0.3V for more than 25% of the cycle time
2. V
or 10ns maximum, and is limited to
+ 0.3V.
Terminal Voltage –0.5 to +4.6 V
with Respect
to GND
Temperature
Under Bias
Temperature
Current
< 20mA for the period of VTERM > Vcc
(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND V
CC
Commercial 0°C to +70°C 0V 3.3V ± 0.3V
2943 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CC Supply Voltage 3.0 3.3 3.6 V
V
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.0 — VCC+0.3 V
V
IL Input Low Voltage –0.3
V
NOTES: 2943 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.3V.
2. V
CAPACITANCE
(TA = +25°C, f = 1.0MHz)TQFP ONLY
Symbol Parameter Conditions
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Output VOUT = 3dV 10 pF
C
(2)
(1)
(1)
— 0.8 V
(2)
Max. Unit
Capacitance
NOTES: 2943 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.37 4
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
LI| Input Leakage Current
|I
LO| Output Leakage Current
|I
OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V
V
OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V
V
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
(1)
VCC = 3.6V, VIN = 0V to VCC —10—5µA
CE
= VIH, VOUT = 0V to VCC —10—5µA
(VCC = 3.3V ± 0.3V)
IDT70V07S IDT70V07L
2943 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
70V07X25 70V07X35 70V07X55
Test
Symbol Parameter Condition Version Typ.
CC Dynamic Operating
I
Current
(Both Ports Active) f = f
ISB1 Standby Current
(Both Ports — TTL
Level Inputs) f = f
ISB2 Standby Current
(One Port — TTL Active Port Outputs Open, L 50 85 45 75 45 75
Level Inputs) f = f
ISB3 Full Standby Current Both Ports
(Both Ports — All
CMOS Level Inputs) V
I
SB4 Full Standby Current
(One Port — All
CMOS Level Inputs)
CE
= VIL, Outputs Open COM’L. S 100 170 90 140 90 140 mA
SEM
= V
IH L 100 140 90 120 90 120
(3)
MAX
CE
R = CEL = VIH COM’L. S 14 30 12 30 12 30 mA
SEM
R =
SEM
L = VIH L12 24 10 24 10 24
(3)
MAX
CE
"A" = VIL and CE"B" = VIH
(3)
MAX
SEM
R =
SEM
L = VIH
CE
L and COM’L. S 1.0 6 1.0 6 1.0 6 mA
CE
R > VCC - 0.2V L 0.2 3 0.2 3 0.2 3
IN > VCC - 0.2V or
V
IN < 0.2V, f = 0
SEM
R =
SEM
CE
"A" < 0.2V and COM’L. S 60 90 55 85 55 85 mA
CE
"B" > VCC - 0.2V
R =
SEM
V
SEM
IN > VCC - 0.2V or VIN < 0.2V
(4)
L > VCC - 0.2V
(5)
L > VCC - 0.2V
(5)
COM’L. S 50 95 45 87 45 87 mA
L60 80 55 74 55 74
Active Port Outputs Open
MAX
(3)
f = f
(1)
(VCC = 3.3V ± 0.3V)
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
NOTES: 2943 tbl 09
1. "X" in part numbers indicates power rating (S or L).
CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
2. V
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
6.37 5
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns Max.
Input Timing Reference Levels 1.5V
DATA
OUT
BUSY
INT
3.3V
590Ω
30pF435Ω
DATA
OUT
3.3V
590Ω
5pF435Ω
Output Reference Levels 1.5V
Output Load Figures 1 and 2
2943 tbl 10
2943 drw 05
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for t
* Including scope and jig.
LZ, tHZ, tWZ, tOW)
2943 drw 06
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT70V07X25 IDT70V07X35 IDT70V07X55
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
RC Read Cycle Time 25 — 35 — 55 — ns
t
AA Address Access Time — 25 — 35 — 55 ns
t
ACE Chip Enable Access Time
t
t
AOE Output Enable Access Time — 15 — 20 — 30 ns
OH Output Hold from Address Change 3 — 3 — 3 — ns
t
t
LZ Output Low-Z Time
t
HZ Output High-Z Time
PU Chip Enable to Power Up Time
t
t
PD Chip Disable to Power Down Time
t
SOP Semaphore Flag Update Pulse (
SAA Semaphore Address Access Time — 35 — 45 — 65 ns
t
NOTES: 2943 tbl 11
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
4. "X" in part numbers indicates power rating (S or L).
IL and
SEM
(3)
(1, 2)
(1, 2)
(2)
(2)
OE
or
SEM
)15—15—15—ns
= VIH. To access semaphore, CE = VIH and
—25—35 —55ns
3—3— 3—ns
—15—20 —25ns
0—0— 0—ns
—25—35 —50ns
SEM
= VIL.
(4)
TIMING OF POWER-UP POWER-DOWN
CE
t
I
CC
I
SB
PU
t
PD
50% 50%
2943 drw 07
6.37 6
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES
(5)
t
RC
ADDR
(4)
t
AA
(4)
t
CE
ACE
t
AOE
(4)
OE
R/
W
t
(1)
t
LZ
DATA
OUT
BUSY
OUT
(3, 4)
t
BDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
4. Start of valid data depends on which timing becomes effective last t
5.
has no relation to valid output data.
= V
IH.
SEM
AOE, tACE, tAA or tBDD.
VALID DATA
(4)
OH
(2)
t
HZ
2943 drw 08
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
WC Write Cycle Time 25 — 35 — 55 — ns
t
EW Chip Enable to End-of-Write
t
AW Address Valid to End-of-Write 20 — 30 — 45 — ns
t
AS Address Set-up Time
t
WP Write Pulse Width 20 — 25 — 40 — ns
t
WR Write Recovery Time 0 — 0 — 0 — ns
t
t
DW Data Valid to End-of-Write 15 — 20 — 30 — ns
t
HZ Output High-Z Time
DH Data Hold Time
t
t
WZ Write Enable to Output in High-Z
t
OW Output Active from End-of-Write
SWRD
t
t
SPS
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
4. The specification for t
over voltage and temperature, the actual t
5. "X" in part numbers indicates power rating (S or L).
SEM
Flag Write to Read Time 5 — 5 — 5 — ns
SEM
Flag Contention Window 5 — 5 — 5 — ns
IL and
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
(1, 2)
(4)
SEM
(3)
(3)
(1, 2)
(1, 2, 4)
= VIH. To access semaphore, CE = VIH and
DH will always be smaller than the actual tOW.
(5)
IDT70V07X25 IDT70V07X35 IDT70V07X55
20 — 30 — 45 — ns
0—0—0—ns
—15 — 20— 25ns
0—0—0—ns
—15 — 20— 25ns
0—0—0—ns
2943 tbl 12
SEM
= VIL. Either condition must be valid for the entire tEW time.
6.37 7
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
t
WC
ADDRESS
OE
t
AW
R/
OUT
W
(9)
(6)
t
AS
(7)
t
WZ
(4) (4)
IN
t
WP
(2)
CECE
CE
CECE
CE or SEM
DATA
DATA
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
WW
W
CONTROLLED TIMING
WW
(3)
t
WR
t
OW
t
DW
t
DH
CONTROLLED TIMING
(1,5,8)
(1,5)
(7)
t
HZ
2943 drw 09
t
WC
ADDRESS
t
AW
R/
(9)
t
AS
t
EW
(2)(6)
t
WR
(3)
W
t
DW
IN
EW or tWP) of a LOW
CE
or R/W (or
SEM
LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
DW. If
OE
IL and
WP.
SEM
= VIH. To access semaphore, CE = VIH and
CE
SEM
is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
and a LOW R/W for memory array writing cycle.
or R/W) going HIGH to the end of write cycle.
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data
SEM
= VIL. tEW must be met for either condition.
t
DH
CE or SEM
DATA
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WR is measured from the earlier of
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the specified t
9. To access RAM, CE = V
2943 drw 10
+ 200mV from steady state with the Output
6.37 8
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
t
OH
(2)
2943 drw 11
NOTES:
1.CE = V
2. "DATA
A0-A
SEM
I/O
R/
W
2
0
VALID ADDRESS
t
AW
t
EW
t
DATA
VALID
t
AS
t
WP
t
WR
DW
IN
t
DH
t
SWRD
VALID ADDRESS
t
SOP
OE
Read CycleWrite Cycle
IH for the duration of the above timing (both write and read cycle).
OUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
t
SAA
t
ACE
t
AOE
DATA
VALID
OUT
(1)
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION
A
0"A"-A2"A"
(2)
SIDE
SIDE
NOTES:
OR = DOL = VIL, CER = CEL = VIH.
1. D
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/
SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
4. If t
(2)
“A”
“B”
R/
SEM
A
0"B"-A2"B"
R/
SEM
"A" or
W
W
"A"
"A"
W
"B"
"B"
SEM
"A" going HIGH to R/WB or
MATCH
MATCH
t
SPS
SEM
"B" going HIGH.
(1,3,4)
2943 drw 12
6.37 9
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT70V07X25 IDT70V07X35 IDT70V07X55
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/
BAA
t
BDA
t
BAC
t
BDC
t
APS Arbitration Priority Set-up Time
t
BDD
t
WH Write Hold After
t
BUSY TIMING (M/
WB
t
t
WH Write Hold After
PORT-TO-PORT DELAY TIMING
WDD Write Pulse to Data Delay
t
t
DDD Write Data Valid to Read Data Delay
NOTES: 2943 tbl 13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
SS
S
= V
IH)
SS
BUSY
Access Time from Address Match — 25 — 35 — 45 ns
BUSY
Disable Time from Address Not Matched — 25 — 35 — 45 ns
BUSY
Access Time from Chip Enable Low — 25 — 35 — 45 ns
BUSY
Disable Time from Chip Enable High — 25 — 35 — 45 ns
BUSY
Disable to Valid Data
SS
S
= V
IL)
SS
BUSY
Input to Write
BUSY
(4)
BUSY
(2)
(3)
(5)
(5)
(1)
(1)
5— 5— 5 —ns
—35 —40 — 50ns
20 — 25 — 25 — ns
0— 0— 0 —ns
20 — 25 — 25 — ns
—55 —65 — 85ns
—50 —60 — 80ns
(6)
BUSY
".
6.37 10
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
t
DDD
(2,4,5)
t
(3)
DH
t
BDA
t
DW
t
WDD
BUSYBUSY
BUSY
BUSYBUSY
VALID
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
t
WC
BUSY
MATCH
S
= VIL (slave).
"A" = VIH and
t
WP
MATCH
BUSY
"B" input is shown above.
ADDR
"A"
R/
W
"A"
DATA
IN "A"
(1)
t
APS
ADDR
"B"
"B"
BUSY
DATA
OUT "B"
NOTES:
1. To ensure that the earlier of the two ports wins. t
L = CER = VIL.
2.
CE
3.OE = VIL for the reading port.
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
IL (slave),
BUSY
is an input. Then for this example
APS is ignored for M/
t
BDD
VALID
2943 drw 13
TIMING WAVEFORM OF WRITE WITH BUSY
R/
W
"A"
(3)
t
WB
BUSY
"B"
"B"
R/
W
NOTES:
WH must be met for both
1. t
2.
BUSY
is asserted on port "B" blocking R/
BUSY
input (SLAVE) and output (MASTER).
"B", until
W
BUSY
"B" goes High.
t
WP
(2)
(1)
t
WH
2943 drw 14
6.37 11
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
ADDR
and
CE
CE
BUSY
"A"
"B"
"A"
"B"
"B"
t
APS
(2)
ADDRESSES MATCH
t
BAC
CECE
CE
TIMING
CECE
t
BDC
(1)
2943 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(1)
ADDR
"A"
t
APS
ADDR
"B"
BUSY
"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
APS is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
2. If t
ADDRESS "N"
(2)
MATCHING ADDRESS "N"
t
BAA
t
BDA
2943 drw 16
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT70V07X25 IDT70V07X35 IDT70V07X55
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
AS Address Set-up Time 0 — 0 — 0 — ns
t
WR Write Recovery Time 0 — 0 — 0 — ns
t
INS Interrupt Set Time — 25 — 30 — 40 ns
t
INR Interrupt Reset Time — 30 — 35 — 45 ns
t
NOTE:
1. "X" in part numbers indicates power rating (S or L).
(1)
2942 tbl 14
6.37 12
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF INTERRUPT TIMING
ADDR
CE
R/
INT
ADDR
CE
W
"A"
"A"
"A"
"B"
"B"
t
"B"
INTERRUPT SET ADDRESS
(3)
t
AS
(3)
t
INS
INTERRUPT CLEAR ADDRESS
(3)
AS
(1)
t
t
WC
RC
(2)
(2)
t
WR
(4)
2943 drw 17
OE
"B"
(3)
t
INR
INT
"B"
2943 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG
Left Port Right Port
CECE
WW
CE
L
R/
W
CECE
WW
L L X 7FFF XXXXXL
X X X X X X L L 7FFF H
XXXXL
X L L 7FFE H
NOTES: 2942 tbl 15
1. Assumes
2. If
3. If
BUSY
L = VIL, then no change.
BUSY
R = VIL, then no change.
BUSY
L
L =
OEOE
OE
OEOE
BUSY
L A14L-A0L
R =VIH.
INTINT
INT
INTINT
L R/
(3)
(2)
(1)
CECE
WW
CE
W
R
CECE
WW
L L X 7FFE X Set Left
OEOE
OE
R
R A14R-A 0R
OEOE
INTINT
INT
R Function
INTINT
(2)
Set Right
(3)
Reset Right
INT
XXXXXReset Left
INT
INT
R Flag
INT
L Flag
L Flag
R Flag
6.37 13
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE IV —
ADDRESS BUSYARBITRATION
Inputs Outputs
0L-A14L
A
CECE
CECE
CE
CE
L
CECE
XX
HX
XH
LL
NOTES: 2943 tbl 16
1. Pins
IDT7007 are push-pull, not open drain outputs. On slaves the
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If t
simultaneously.
3. Writes to the left port are internally ignored when
internally ignored when
R A0R-A14R
CECE
BUSY
L and
NO MATCH H H Normal
MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit
BUSY
R are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
Functions D0 - D7 Left D0 - D7 Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
(1)
BUSYBUSY
BUSY
L
BUSYBUSY
R outputs are driving LOW regardless of actual logic level on the pin.
(1)
BUSYBUSY
BUSY
R
BUSYBUSY
APS is not met, either
BUSY
Function
(3)
input internally inhibits writes.
BUSY
BUSY
L or
BUSY
R = LOW will result.
L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
BUSY
L and
BUSY
outputs on the
BUSY
R outputs can not be LOW
(1,2)
NOTES: 2943 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
2. There are eight semaphore flags written to via I/O
0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT70V07 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V07 has an
automatic power down feature controlled by CE. The
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
7FFF location 7FFF. The message (8 bits) at 7FFE or 7FFF
is user-defined since it is an addressable SRAM location. If
the interrupt function is not used, address locations 7FFE and
7FFF are not used as mail boxes, but as part of the random
CE
access memory. Refer to Truth Table for the interrupt
operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location 7FFE (HEX), where a write is
defined as CE = R/W = VIL per the Truth Table. The left port
clears the interrupt through access of address location 7FFE
when
CE
R = OER = VIL, R/
right port interrupt flag (
writes to memory location 7FFF (HEX) and to clear the
interrupt flag (
INT
R), the right port must read the memory
INT
L) is asserted when the right port
W
is a "don't care". Likewise, the
INT
R) is asserted when the left port
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
6.37 14
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the
BUSY
pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V07 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V07 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
MASTER
Dual Port
RAM
BUSY
L
MASTER
Dual Port
RAM
BUSY
BUSY
L
Figure 3. Busy and chip enable routing for both width and depth
L
expansion with IDT70V07 RAMs.
BUSY
BUSY
CE
CE
SLAVE
Dual Port
RAM
BUSY
R
R
L
SLAVE
Dual Port
RAM
BUSY
L
CE
BUSY
CE
BUSY
R
R
DECODER
BUSY
2943 drw 19
R
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V07 RAM the busy pin
is an output if the part is used as a master (M/S pin = H), and
the busy pin is an input if the part used as a slave (M/S pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
SEMAPHORES
The IDT70V07 is an extremely fast Dual-Port 32K x 8
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and
SEM
, the semaphore enable. The CE and
SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and
SEM
are both high.
CE
Systems which can best use the IDT70V07 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V07's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V07 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
6.37 15
IDT70V07S/L
D
2943 drw 20
0
D
Q
WRITE
D0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V07 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
SEM
Figure 4. IDT70V07 Semaphore Logic
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag
low and the other side high. This condition will continue until
a one is written to the same semaphore request latch. Should
the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
SEM
) and output enable (OE) signals go
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
SEM
or OE)
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT70V07’s Dual-Port
RAM. Say the 32K x 8 RAM was to be divided into two 16K
6.37 16
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
x 8 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 16K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower
16K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 16K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 16K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.37 17
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX
IDT
A
999
A
Device
Type
Power
SpeedAPackage
Process/
Temperature
Range
Blank
PF
G
J
25
35
55
S
L
Commercial (0°C to +70°C)
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
Speed in nanoseconds
Standard Power
Low Power
256K (32K x 8) 3.3V Dual-Port RAM70V07
2943 drw 21
6.37 18
Loading...