Datasheet IDT70T651-9S Datasheet (IDT)

查询IDT70T651供应商

HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE

Features

◆◆

◆

◆◆

True Dual-Port memory cells which allow simultaneous
access of the same memory location

◆◆

◆

◆◆

High-speed access

– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)

◆◆

◆

◆◆

RapidWrite Mode simplifies high-speed consecutive write
cycles

◆◆

◆

◆◆

Dual chip enables allow for depth expansion without
external logic

◆◆

◆

◆◆

IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device

◆◆

◆

◆◆

M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave

Functional Block Diagram

BE

3L

BE

2L

BE

1L

BE

0L

R/

W

L

CE

0L

CE

1L

PRELIMINARY

IDT70T651/9S

◆◆

◆

◆◆

Busy and Interrupt Flags

◆◆

◆

◆◆

On-chip port arbitration logic

◆◆

◆

◆◆

Full on-chip hardware support of semaphore signaling
between ports

◆◆

◆

◆◆

Fully asynchronous operation from either port

◆

Separate byte controls for multiplexed bus and bus
matching compatibility

◆◆

◆

◆◆

Sleep Mode Inputs on both ports

◆◆

◆

◆◆

Supports JTAG features compliant to IEEE 1149.1

◆◆

◆

◆◆

Single 2.5V (±100mV) power supply for core

◆◆

◆

◆◆

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port

◆◆

◆

◆◆

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.

◆◆

◆

◆◆

Industrial temperature range (–40°C to +85°C) is available
for selected speeds

BE

3R

BE

2R

BE

1R

BE

0R

R/

W

CE

CE

R

0R
1R

B

B

B

B

B

B

B

B

E

E

E

E

E

E

E

E

0

1

2

3

3

2

1

0

R

R

R

R

L

L

L

L

OE

L

I/O

BUSY

NOTES:

1. Address A

17x is a NC for IDT70T659.

2. BUSY is an input as a Slave (M/S=V

0L-

I/O

35L

(1)

A

17L

A

0L

(2,3)

L

SEM

L

(3)

INT

L

IL) and an output when it is a Master (M/S=VIH).

CE

CE

Address
Decoder

0L
1L

R/W

OE

ZZ

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L

Dout18-26_R

Dout27-35_L

Dout27-35_R

256/128K x 36

MEMORY

ARRAY

Di n_L

ADDR_L

L
L

(4)

L

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/S

ZZ

CONTROL

LOGIC

Di n_R

OE

R/W

ZZ

R

R

R

(4)

Address
Decoder

CE

0R

TDI

CE

1R

TD O

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

1

©2003 Integrated Device Technology, Inc.

JTAG

BUSY
SEM

R
(3)

INT

R

4869 drw 01

OE

R

I/O

0R -

I/O

35R

(1)

A

17R

A

0R

TC K
TMS

TRST

(2,3)

R

NOVEMBER 2003

DSC-5632/3

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous
Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS­TER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.

This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE
on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T651/9 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input
each cycle. This is especially significant at the 8 and 10ns cycle times of
the IDT70T651/9, easing design considerations at these high perfor­mance levels.

The 70T651/9 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) is at 2.5V.

0 or CE1) permit the

2

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

03/18/03

A2

A1

B1

I/O

C1

I/O

D1

I/O

E1

I/O

F1

I/O

G1

I/O

H1

I/O

J1

I/O

K1

I/O

L1

I/O

M1

I/O

N1

I/O

P1

I/O

R1

I/O

T1

NC

18L

18R

20R

21R

23L

24R

26L

27L

29R

30L

32R

33L

35R

35L

NC

A3

NC

TDI

B3

B2

TDO

NC

C3

C2

V

I/O

19L

D2

D3

I/O

19R

I/O

E2

E3

I/O

21L

I/O

F2

F3

I/O

22R

I/O

G2

G3

I/O

24L

I/O

H3

H2

I/O

I/O

25R

J2

J3

I/O

28R

I/O

K2

K3

I/O

29L

I/O

L3

L2

I/O

I/O

31R

M2

M3

I/O

32L

I/O

N2

N3

I/O

34R

I/O

P2

P3

I/O

34L

TMSP4A

R2

NCR3TRSTR4NC

T2

TCKT3NCT4A

(1,2,3)

SS

20L

22L

23R

25L

26R

27R

28L

30R

31L

33R

A4

A

B4

C4

D4

E4

V

F4

V

G4

V

H4

V

J4

V

K4

V

L4

V

M4

V

N4

17L

NC

A

16L

V

DD

DDQL

DDQL

DDQR

DDQR

DDQL

DDQL

DDQR

DDQR

V

DD

16R

17R

70T651/9BC

BC-256

(5,6)

256-Pin BGA

Top View

A6

A

B6

A

C6

A

D6

V

E6

F6

G6

H6

J6

K6

L6

M6

N6

V

P6

A

R6

A

T6

A

11L

12L

10L

DDQL

V

DD

NC

V

SS

V

SS

V

SS

V

SS

NC

V

DD

DDQR

10R

12R

11R

A7

B7

C7

D7

V

E7

F7

G7

H7

J7

K7

L7

M7

N7

V

P7

R7

T7

A

8L

A

9L

A

7L

DDQR

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQL

A

7R

A

9R

A

8R

A5

(4)

A

14L

B5

A

15L

C5

A

13L

D5

V

DDQL

E5

V

DD

F5

V

DD

G5

V

SS

H5

V

SS

J5

ZZ

R

K5

V

SS

L5

V

DD

M5

V

DD

N5

V

DDQR

P5

A

13R

R5

A

15R

T5

(4)

A

14R

A8

B8

BE

C8

D8

V

E8

F8

G8

H8

J8

K8

L8

M8

N8

V

P8

BE

R8

BE

T8

BE

BE

DDQR

V

V

SS

V

SS

V

SS

V

V

V

V

DDQL

BE

A9

A10

CE

1L

2L

3L

1L

SS

SS

SS

SS

SS

1R

3R

2R

B9

CE

C9

BE

D9

V

E9

F9

G9

H9

J9

K9

L9

M9

N9

V

P9

BE

R9

CE

T9

CE

0L

DDQL

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQR

0R

0R

OE

L

B10

0L

R/W

L

C10

SEM

L

D10

V

DDQL

E10

V

SS

F10

V

SS

G10

V

SS

H10

V

SS

J10

V

SS

K10

V

SS

L10

V

SS

M10

V

SS

N10

V

DDQR

P10

SEM

R

R10

R/W

R

T10

1R

OE

R

A11

INT

B11

NC

C11

BUSY

D11

V

DDQR

E11

V

DD

F11

V

SS

G11

V

SS

H11

V

SS

J11

V

SS

K11

V

SS

L11

V

SS

M11

V

DD

N11

V

DDQL

P11

BUSY

R11

M/S

T11

INT

A12

A13

A14

A

A

2L

A

1L

A

3L

V

DD

DDQR

DDQR

DDQL

DDQL

DDQR

DDQR

DDQL

DDQL

V

DD

A

3R

A

1R

A

2R

B14

NC

C14

OPT

D14

I/O

E14

I/O

F14

I/O

G14

I/O

H14

I/O

J14

I/O

K14

I/O

L14

I/O

M14

I/O

N14

I/O

P14

I/O

R14

OPT

T14

A

0L

L

15R

13L

12R

10L

9R

8R

6R

5L

3R

2L

0L

R

0R

A

5L

L

B12

B13

A

4L

C12

C13

A

6L

L

D12

D13

V

DDQR

E12

E13

V

DD

V

F13

F12

V

DD

V

G13

G12

V

SS

V

H13

H12

V

V

SS

J13

J12

V

ZZ

L

K12

K13

V

SS

V

L12

L13

V

DD

V

M12

M13

V

DD

V

N12

N13

V

DDQL

P12

P13

A

6R

R

R12

R13

A

4R

T12

R

T13

A

5R

A16

A15

NC

B16

B15

I/O

17L

C16

C15

I/O

I/O

17R

D16

D15

I/O

I/O

15L

E16

E15

I/O

I/O

14L

F15

F16

I/O

I/O

13R

G15

G16

I/O

I/O

11L

H16

H15

I/O

IO

9L

J15

J16

I/O

7R

K16

K15

I/O

I/O

6L

L16

L15

I/O

I/O

4R

M16

M15

I/O

3L

N16

N15

I/O

I/O

1R

P16

P15

I/O

0R

R16

R15

NC

T15NCT16

I/O

I/O

I/O

NC

NC

NC

NC

16L

16R

14R

12L

11R

10R

8L

7L

5R

4L

2R

1L

,

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground supply.

17X is a NC for IDT70T659.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

3

5632 drw 02f

,

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

I/O

I/O

I/O
I/O
V

I/O
I/O

I/O
I/O

V

I/O
I/O

I/O
I/O
V

I/O
I/O

I/O
I/O

V

V
I/O

I/O
I/O

I/O

V

I/O

I/O
I/O

I/O
V

I/O

I/O
I/O

I/O

V

I/O

I/O
I/O

I/O

03/18/03

19L

19R

20L

20R

DDQL

V

SS

21L

21R

22L

22R

DDQR

V

SS

23L

23R

24L

24R

DDQL

V

SS

25L

25R

26L

26R

DDQR

ZZ
V

DD

V

DD

V

SS

V

SS

DDQL

V

SS

27R

27L

28R

28L

DDQR

V

SS

29R

29L

30R

30L

DDQL

V

SS

31R

31L

32R

32L

DDQR

V

SS

33R

33L

34R

34L

R

L

R

Q

8

8
1

1

D

S
S

V

8
0
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

R

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

3
5

S
S

V

D

S

D

S

D

O

O

/

/

V

I

I

V

V

7

6

5

4

3

0

0

0

0

0

2

2

2

2

2

4

6

8

5

7

5

5

5

5

5

L

L

D

R

S

5

5

Q

D

3

3

M

D

V

O

T

D

O

/

/

I

I

V

)
4

(

L

L

L

L

L

L

L

I

O

7

6

5

C

C

1

1

D

D

T

T

2

1

0

0

2

2

1

A

A

N

A

N

0

9

8

7

6

0

9

9

9

9

2

1

1

1

1

L

4

3

2

1

0

L

L

1

1

1

A

A

A

5

4

3

9

9

9

1

1

1

L

1

1

9

8

7

A

A

A

A

A

2

1

0

9

8

9

9

9

8

8

1

1

1

1

1

L

L
3

E
B

7
8
1

L

L

L

L

1

0

2

1

0

D

D

S

E

E

E

E

E

D

D

B

B

B

6

5

4

8

8

8

1

1

1

S

C

C

V

V

V

3

2

1

0

9

8

8

8

8

7

1

1

1

1

1

70T651/9DR

DR-208

(5,6,7)

208-Pin

PQFP

Top View

9

1

3

0

2

4

6

8

5

7

9

1

3

5

6

6

6

6

6

6

)

R

T

K

S

C
T

R
T

R

4

C

C

(

6

5

1

1

N

N

R
7

A

A

1

A

0

6

6

6

6

7

R

R

R

R

R

4

3

2

1

0

1

1

1

1

1

A

A

A

A

A

5

2

4

6

7

7

R

R

9

8

A

A

7

7

7

7

7

7

R

R

R

R

R

7

3

2

1

0

E

E

E

E

A

B

B

B

B

(8)

8

0

9

2

1

7

8

7

8

8

S

D

D

R

R

1

0

S

D

D

E

E

V

V

V

C

C

L

L

Y

L

L

L

S

M

S

E

E

S

V

S

O

8

7

6

7

7

7

1

1

1

4

3

5

8

8

8

S

R

R

S

E

M

V

O

E
S

L

L

W

/

U

R

B

5

4

7

7

1

1

7

6

8

8

R

R

Y

W

/

S

R

U
B

L

T

C

6

5

4

N

A

I

N

A

A

3

2

1

0

9

7

7

7

7

6

1

1

1

1

1

9

8

0

2

1

8

8

9

9

9

R

R

R

R

S

/

6

5

4

T

A

A

A

M

N

I

D

L
3

A

8
6
1

3
9

R
3

A

D

L

L

L

2

1

0

D

D

A

A

A

V

V

7

6

5

4

3

6

6

6

6

6

1

1

1

1

1

4

5

7

6

8

9

9

9

9

9

S

D

R

R

R

2

1

0

S

D

A

A

A

V

V

R

R

L

L

Q

7

7

T

1

1

D

S
S

V

2
6
1

9
9

S
S

V

S

P

D

S

O

O

/

/

O

I

I

V

V

1

0

9

8

7

6

6

5

5

5

1

1

1

1

1

I/O

4
0
1

5632 drw 02d

S
S

V

I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
V
V
V
V
ZZ
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O

16L
16R
15L

15R
SS
DDQL

14L

14R

13L

13R
SS
DDQR

12L

12R

11L

11R
SS
DDQL

10L

10R

9L

9R
SS
DDQR
DD
DD
SS
SS

L
DDQL

8R

8L

7R

7L
SS
DDQR

6R

6L

5R

5L
SS
DDQL

4R

4L

3R

3L
SS
DDQR

2R

2L

1R

1L

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

1

0

2

3

0

0

0

0

1

1

1

1

L

L

R

R

0

0

Q

T

D

O

O

P

/

/

D

I

I

O

V

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground.

17X is a NC for IDT70T659.

5. Package body is approximately 28mm x 28mm x 3.5mm.

6. This package code is used to reference the package diagram.

7. 8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.

8. This text does not indicate orientation of the actual part-marking.

4

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

21

I/O

(1,2,3)

18LVSS

(con't.)

TDO

NC

9876543

A

12L

A

A

16L

8L

BE

1L

10

V

11

DD

SEM

INT

L

L

1412 13

15

A

0L

A4

L

OPT

1716

A

V

SS

I/O

17L

L

Pin Configurations

03/18/03

I/O

19L

A

I/O

20RVSS

B

V

DDQL

C

I/O

22LVSS

D

I/O

23L

E

V

DDQL

F

I/O

26LVSS

G

V

DD

H

V

DDQ L

J

I/O

28RVSS

K

I/O

29R

L

V

DDQL

M

I/O

31LVSS

N

I/O

32R

P

VSSI/O

R

I/O

33R

T

V

SS

U

I/O

19R

I/O

22RVDDQR

I/O

23R

I/O

26R

V

DD

I/O

28LVDDQR

I/O

29L

I/O

32LVDDQR

33L

I/O

34LVDDQL

I/O

35L

I/O

18R

V

DDQ R

I/O

21L

I/O

24LVSS

I/O

25L

V

DDQ R

VSSZZ

I/O

27R

I/O

30RVSS

I/O

31R

I/O

34R

V

DD

I/O

(4)

TDI

A

17L

V

DD

NC I/O

A

15LA11LA7L

I/O

20L

I/O

21R

I/O

24R

I/O

25R

R

V

SS

I/O

27L

I/O

30L

TRST

35R

(4)

A

17R

TCK

NC

TMS

NC

A

15R

A

9L

A

13L

A

10L

A

14L

A

16RA12RA8R

A

13RA9R

A

14RA10R

A

11RA7R

CE

0L

BE

2L

CE

1L

BE

3L

V

DD

BE

0L

70T651/9BF

BF-208

(5,6)

208-Ball

fpBGA

Top View

BE

1R

BE

2R

CE

0

R

CE

1R

BE

3R

V

DD

BE

0R

A5

V

SS

BUSY

V

SS

OE

L

L

1L

L

R/

W

L

NC

A

A

2L

A6

L

V

DD

A

3

L

(7)

A

V

DD

SEM

R

V

SS

BUS Y

R

V

SS

R/

W

R

M/

S

OE

R

INT

A

A

A

4R

R

A

1R

5R

A

2R

6R

A

0R

3R

V

V

SS

V

DD

I/O

17R

V

I/O

I/O

12L

V

SS

I/O

I/O9LV

VDDI/O

ZZ

L

V

I/O

7R

I/O

6R

V

SS

I/O

3R

V

I/O2LI/O

V

SS

V

SS

V

DD

OPTRI/O0LI/O

I/O

I/O

I/O

V

I/O

DDQR

DDQL

DDQL

V

DDQL

DDQL

DDQL

13R

12R

DD

16R

9R

7L

6L

3L

0R

I/O16L

15L

I/O

14L

V

SS

I/O

11L

I/O

10L

VSSI/O

V

SS

I/O8R

V

SS

I/O

5R

I/O

4R

V

SS

I/O1RV

V

SS

I/O

15R

B

V

SS

C

I/O

14R

D

I/O

13L

E

V

DDQR

F

I/O

11R

G
H

10R

V

DDQR

J

V

SS

K

I/O

8L

L

V

DDQR

M
N

I/O

5L

I/O

4L

P

DDQ R

R

I/O

2R

T

1L

U

5632 drw 02e

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground.

17X is a NC for IDT70T659.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

5

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

0L

CE

R/W

L

OE

0L

A

0L

I/O

SEM

INT

BUSY

0L

BE

,

L

- A

- I/O

L

L

- BE

CE

L

V

17L

DDQL

OPT

ZZ

1L

(1)

35L

3L

L

CE

0R

,

CE

1R

R/W

R

OE

R

(1)

A0R - A

17R

I/O0R - I/O

35R

SEM

R

INT

R

BUSY

R

BE0R - BE

3R

V

DDQR

L

OPT

ZZ

R

M/S Master or Slav e Select (Input)

V

DD

SS

V

TDI Test Data Inp ut

TDO Tes t Data Outp ut

TCK Test Lo gic Cloc k (10MHz) (Input)

TMS Test Mode Select (Input)

TRST

Chip Enables (Input)

Read /Write Enable (Input)

Output Enable (Input)

Address (Input)

Data Inp ut/Outp ut

Semapho re Enable (Inp ut)

Interrup t Fl ag (Output)

Busy Flag (Output)

Byte Enab le s (9-bit bytes) (Input)

Power (I/O Bus) (3.3V or 2.5V)

R

Optio n fo r sele c ting V

Sleep Mode Pin

Power (2.5V)

(2)

(Input)

Ground (0V) (Input)

Reset (Initialize TAP Controller) (Input)

(4)

(Input)

DDQX

(2,3 )

(2)

(Input)

(Input)

(5)

5632 tbl 01

NOTES:

1. Address A

2. V
applying inputs on I/O

3. OPT
If OPT
levels and V
port's I/Os and controls will operate at 2.5V levels and V

17x is a NC for IDT70T659.

DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

X.

X selects the operating voltage levels for the I/Os and controls on that port.

X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

DDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.

5. BUSY is an input as a Slave (M/S=V

IH).

(M/S=V

IL) and an output when it is a Master

6

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

18-26

(1,2)

Byte 1
I/O

9-1 7

Byte 0

I/O

0-8

MODE

Truth Table I—Read/Write and Enable Control

OE SEM CE

1

0

BE3BE2BE1BE

0

R/W ZZ

I/O

CE

Byte 3

27-35

Byte 2

I/O

X H H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X H X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X H L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected

X H L H H H H L L L High-Z Hig h-Z High-Z D

X H L H H H L H L L Hi gh- Z Hig h-Z D

XHL HHL HHL LHigh-Z D

XHLHLHHHLL D

IN

IN

High-Z High-Z High-Z Write to Byte 3 Only

X H L H H H L L L L Hig h-Z Hig h-Z D

XHLHLLHHLL D

XHLHLLLLLL D

IN

IN

D

IN

D

IN

IN

High-Z High-Z Write to Byte 2 Only

IN

High-Z High-Z Write to Upper 2 bytes Only

D

IN

L H L H H H H L H L Hig h-Z High-Z High-Z D

LHLHHHLHHLHigh-ZHigh-Z D

LHLHHLHHHLHigh-Z D

LHLHLHHHHL D

OUT

OUT

High-Z High-Z High-Z Re ad Byte 3 Only

LHLHHHLLHLHigh-ZHigh-ZD

LHLHLLHHHL D

LHLHLLLLHL D

OUT

OUT

D

OUT

D

OUT

OUT

High-Z High-Z Read Byte 2 Only

OUT

High-Z High-Z Read Upper 2 Bytes Only

D

OUT

IN

Write to Byte 0 Only

High-Z Write to Byte 1 Only

D

IN

Write to Lower 2 Bytes Only

D

IN

Write to All Bytes

OUT

Read Byte 0 Only

High-Z Read Byte 1 Only

D

OUT

Read Lower 2 Bytes Only

D

OUT

Read All Bytes

H H L H L L L L X L High-Z High-Z High-Z High-Z Outputs Disabled

X X X X X X X X X H High-Z High-Z High-Z High-Z High-Z Sleep Mode

NOTES:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

5632 tb l 02

2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II – Semaphore Read/Write Control

(1)

Inputs

(2)

CE

R/W

OE BE

3

BE

2

BE

1

BE

0

SEM

HHLLLLLLDATA

H

↑

XXXXL L X DATAINWrite I/O0 into Semaphore Flag

LXXXXXX L

NOTES:

1. There are eight semaphore flags written to I/O

2. CE = L occurs when CE

0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

3. Each byte is controlled by the respective BEn. To read data BEn = V

0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.

IL.

7

Outputs

I/O

1-3 5

OUT

______ ______

(1)

I/O

DATA

0

OUT

Read Data in Semaphore Flag

Not Allowed

Mode

(3)

5632 tbl 03

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating
Temperature and Supply Voltage

Ambi ent

Grade

Commercial 0OC to +70OC0V2.5V + 100mV

Industrial -40

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Capacitance

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions

IN

Input Capacitance VIN = 3dV 8 pF

C

(3)

OUT

C

NOTES:

1. These parameters are determined by device characterization, but are not
production tested.

2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.

3. C

Outp ut Cap acitance V

OUT also references CI/O.

Absolute Maximum Ratings

Symbol Rating Commercial

TE R M

V
(VDD)

(2 )

TE R M

V
(V

DDQ

)

(2)

TER M

V
(INPUTS and I/O' s)

(3)

BIAS

T

T

STG

JN

T

OUT

(Fo r V

DDQ =

I

OUT

(Fo r V

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed V
supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

3.3V ) DC Output Curre nt 50 mA

DDQ =

2.5V ) DC Output Curre nt 40 mA

Temperature GND V

O

C to +85OC0V2.5V + 100mV

(1)

(2)

OUT

= 3dV 10.5 pF

(1)

& Ind ustri al

V

DD

Terminal Voltag e

with Re spec t to GND

V

DDQ

Te rminal Voltag e

with Re spec t to GND

Input and I/O Terminal
Voltage with Respect to GND

Tempe rature
Under Bias

Storage
Tempe rature

Junc tio n Tempe rature +150

-0.5 to 3.6 V

-0.3 to V

DDQ

-0.3 to V

DDQ

-55 to +125

-65 to +150

DDQ during power

(1)

DD

5632 tbl 04

Max. Unit

5632 tbl 08

+ 0.3 V

+ 0.3 V

5632 tbl 07

Unit

o

o

o

C

C

C

Recommended DC Operating
Conditions with V

Symbol Parameter Min. Typ. Max. Unit

DD

Core Supp ly Voltag e 2.4 2.5 2.6 V

V

V

DDQ

I/O Supply Voltage

V

SS

Ground 0 0 0 V

Inp ut Hi gh Vo lltage
(Address, Control &

V

IH

Data I/ O Inputs)

Inp ut Hi gh Vo ltag e

V

IH

JTAG

Input High Voltage -

V

IH

ZZ, OP T, M /S

IL

Inp ut Lo w Voltag e -0.3

V

Input Low Voltage -

V

IL

ZZ, OP T, M /S

NOTES:

IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

1. V

IH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

2. V
less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
supplied as indicated above.

(3)

_

DDQ at 2.5V

(3)

2.4 2.5 2.6 V

____

1.7

____

1.7

DD

- 0.2V

V

-0.3

____

(1)

____

(1)

____

SS(0V), and VDDQX for that port must be

V

V

V

DDQ

DD

DD

+ 100m V

+ 100m V

(2)

+ 100mV

(2)

(2)

0.7 V

0.2 V

5632 tb l 05

V

V

V

Recommended DC Operating
Conditions with V

Symbol Parameter Min. Typ. Max. Unit

V

DD

Core Sup ply Voltag e 2.4 2. 5 2. 6 V

V

DDQ

I/O Supply Voltage

V

SS

Ground 0 0 0 V

Input Hig h Vo ltag e
(Add re ss , Co ntrol

IH

V

&Data I/O Inp uts )

Input Hig h Vo ltag e

V

IH

JTAG

Input High Voltage -

V

IH

ZZ, O P T, M/S

V

IL

Input Lo w Voltag e -0.3

Input Lo w Vol tag e -

V

IL

ZZ, O P T, M/S

NOTES:

IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

1. V

IH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

2. V
less.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
supplied as indicated above.

(3)

(3)

_

DDQ at 3.3V

3.15 3. 3 3. 45 V

2.0

1.7

DD

- 0.2V

V

-0.3

DD (2.5V), and VDDQX for that port must be

____

V

DDQ

____

V

DD

____

V

DD

(1)

____

(1)

____

(2)

+ 150mV

(2)

+ 100m V

(2)

+ 100m V

0.8 V

0.2 V

V

V

V

5632 tbl 06

8

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

LI

| Input Le ak age Current

|I

LI

| JTAG & ZZ Input Le akage Current

|I

|I

LO

| Outp ut Leakage Curre nt

OL

(3.3V) Outp ut Lo w Vol tage

V

OH

(3.3V) Output Hig h Voltage

V

OL

(2.5V) Outp ut Lo w Vol tage

V

V

OH

(2.5V) Output Hig h Voltage

NOTES:

DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

1. V

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

(1)

(1,3)

(1)

(1)

(1)

(1)

V

DDQ

= Max., VIN = 0V to V

(1,2)

V

DD =

Max., VIN = 0V to V

CE0 = VIH or CE1 = VIL, V

IOL = +4mA, V

IOH = -4mA, V

IOL = +2mA, V

IOH = -2mA, V

DDQ

= Min.

DDQ

= Min. 2.4

DDQ

= Min.

DDQ

= Min. 2.0

(VDD = 2.5V ± 100mV)

DDQ

DD

OUT

= 0V to V

DDQ

70T651/9S

___

___

___

___

___

10 µA

+30 µA

10 µA

0.4 V

___

0.4 V

___

5632 tb l 09

UnitMin. Max.

V

V

DC Electrical Characteristics Over the Operating

(3)

Temperature and Supply Voltage Range

Symbol Parameter Test Condition Version Typ.

DD

Dynamic Operating

I

Current (Both
Ports Active)

(6)

I

SB1

Standb y Current
(Both P orts - TTL
Le ve l Inputs)

(6)

I

SB2

Standb y Current
(One Port - TTL
Le ve l Inputs)

I

SB3

Full Standby Current
(Both P orts - CMOS
Le ve l Inputs)

(6)

I

SB4

Full Standby Current
(One Port - CMOS
Le ve l Inputs)

I

ZZ

Sleep Mode Current
(Both P orts - TTL
Le ve l Inputs)

NOTES:

1. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input

levels of GND to 3.3V.

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 100mA (Typ).

4. V

X = VIL means CE0X = VIL and CE1X = VIH

5. CE

CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

X > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V.

CE

"X" represents "L" for left port or "R" for right port.

SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

6. I

7. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

L

and CER= VIL,

CE

Outputs Disabled

(1)

f = f

MAX

L

= CER = V

CE

f = f

MAX

CE

"A"

Active Po rt Outputs Disable d,
f = f

MAX

IH

(1)

= VIL and CE

(1)

"B"

= V

(5)

IH

Both Ports CEL and

CE

R

> VDD - 0.2V, VIN > VDD - 0.2V

or V

IN

< 0.2V, f = 0

"A"

< 0.2V and CE

CE

VIN > VDD - 0.2V or VIN < 0.2V, Ac tiv e

Po rt, Outp uts Dis ab led , f = f

ZZ

L = ZZR = VIH

(1)

f = f

MAX

(2)

"B"

> VDD - 0.2 V

MAX

(1)

COM'L S 350 475 300 405 300 355 225 305

IND S

COM'L S 115 140 90 120 75 105 60 85

IND S

COM'L S 240 315 200 265 180 230 150 200

IND S

COM'LS210210210210

IND S

(5)

COM'L S 240 315 200 265 180 230 150 200

IND S

COM'LS210210210210

IND S

(VDD = 2.5V ± 100mV)

(4)

(7)

70T651/9S10

Max. Typ.

300 445 300 395

90 145 75 130

200 290 180 255

220220

200 290 180 255

220220

70T651/9S8

Com'l Only

____ ____

____ ____

____ ____

____ ____

____ ____

____ ____

Com'l

& Ind

(4)

(7)

Max. Typ.

70T651/9S12

Com'l
& Ind

(4)

Max. Typ.

70T651/9S15

Com'l Only

(4)

Max. Unit

____ ____

____ ____

____ ____

____ ____

____ ____

____ ____

mA

mA

mA

mA

mA

mA

5632 tbl 10

9

IDT70T651/9S Preliminary

,

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ - 3.3V/2.5V)

Input Pulse Levels

Input Rise/Fall Time s

Input Timing Re ference Leve ls

Output Refere nce Leve ls

Output Load

GND to 3.0V / GND to 2.4V

2ns Max.

1.5V/1.25V

1.5V/1.25V

Figure 1

5632 tbl 11

DATA

∆

t

AA

/

t

ACE

(Typical, ns)

OUT

4

3.5

3

2.5

2

1.5

1

0.5
0

50Ω

50Ω

1.5V/1.25

10pF
(Tester)

Figure 1. AC Output Test load.

0

20

40 60

80 100

120 140

5632 drw03

160

∆

Capacitance (pF) from AC Test Load

Figure 3. Typical Output Derating (Lumped Capacitive Load).

5632 drw 05

10

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

(5)

70T651/9S10

Com'l

& Ind

____

10

____

8

____

8

____

4

____

4

____

3

____

3

____

0

____

0

____

7

____

4

____

5

Symbol Parameter

READ CYCLE

RC

t

t

AA

ACE

t

ABE

t

AOE

t

t

OH

LZ

t

t

LZOB

t

HZ

PU

t

PD

t

SOP

t

t

SAA

SOE

t

Read Cyc le Tim e 8

Address Access Time

Chip Enable Ac cess Time

Byte Enable Access Time

(3)

(3)

Outp ut E nab le A cc e ss Time

Output Hold from Address Change 3

Output Low-Z Time Chip Enable and Se mapho re

Output Low-Z Time Output Enable and Byte Enable

Output Hig h-Z Time

Chip Enab le to Po we r Up Time

(1,2)

(2)

Chip Disabl e to Powe r Do wn Tim e

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time 2 8 2 10 2 12 2 15 ns

Semaphore Output Enable Access Time

70T651/9S8

Com'l Only

____

____

____

____

(1,2)

(1,2)

3

0

03.5040608ns

0

(2)

____

____

____

(4)

(5)

70T651/9S12

Com 'l
& Ind

70T651/9S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max. Min. Max.

____

10

10

5

5

____

____

____

____

8

4

5

____

12

____

12

____

12

____

6

____

6

____

3

____

3

____

0

____

0

____

8

____

6

____

6

15

____

____

____

____

3

3

0

0

____

____

____

____

ns

15 ns

15 ns

7ns

7ns

____

ns

____

ns

____

ns

____

ns

12 ns

8ns

7ns

5632tb l 12

AC Electrical Characteristics Over the

Com' l Onl y

6

0

3

4

4

____

____

____

____

____

____

____

____

3.5

____

____

____

(4)

(5)

70T651/9S10

Com 'l

(5)

& Ind

10

7

7

0

7

0

5

0

____

3

5

5

70T651/9S12

Com' l
& Ind

____

____

____

____

____

____

____

____

4

____

____

____

____

12

____

9

____

9

____

0

____

9

____

0

____

7

____

0

____

6

____

3

____

5

____

5

Operating Temperature and Supply Voltage

70T651/9S8

Symbol Parameter

WRI T E CYCLE

t

WC

t

EW

t

AW

t

AS

t

WP

t

WR

t

DW

t

DH

t

WZ

t

OW

t

SWRD

t

SPS

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE= V

CE

4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

Write Cycle Time 8

Chip Enable to End-of-Write

(3)

Address Valid to End-of-Write 6

Address Set-up Time

(3)

Write Pulse Width 6

Write Recovery Time 0

Data Valid to End-of-Write 4

Data Ho ld Time 0

Write Enable to Output in High-Z

Outp ut Activ e fro m E nd -o f-Write

(1,2)

(1,2)

SEM Flag Write to Read Time

SEM Flag Contention Window

0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when

____

70T651/9S15

Com'l Only

15

12

12

0

12

0

10

0

____

3

5

5

UnitMin. Max. Mi n. Max. Min. Max. Min. Max.

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

8ns

____

ns

____

ns

____

ns

5632 tbl 13

11

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Read Cycles

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

CE

(6)

ACE

t

AOE

(4)

OE

(4)

t

ABE

BEn

R/W

t

LZOB

(1)

(4)

(3,4)

t

BDD

AOE, tACE, tAA, tABE or tBDD.

VALID DATA

tLZ/t

DATA

OUT

BUSY

OUT

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

3. t
has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t

5. SEM = V

6. CE = L occurs when CE

IH.

0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

OH

(2)

t

HZ

.

5632 drw 06

Timing of Power-Up Power-Down

CE

t

PU

I

CC

I

SB

50% 50%

12

t

PD

5632 drw 07

.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

t

WC

(1,5,8)

ADDRESS

(7)

t

HZ

OE

t

AW

t

WP

(2)

t

WR

(3)

CE or SEM

BEn

(9)

(9)

(6)

t

AS

R/W

(7)

t

OW

t

DH

DATA

DATA

OUT

(7)

t

WZ

(4) (4)

t

DW

IN

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

t

WC

ADDRESS

t

AW

BEn

R/W

(9)

(6)

t

AS

(9)

(2)

t

EW

t

DW

t

WR

(3)

t

DH

CE or SEM

(1,5,8)

5632 drw 10

.

IN

DATA

5632 drw 11

NOTES:

1. R/W or CE or BEn = V

2. A write occurs during the overlap (t

WR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.

3. t

IH during all address transitions for Write Cycles 1 and 2.

EW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = V

IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).

8. If OE = V

9. To access RAM, CE = V

IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t

WP.

specified t

DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

13

.

.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

taken to still meet the Write Cycle time (t

WC), the time in which the Address

inputs must be stable. Input data setup and hold times (tDW and tDH) will

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T651/9 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.

During this new RapidWrite Mode, the end of the write cycle is now

defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles. Care must be

now be referenced to the ending address transition. In this RapidWrite
Mode the I/O will remain in the Input mode for the duration of the operations
due to R/W being held low. All standard Write Cycle specifications must
be adhered to. However, t

AS and tWR are only applicable when switching

between read and write operations. Also, there are two additional
conditions on the Address Inputs that must also be met to ensure correct
address controlled writes. These specifications, the Allowable Address
Skew (t

AAS) and the Address Rise/Fall time (tARF), must be met to use the

RapidWrite Mode. If these conditions are not met there is the potential for
inadvertent write operations at random intermediate locations as the
device transitions between the desired write addresses.

Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle

t

WC

(4)

t

WC

ADDRESS

t

WC

(1,3)

(2)

t

EW

CE or SEM

(6)

BEn

t

WR

t

WP

R/W

(5)

t

WZ

DAT A

OUT

IN

DA TA

NOTES:

1. OE = V

2. A write occurs during the overlap (t

3. If the CE or SEM = V

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

6. To access RAM, CE = V

IL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.

EW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

(Figure 1).

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

t

DH

t

DW

t

DH

t

DW

t

DW

(5)

t

OW

t

DH

5632 drw 08

14

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle

Symbol Parameter Min Max Unit

t

AAS

t

ARF

NOTE:

1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.

Allowable Address Skew for RapidWrite Mode

Address Rise/Fall Time for RapidWrite Mode 1.5

____

1ns

____

(1)

V/ns

5632 tbl 14

Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle

A

0

t

ARF

t

ARF

A

17

t

AAS

(1)

NOTE:

16 for IDT70T659.

1. A

5632 drw 09

15

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side

t

SAA

A0-A

SEM

2

(1)

I/O

VALID ADDRESS

t

AW

t

EW

DATA VALID

t

t

AS

WP

t

DW

IN

t

WR

t

DH

VALID ADDRESS

t

ACE

t

SOP

DATA

VALID

t

OUT

OH

(2)

(1)

R/W

t

SWRD

t

SOE

OE

Write Cycle

NOTES:

0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for

1. CE
appropriate BEn controls.

2. "DATA

OUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention

A

(2)

SIDE "A"

(2)

SIDE

"B"

0"A"-A2"A"

R/W

SEM

A

0"B"-A2"B"

R/W

"A"

"A"

"B"

MATCH

t

t

SPS

MATCH

SOP
Read Cycle

5632 drw 12

(1,3,4)

.

SEM

"B"

NOTES:

OR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.

1. D

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W

SPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

4. If t

"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

5632 drw 13

.

16

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

(6)

70T651/9S8

Com'l Only

70T651/9S10

Com 'l

(6)

& Ind

Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max.

IH

BUSY TIMING (M/ S=V

BAA

t

BDA

t

BAC

t

t

BDC

APS

t

t

BDD

t

WH

BUSY TIMING (M/ S=V

WB

t

t

WH

)

BUSY Access Time fro m Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time fro m Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time

BUSY Disable to Valid Data

Write Ho ld Afte r BUSY

IL

)

BUSY Input to Write

Write Ho ld Afte r BUSY

(2)

(3)

(5)

(4)

(5)

____

____

____

____

2.5

____

____

8

____

8

____

8

____

8

____

2.5

____

8

____

6

____

0

____

6

7

0

7

PORT-TO-PORT DELAY TIMING

t

t

WDD

DDD

Write Pulse to Data Delay

(1)

Write Data Valid to Read Data De lay

(1)

____

____

____

12

____

12

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

____

____

____

____

70T651/9S12

Com'l

70T651/9S15

Com'l Only

& In d

____

10

____

10

____

10

____

10

2.5

____

10

9

0

9

____

14

____

14

12

12

12

12

____

12

____

____

____

16

16

____

____

____

____

2.5

____

12

12

____

____

15 ns

15 ns

15 ns

15 ns

____

15 ns

____

____

0

____

20 ns

20 ns

5632 tbl 15

IH)".

Uni t

ns

ns

ns

ns

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

70T651/ 9S8

Com'l Only

Symbol Parameter

SLEEP MODE TIMING (ZZx=V

ZZS

t

t

ZZR

t

ZZPD

t

ZZPU

Sleep Mode Set Time 8

Sleep Mode Reset Time 8

Sleep Mode Power Down Time

Sleep Mode Power Up Time

IH

)

(5)

(5)

Min. Max. Min. Max. Min. Max. Min. Max.

8

____

NOTES:

1. Timing is the same for both ports.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.

3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

5. This parameter is guaranteed by device characterization, but is not production tested.

17

(4)

____

____

____

0

(1,2,3)

70T651/ 9S10

Com 'l

(4)

& In d

10

10

10

____

____

____

____

0

70T651/ 9S12

Com 'l
& Ind

12

12

12

____

____

____

____

0

70T651/ 9S15

Com'l Only

15

15

15

____

5632 tbl 15a

____

____

____

0

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)

t

WC

(2,4,5)

t

BAA

MATCH

t

WP

t

DW

MATCH

t

WDD

VALID

t

DDD

(3)

ADDR

DATA

ADDR

BUSY

DATA

R/W

IN "A"

OUT "B"

"A"

"A"

"B"

"B"

t

APS

(1)

NOTES:

1. To ensure that the earlier of the two ports wins. t

0L = CE0R = VIL; CE1L = CE1R = VIH.

2. CE

3. OE = V

4. If M/S = V

IL for the reading port.

IL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

APS is ignored for M/S = VIL (SLAVE).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

t

BDA

t

DH

t

BDD

VALID

.

5632 drw 14

Timing Waveform of Write with BUSY (M/S = VIL)

t

WP

R/W

"A"

(3)

t

WB

BUSY

"B"

R/W

"B"

NOTES:

WH must be met for both BUSY input (SLAVE) and output (MASTER).

1. t

2. BUSY is asserted on port "B" blocking R/W

WB only applies to the slave mode.

3. t

"B", until BUSY"B" goes HIGH.

(2)

18

t

WH

(1)

5632 drw 15

.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)

(1)

ADDR

and

CE

CE

BUSY

"A"
"B"

"A"

"B"

"B"

t

APS

(2)

ADDRESSES MATCH

t

BAC

t

BDC

Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing

ADDR

ADDR

"A"

"B"

(M/S = VIH)

(1,3,4)

t

APS

ADDRESS "N"

(2)

MATCHING ADDRESS "N"

5632 drw 16

.

t

BAA

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2. If t

X = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.

3. CE

0X = OEX = BEnX = VIL. CE1X = VIH.

4. CE

t

BDA

5632drw 17

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

70T651 /9S8

Com' l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

AS

t

WR

t

INS

t

INR

t

NOTES:

1. Timing is the same for both ports.

2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

Address Set-up Time 0

Write Recovery Time 0

Interrupt Se t Time

Interrup t Re set Time

____

____

____

____

(3)

70T651/9S10

Com'l

& Ind

0

0

____

8

____

8

(1,2)

70T651 /9S12

____

____

Com' l

& Ind

____

0

____

0

12

12

(3)

____

____

10

10

70T651 /9S15

Com'l Only

0

0

____

____

____

____

15 ns

15 ns

5632 tbl 16

,

ns

ns

19

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

ADDR

CE

R/W

INT

"A"

"A"

(3)

"A"

"B"

INTERRUPT SET ADDRESS

(4)

t

AS

(4)

t

INS

(1)

t

WC

(2)

t

WR

(5)

t

RC

ADDR

CE

"B"

OE

INT

"B"

(3)

"B"

"B"

INTERRUPT CLEAR ADDRESS

(4)

t

AS

(4)

t

INR

(2)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

X = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1 X = VIL.

3. CE

4. Timing depends on which enable signal (CE or R/W) is asserted last.

5. Timing depends on which enable signal (CE

or R/W) is de-asserted first.

5632 drw 18

5632 drw 19

.

.

Truth Table III — Interrupt Flag

(1,4)

Left Port Right Port

L

CE

L

OE

L

A

17L-A0L

(5)

INT

R/W

L

R

CE

R

OE

R

A

17R-A0R

(5)

INT

L L X 3FFFF XXXX X L

XXXXXXLL3FFFFH

XXX X L

X L L 3FFFE H

(3)

(2)

L L X 3FFFE X Set Left INTL Flag

X X X X X Re s e t Le ft INTL Flag

NOTES:

1. Assumes BUSY

2. If BUSY

3. If BUSY

L and INTR must be initialized at power-up.

4. INT

17x is a NC for IDT70T659. Therefore, Interrupt Addresses are 1FFFF and 1FFFE.

5. A

L = BUSYR =VIH. CE0X = VIL and CE1 X = VIH.

L = VIL, then no change.
R = VIL, then no change.

20

R

(2)

Se t Right INTR Flag

(3)

Res et Rig ht INTR Flag

FunctionR/W

5632 tb l 17

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table IV —
Address BUSY Arbitration

Inputs Outputs

(4)

AOL-A

(5)

CE

(5)

L

CE

R

X X NO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

LL MATCH (2) (2)

AOR-A

17L

17R

BUSY

(1)

L

BUSY

(1)

R

Function

Write Inhibit

(3)

NOTES:

1. Pins BUSY
IDT70T651/9 are push-pull, not open drain outputs. On slaves the BUSY

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t

3. Writes to the left port are internally ignored when BUSY
when BUSY

4. A

5. CE

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

R outputs are driving LOW regardless of actual logic level on the pin.

17 is a NC for IDT70T659. Address comparison will be for A0 - A16.

X = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.

Truth Table V — Example of Semaphore Procurement Sequence

5632 tbl 18

input internally inhibits writes.

(1,2,3)

Functions D0 - D35 Left D0 - D35 Right Sta tus

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes " 0" to Semap hore 0 1 No chang e . Rig ht side has no write ac cess to s emap ho re

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Se mapho re 1 0 No chang e. Le ft port has no write acce s s to s emaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T651/9.

2. There are eight semaphore flags written to via I/O

3. CE = V

IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.

5632 tbl 19

Functional Description

The IDT70T651/9 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T651/9 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = HIGH). When a port is enabled, access to the
entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt
flag (INT

L) is asserted when the right port writes to memory location

3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left port
writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 3FFFF. The
message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T659)
is user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FFFE and 3FFFF are not used

21

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T651/9 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.

A

18

CE

MASTER
Dual PortRAM

BUSY

BUSY

L

0

R

SLAVE
Dual Port RAM

BUSY

CE

0

R

BUSY

L

long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.

Semaphores

The IDT70T651/9 is an extremely fast Dual-Port 256/128K x 36
CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an ex­ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.

The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro­tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE

0 and CE 1, the Dual-Port RAM chip enables, and

SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-

MASTER
Dual PortRAM

BUSY

L

BUSY

CE

1

R

SLAVE
Dual Port RAM

BUSY

L

CE

BUSY

1

R

chip power down circuitry that permits the respective port to go into standby
mode when not selected.

Systems which can best use the IDT70T651/9 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems

5632 drw 20

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70T651/9 Dual-Port RAMs.

.

can benefit from a performance increase offered by the IDT70T651/9s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.

If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.

Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T651/9 does not use its semaphore

Width Expansion with Busy Logic
Master/Slave Arrays

When expanding an IDT70T651/9 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the

flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.

master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T651/9 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen­dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then

22

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

verifies its success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side processor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.

The eight semaphore flags reside within the IDT70T651/9 in a
separate memory space from the Dual-Port RAM. This address space
is accessed by placing a low input on the SEM pin (which acts as a chip
select for the semaphore flags) and using the other control pins (Address,
CE0, CE1,R/W and BEn) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the flag
will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough
discussion on the use of this feature follows shortly.) A zero written into the
same location from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE
signals need to be active. (Please refer to Truth Table II). Furthermore,
the read value is latched into one side’s output register when that side's
semaphore select (SEM, BEn) and output enable (OE) signals go active.
This serves to disallow the semaphore from changing state in the middle
of a read cycle due to a write cycle from the other side.

A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success­fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during

the gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore
request latches feed into a semaphore flag. Whichever latch is first to
present a zero to the semaphore flag will force its side of the semaphore
flag LOW and the other side HIGH. This condition will continue until a one
is written to the same semaphore request latch. If the opposite side
semaphore request latch has been written to zero in the meantime, the
semaphore flag will flip over to the other side as soon as a one is written
into the first request latch. The opposite side flag will now stay LOW until
its semaphore request latch is written to a one. From this it is easy to

LPORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

D

WRITE

SEMAPHORE

READ

Figure 4. IDT70T651/9 Semaphore Logic

SEMAPHORE

REQUEST FLIP FLOP

Q

Q

RPORT

0

D

D

WRITE

SEMAPHORE
READ

5632 drw 21

understand that, if a semaphore is requested and the processor which
requested it no longer needs the resource, the entire system can hang up
until a one is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.

One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema­phore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.

23

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

n

o

i

t
a

r

e

p
O

l

a
m

r

o
N

,

d

e
w

o

l

l

a
s

e

t

i

r
w
r

o
s

d

a

e

r
o
N

e

d

o
M
p

e

e

l
S

R
Z
Z

t

2
2

w

r
d

2
3
6
5

U
P
Z
Z

t

Z
Z

I

(1,2)

d

e
w

o

l

l

a
s

e

t

i

r
w
r

o
s

d

a

e

r
w

e

n
o
N

S
Z
Z

t

n

o

i

t

a

r

e

p
O

l

a
m

r

o
N

0

E
C

Z
Z

S
S
E
R
D
D
A

D

I

L
A
V

S
S
E
R
D
D
A

A
T
A
D

D

I

L
A
V

A
T
A
D

D
P
Z
Z

t

D
D

I

1 = VIH.

Timing Waveform of Sleep Mode

24

NOTES:

1. CE

2. All timing is same for Left and Right ports.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Sleep Mode

The IDT70T651/9 is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will meet lowest possible power
conditions. The sleep mode timing diagram shows the modes of operation:
Normal Operation, No Read/Write Allowed and Sleep Mode.

For a period of time prior to sleep mode and after recovering from sleep
mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read

operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).

During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal buffer. All outputs will remain in high-Z state while
in sleep mode. All inputs are allowed to toggle. The RAM will not be selected
and will not perform any reads or writes.

JTAG Timing Specifications

t

JCYC

t

t

JCL

JR

t

JCH

TCK

t

JF

Device Inputs

(1)

/

TDI/TMS

t

JStJH

(2)

TDO

/

t

JRSR

Device Outputs

TRST

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS, TCK and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical
Characteristics

Symbol Parameter Min. Max. Units

JCYC

t

t

JCH

JCL

t

t

JR

t

JF

JRST

t

t

JRSR

JCD

t

t

JDC

t

JS

JH

t

JTAG Clock Input Period 100

JTAG Clock HIGH 40

JTAG Clock Low 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data Output

JTAG Data Output Hold 0

(1,2,3,4,5)

____

____

JTAG Reset 50

____

JTAG Setup 15

JTAG Hold 15

70T651/ 9

____

____

____

(1)

3

(1)

3

____

____

25 ns

____

____

____

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

5632 tbl 20

t

JDC

JCD

t

x

5632 drw 23

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

5. JTAG cannot be tested in sleep mode.

25

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Fi eld Val ue Description

Revision Numbe r (31:28) 0x0 Rese rve d for version numbe r

IDT Device ID (27:12)

IDT JEDEC ID (11:1) 0x33 All ows unique id entific atio n o f dev ice vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

NOTE:

1. Device ID for IDT70T659 is 0x339.

0x338

(1)

Defines IDT part numb er 70T651

Scan Register Sizes

Register Name Bit Size

Instruction (IR) 4

Bypass (BYR) 1

Identific atio n (IDR) 32

Boundary Scan (BSR) Note (3)

5632 tbl 2 2

5632 tb l 21

System Interface Parameters

Instruction Code Descripti on

EXTEST 0000 Fo rces contents of the boundary scan cells onto the de vice outputs

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vendor ID cod e and places the

register between TDI and TDO.

HIGHZ

CLAMP 0011

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

RESERVED

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, TCK and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.

0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.

(2)

SAMPLE allows data from device inputs

and outputs
in the bound ary sc an ce lls and shifted serially thro ug h TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.

All Other Codes

Se veral comb inatio ns are re serve d. Do not use code s o ther than those
identifie d abo v e .

(1)

to be captured

(1)

.

5632 tbl 23

26

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

XXXXX

IDT

Device

Type

NOTE:

1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank
I

BC
DR
BF

8
10
12
15

S Standard Power

70T651
70T659

Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)

256-ball BGA (BC-256)
208-pin PQFP (DR-208)
208-ball fpBGA (BF-208)

Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial Only

9Mbit(256Kx 36) Asynchronous Dual-Port RAM
4Mbit(128Kx 36) Asynchronous Dual-Port RAM

(1)

(1)

peed in nanoseconds

S

5632 drw 24

.

Preliminary Datasheet: Definition

"PRELIMINARY' datasheets contain descriptions for products that are in early release.

Datasheet Document History:

04/25/03: Initial Datasheet
10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table

Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table
Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only
Page 10 Added Capacitance Derating Drawing
Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables
Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table
Page 12 Added tLZOB to the Waveform of Read Cycles Drawing
Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing
Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information
Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms

10/20/03: Page 15 Corrected tARF to 1.5V/ns Min.

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Santa Clara, CA 95054 fax: [phone] [e-mail]

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

27

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