Datasheet IDT70T633-1S Datasheet (IDT)

查询IDT70T631S供应商

HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

Features

◆◆

◆

◆◆

True Dual-Port memory cells which allow simultaneous access of the same memory location

◆◆

◆

◆◆

High-speed access

– Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.)

◆◆

◆

◆◆

RapidWrite Mode simplifies high-speed consecutive write cycles

◆◆

◆

◆◆

Dual chip enables allow for depth expansion without external logic

◆◆

◆

◆◆

IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device

◆◆

◆

◆◆

M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave

◆◆

◆

◆◆

Busy and Interrupt Flags

Functional Block Diagram

UB

L

LB

L

PRELIMINARY

IDT70T633/1S

◆◆

◆

◆◆

Full hardware support of semaphore signaling between ports on-chip

◆◆

◆

◆◆

On-chip port arbitration logic

◆◆

◆

◆◆

Fully asynchronous operation from either port

◆

Separate byte controls for multiplexed bus and bus matching compatibility

◆◆

◆

◆◆

Sleep Mode Inputs on both ports

◆◆

◆

◆◆

Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages

◆◆

◆

◆◆

Single 2.5V (±100mV) power supply for core

◆◆

◆

◆◆

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port

◆◆

◆

◆◆

Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array

◆◆

◆

◆◆

Industrial temperature range (–40°C to +85°C) is available for selected speeds

UB

R

LB

R

R/

W

L

CE

0L

CE

1L

OE

L

I/O0L-I/O

17L

(1)

A

18L

A

0L

(2,3)

BUSY

L

SEM

L

(3)

INT

L

NOTES:

1. Address A18x is a NC for IDT70T631.

2. BUSY is an input as a Slave (M/S=V

B E 0 L

Dout0-8_L Dout9-17_L

512/256K x 18

Din_L

Address Decoder

CE

0L

CE

1L

IL) and an output when it is a Master (M/S=VIH).

OE

R/W

ZZ

ADDR_L

L

(4)

L

B E 1 L

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/S

ZZ

CONTROL

LOGIC

B

E

0

1

R

Dout0-8_R

Dout9-17_R

Din_R

ADDR_R

R/W

ZZ

Address Decoder

OE

R

CE

0R

CE

R

(4)

R

1R

3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

1

R/

W

R

CE

0R

CE

1R

OE

R

I/O0R-I/O

17R

(1)

A

18R

A

0R

TDI

BUSY SEM

INT

JTAG

R R (3)

R

(2,3)

5670 drw 01

TDO

TCK TMS

TRST

NOVEMBER 2003

DSC-5670/3

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T651/9 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performance levels.

The 70T633/1 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (V

DD) remains at 2.5V.

2

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

03/13/03

A3

A2

A1

NC

TDI

NC

B1

NC

C1

NC

D1

NC

E1

I/O

10R

F1

I/O

11L

G1

NC

H1

NCH2I/O

J1

I/O

13L

K1

NC

L1

I/O

15L

M1

I/O

16R

N1

NCN2I/O

P1

NCP2I/O

R1

NCR2NCR3TRSTR4A

T1

NC

B3

B2

NC

C2

C3

I/O

9L

D2

D3

I/O

9R

E2

E3

I/O

10L

F2

NCF3I/O

G2

G3

NC

I/O

H3

12R

J2

J3

I/O

14R

I/O

K2

K3

NC

I/O

L3

L2

I/O

NC

M2

M3

I/O

16L

N3

17R

P3

17L

T2

TCKT3NC

TDO

V

NC

NCE4V

NCH4V

NCM4V

NC

TMSP4A

(1,2,3)

SS

11R

12L

13R

14L

15R

A4

A

B4

A

C4

A

D4

F4

V

G4

V

J4

V

K4

V

L4

V

N4

T4

A

17L

18L

16L

V

DD

DDQL

DDQR

DDQL

DDQR

V

DD

16R

18R

17R

A5

A

B5

(4)

A

C5

A

D5

V

E5

F5

G5

H5

J5

K5

L5

M5

N5 N6

V

P5

A

R5

(4)

A

T5

A

14L

15L

13L

DDQL

V

DD

V

DD

V

SS

V

SS

ZZ

V

SS

V

DD

V

DD

DDQR

13R

15R

14R

70T633/1BC

BC-256

(5,6)

256-Pin BGA

Top View

A6

A7

A

11L

12L

10L

DDQL

DD

NC

SS

V

SS

V

SS

NC

V

DD

DDQR

10R

12R

11R

B7

C7

D7

V

E7

F7

G7

H7

J7

K7

L7

M7

N7

V

P7

R7

T7

8L

A

9L

A

7L

DDQR

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DDQL

A

7R

A

9R

A

8R

A

B6

A

C6

A

D6

V

E6

V

F6

G6

V

H6

V

J6

R

K6

L6

M6

V

P6

A

R6

A

T6

A

A8

NC

B8

UB

L

C8

NC

D8

V

DDQR

E8

V

SS

F8

V

SS

G8

V

SS

H8

V

SS

J8

V

SS

K8

V

SS

L8

V

SS

M8

V

SS

N8

V

DDQL

P8

NCP9LB

R8

UB

R

T8

NC

A9

B9

C9

D9

V

E9

F9

G9

H9

J9

K9

L9

M9

N9

V

R9

T9

CE

LB

DDQL

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQR

CE

A10

1L

OE

L

B10

0L

R/W

L

C10

SEM

L

D10

V

DDQL

E10

SS

V

SS

F10

V

SS

G10

V

SS

H10

V

SS

J10

V

SS

K10

V

SS

L10

V

SS

M10

SS

V

SS

N10

V

DDQR

P10

R

SEM

R

R10

0R

R/W

R

T10

1R

OE

R

A11

INT

B11

NC

C11

BUSY

D11

V

DDQR

E11

V

DD

F11

V

SS

G11

V

SS

H11

V

SS

J11

V

SS

K11

V

SS

L11

V

SS

M11

V

DD

N11

V

DDQL

P11

BUSY

R11

M/S

T11

INT

A12

A

5L

L

B12

A

4L

C12

A

6L

L

D12

V

DDQR

E12

V

DD

F12

V

DD

G12

V

SS

H12

V

SS

J12

ZZ

L

K12

V

SS

L12

V

DD

M12

V

DD

N12

V

DDQL

P12

A

6R

R

R12

A

4R

T12

R

A

5R

A13

B13

C13

D13

E13

V

F13

V

G13

V

H13

V

J13

V

K13

V

L13

V

M13

V

N13

P13

R13

T13

A

2L

A

1L

A

3L

V

DD

DDQR

DDQL

DDQR

DDQL

V

DD

A

3R

A

1R

A

2R

A14

A

B14

NC

C14

OPT

D14

NC

E14

NC

F14

I/O

G14

I/O

H14

NC

J14

I/O

K14

NC

L14

I/O

M14

I/O

N14

NC

P14

NC

R14

OPT

T14

A

0L

L

6R

5L

4R

2L

1R

R

0R

A16

A15

NC

B15

B16

NC

C16

C15

NC

D15

D16

NC

E16

E15

I/O

7L

F16

F15

NC

G16

G15

NC

H16

H15

NC

J15

J16

I/O

3R

K16

K15

NC

L16

L15

NC

M16

M15

I/O

1L

N16

N15

I/O

0R

P15

P16

NC

R16

R15

NC

T15NCT16

I/O

NC

8L

8R

7R

6L

5R

4L

3L

2R

0L

,

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground supply.

18X is a NC for IDT70T631.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

3

5670 drw 02c

,

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3,8)

(con't.)

03/13/03

V

DDQR

V

I/O

V

DDQL

V

I/O

V

DDQR

ZZ V V

V V

V

DDQL

V

I/O

V

DDQR

V

I/O

V

DDQL

SS

9R

10L

10R

11L

11R

SS

12L

12R

DD DD

SS SS

SS

13R

13L

14R

14L

SS

15R

15L

16R

16L

17R

17L

SS

NC

)

4

(

L

D

8

7

6

5

C

D

1

V

N

A

N

4

3

2

1

4

1

1 2 3 4

9L

5 6 7 8 9 10 11 12 13 14 15

R

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

1

7

9

8

0

3

4

1

A

0

9

8

7

4

3

1

3

2

1

4

L

3

2

1

0

L

1

A

6

5

3

1

L

1

9

8

A

4

3

2

1

3

1

70T633/1DD

DD-144

144-Pin TQFP

Top View

5

4

9

8

7

6

4

0

4

5

L

1

0

L

D

L

B

7

B

A

U

L

0

9

8

3

2

1

S

E

D

S

C

V

7

6

5

4

2

1

(5,6,7)

(8)

1

5

4

3

2

5

7

6

5

L

Y

L

S

M

W

E

/

E S

O

R

3

2

1

2

1

0

9

8

6

5

L

T

C

U

N

B

I

N

0

9

8

2

1

3

2

6

L

6

5

4

3

A

7

6

5

4

1

5

4

7

6

D

L

2

A

3

1

8

6

S

L

1

0

D

S

A

V

2

1

0

9

1

0

1

108 107 106 105 104 103 102 101 100

1

0

9

2

7

6

7

OPT

L

V

DDQR

V

SS

I/O

8L

I/O

8R

I/O

7L

I/O

7R

I/O

6L

I/O V

SS

V

DDQL

I/O I/O V

SS

V

DDQR

V

DD

V

DD

V

SS

V

SS

ZZ V

DDQL

I/O I/O I/O I/O V

SS

V

DDQR

I/O I/O I/O I/O I/O I/O V

SS

V

DDQL

OPT

6R

5L 5R

L

4R 4L 3R 3L

2R 2L 1R 1L 0R 0L

R

,

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

)

D D

V

R

4

C

(

7

6

5

4

3

2

1

0

R

N

1

8

A

1

A

1

A

9

1

A

R

8

7

B

A

L

U

S

D

R

1

0

D

E

V

C

R

S

E

M

W

V

/

O

E

R

S

R

S

/

6

T

Y

A

M

S

N

I

U B

R

5

4

3

2

A

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground.

18X is a NC for IDT70T631.

5. Package body is approximately 20mm x 20mm x 1.4mm.

6. This package code is used to reference the package diagram.

7. 8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package.

8. This text does not indicate orientation of the actual part-marking.

9. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.

4

S

D

R

1

0

A

S

D

V

5670 drw 02a

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations

03/12/03

21

I/O

9L

A B

NC V

(1,2,3)

(con't.)

9876543

A

SS

TDO

NC

SS

NC

TDI

A

17L

12L

A

16L

A

9L

A

13L

NC

NCA

8L

CE

0L

10

V

11

DD

SS

SEM

BUSY

INT

L

A

5L

L

1412 13

15

A

0L

A

4L

1L

A

OPT

V

DDQR

V

SS

1716

A

V

SS

NC

L

NC

B

I/O

8L

C D E F G H J K L M N P R T U

V

DDQL

NC

I/O

11L

V

DDQL

NC

DD

V

DDQL

I/O

14RVSS

NC I/O

V

DDQL

NC

I/O

16R

SS

V

NC I/O

SS

V

I/O

9R

V

SS

NC

11R

I/O

SS

V

NC V

V

DD

14LVDDQR

NC

SS

V

I/O

16LVDDQR

NC I/O

17LVDDQL

NC

V

DDQR

I/O

10L

V

DDQR

NC

I/O

12L

DDQR

VSSZZ

V

I/O

(4)

DD

A

18L

A

15LA11LA7L

NC V

10R

V

SS

NC

12R

R

A

10L

A

14L

CE

1L

V

UB

L

LB

L

SS

V

DD

OE

L

70T633/1BF

BF-208

(5,6)

208-Ball BGA

CE

(7)

DD

V

NC

V

SS

CE

0R

V

SS

1R

V

DD

OE

R

I/O

13R

I/O

15RVSS

NC I/O

17R

V

DD

V

I/O

NC

TCK

TMS

NC

SS

13L

15L

A

16RA12RA8R

TRST

A

13RA9R

A

17R

(4)

A

14RA10R

18R

A

11RA7R

A

15R

Top View

NC

UB

R

LB

R

R/

NC

SEM

BUSY

R/

M/

V

NC

I/O

7L

SS

V

NC

I/O

5L

SS

V

SS

I/O

4R

V

SS

I/O

2R

NC

V

SS

I/O0RV

V

SS

I/O

V

I/O

V

I/O

V

I/O

SS

NC

DDQR

NC

DDQR

V

SS

DDQR

NC

DDQR

NC

C

7R

D E F G H

5R

J K

4L

L M

2L

N P

R T

0L

U

A

2L

A

6

L

W

L

DD

A

3L

A

4R

INT

R

A

1R

A

5R

R

A

2R

A

6R

W

R

A

0R

A

3R

S

I/O

V

DD

V

NC

I/O

6L

V

SS

I/O

NC V

V

DD

ZZ

L

V

I/O

3R

I/O

NC

SS

I/O

1R

V

NC I/O

V

SS

V

SS

V

DD

OPTRNC I/O

DDQL

NC

DDQL

NC

V

DDQL

NCV

DDQL

NC

8R

6R

DD

3L

1L

NOTES:

DD pins must be connected to 2.5V power supply.

1. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

2. All V

3. All V

4. A

SS (0V).

set to V

SS pins must be connected to ground.

18X is a NC for IDT70T631.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

5

5670 drw 02b

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

0L

CE

R/W

OE

A

0L

I/O

0L

SEM

INT

BUSY

L

UB

L

LB

L

- A

- I/O

L

,

CE

1L

(1)

18L

17L

L

V

DDQL

OPT

ZZ

L

CE

0R

,

CE

1R

R/W

R

OE

R

(1)

A0R - A

18R

I/O0R - I/O

17R

SEM

R

INT

R

BUSY

R

UB

R

LB

R

V

DDQR

L

OPT

ZZ

R

M/S Master or Slave Select (Input)

V

DD

V

SS

TDI Test Data Input

TDO Test Data Outp ut

TCK Te st Logic Clock (10MHz) (Input)

TMS Test Mode Select (Input)

TRST

Chip Enables (Input)

Read/ Write E nable (Input)

Outp ut Enable (Input)

Address (Input)

Data Inp ut/Outp ut

Semapho re Enable (Input)

Interrup t Flag (Outp ut)

Busy Flag (Output)

Upper Byte Select (Input)

Lower Byte Select (Input)

Power (I/O Bus ) (3.3V o r 2.5V )

R

Optio n fo r sele c ting V

Sleep Mode Pin

Power (2.5V)

(2)

(Input)

Ground (0V) (Input)

Reset (Initialize TAP Controlle r) (Input)

(4)

(Input)

DDQX

(2,3 )

(2)

(Input)

(5)

5670 tb l 01

NOTES:

1. Address A

2. V

applying inputs on I/O

3. OPT

If OPT levels and V port's I/Os and controls will operate at 2.5V levels and V

18x is a NC for IDT70T631.

DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

X.

X selects the operating voltage levels for the I/Os and controls on that port.

X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

DDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.

5. BUSY is an input as a Slave (M/S=V

IH).

(M/S=V

IL) and an output when it is a Master

6

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control

OE SEM CE

CE

0

1

UB LB

R/W ZZ

Upper Byte

9-17

I/O

(1)

Lower Byte

I/O

0-8

MODE

X H H X X X X L Hig h-Z Hig h-Z De s e lec te d–Powe r Do wn

X H X L X X X L High -Z High -Z De sele c te d –P o we r Do wn

X H L H H H X L High-Z High-Z Both Bytes Deselected

IN

D

IN

OUT

Write to Lower Byte

Write to Bo th By te s

Read Lo we r Byte

Read Bo th Byte s

XHLHHLLLHigh-Z D

XHLHLHLL D

XHLHLLLL D

IN

High-Z Write to Uppe r Byte

LHLHHLHLHigh-ZD

LHLHLHHL D

LHLHLLHLD

OUT

Hig h-Z Re ad Uppe r Byte

D

H H L H L L X L High-Z High-Z Outputs Dis abled

XXXXXXXHHigh-ZHigh-ZHigh-Z Sleep Mode

5670 tbl 02

NOTE:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

Truth Table II – Semaphore Read/Write Control

(1)

Inputs

(2)

CE

R/W

OE UB LB SEM

HHLLLLDATA

H

↑

XXL L X DATAINWrite I/O0 into Semaphore Flag

LXXXX L

NOTES:

1. There are eight semaphore flags written to I/O

2. CE = L occurs when CE

0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.

3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = V

Outputs

I/O

1-17

OUT

DATA

______ ______

I/O

0

OUT

Read Data in Se maphore Flag

Not Allowed

IL.

(1)

Mode

(3)

5670 tbl 03

7

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating Temperature and Supply Voltage

Ambi ent

Grade

Commercial 0OC to +7 0OC0V2.5V

Industrial -40

NOTE:

1. This is the parameter T

Absolute Maximum Ratings

Symbol Rating Commercial

TER M

V

(VDD)

(2)

V

TER M

(V

DDQ

)

(2)

V

TE RM

(INPUTS and I/O's)

(3)

T

BIAS

STG

T

JN

OUT

(For V

DDQ =

I

OUT

(For V

I

3.3V) DC Output Current 50 mA

DDQ =

2.5V) DC Output Current 40 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Capacitance

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol Parameter Conditions

IN

Input Capaci tance VIN = 3dV 8 pF

C

(3)

C

OUT

Output Capacitance V

NOTES:

1. These parameters are determined by device characterization, but are not production tested.

2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.

OUT also references CI/O.

3. C

Temperature GND V

O

C to +85OC0V2.5V + 100mV

A. This is the "instant on" case temperature.

(1)

& Industrial

V

DD

Te r m in al V o lta g e

-0.5 to 3.6 V

with Re spect to GND

V

DDQ

Terminal Voltage

-0.3 to V

DDQ

with Re spect to GND

Inp u t a nd I/O Termin al

-0.3 to V

DDQ

Voltage with Respect to GND

Temperature

-55 to +125

Under Bi as

Storage

-65 to +150

Temperature

Junction Te mpe rature +150

(1)

(2)

OUT

= 3dV 10.5 pF

(1)

DD

+

100mV

5670 tbl 0 4

Unit

+ 0.3 V

o

C

o

C

o

C

5670 tbl 07

DDQ during power

Max. Unit

5670 tbl 08

Recommended DC Operating Conditions with V

Symbol Parameter Min. Typ. Max. Unit

DD

Core Sup ply Vol tage 2.4 2.5 2.6 V

V

DDQ

I/O Supply Voltage

V

SS

Ground 0 0 0 V

Input Hig h Vo ll tag e (Address, Control &

IH

V

Data I/O Inputs)

Input Hig h Vo ltag e

V

IH

JTAG

Input High Voltage -

IH

V

ZZ, O PT, M/ S

IL

Input Low Voltage -0.3

V

Input Lo w Vo ltag e -

IL

V

ZZ, O PT, M/ S

NOTES:

IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

1. V

IH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

2. V less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V supplied as indicated above.

(3)

_

DDQ at 2.5V

(3)

2.4 2.5 2.6 V

____

1.7

____

1.7

DD

V

-0.3

____

- 0.2V

(1)

____

(1)

____

SS (0V), and VDDQX for that port must be

V

DDQ

DD

+ 100mV

(2)

0.7 V

0.2 V

5670 tbl 05

V

Recommended DC Operating Conditions with V

Symbol Parameter Min. Typ. Max. Unit

V

DD

Core Supply Voltage 2.4 2.5 2.6 V

V

DDQ

I/O Supply Voltage

V

SS

Ground 0 0 0 V

Input Hig h Vol tag e (Address, Control

IH

V

&Data I/ O Inputs)

Input Hig h Vol tag e

V

IH

JTAG

Input High Vo ltage -

V

IH

ZZ, O PT, M / S

V

IL

Input Low Voltage -0. 3

Input Low Voltage -

V

IL

ZZ, O PT, M / S

NOTES:

IL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

1. V

IH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

2. V less.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V supplied as indicated above.

(3)

_

DDQ at 3.3V

3.15 3.3 3.45 V

2.0

1.7

V

DD

- 0.2V

-0.3

DD (2.5V), and VDDQX for that port must be

____

V

DDQ

+ 150mV

____

V

DD

____

V

DD

(1)

____

(1)

____

(2)

+ 100mV

(2)

+ 100mV

0.8 V

0.2 V

(2)

5670 tbl 06

V

8

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

LI

| Input Le ak ag e Curre nt

|I

LI

| JTAG & ZZ Input Le ak ag e Curre nt

|I

LO

| Output Le akag e Curre nt

V

OL

(3.3V) Output Low Vo ltage

OH

(3.3V) Output High Voltage

V

OL

(2.5V) Output Low Vo ltage

V

OH

(2.5V) Output High Voltage

NOTES:

DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

1. V

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

(1)

(1,3)

(1)

V

DDQ

= Max., VIN = 0V to V

(1,2)

V

DD =

Max., VIN = 0V to V

CE0 = VIH or CE1 = VIL, V

IOL = +4mA, V

IOH = -4mA, V

IOL = +2mA, V

IOH = -2mA, V

DDQ

= Min.

DDQ

= Min. 2.4

DDQ

= Min.

DDQ

= Min. 2.0

(VDD = 2.5V ± 100mV)

DDQ

DD

OUT

= 0V to V

DDQ

70T633/1S

___

10 µA

+30 µA

10 µA

0.4 V

___

0.4 V

___

5670 tb l 09

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

Symbol Parameter Test Condition Version Typ.

DD

Dynamic Op erating

I

Current (Both Ports Active)

(6)

I

SB1

Standby Current (Both P orts - TTL Lev e l Inputs)

(6)

I

SB2

Standby Current (One Port - TTL Lev e l Inputs)

I

SB3

Full Standby Curre nt (Both P orts - CMOS Lev e l Inputs)

(6)

I

SB4

Full Standby Curre nt (One Port - CMOS Lev e l Inputs)

I

ZZ

Sleep Mode Current (Both P orts - TTL Lev e l Inputs)

NOTES:

1. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

DD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).

3. V

X = VIL means CE0X = VIL and CE1X = VIH

4. CE

CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

X > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V

CE

"X" represents "L" for left port or "R" for right port.

SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

5. I

6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

L

and CER= VIL,

CE

Outputs Di sab led

(1)

f = f

MAX

L

= CER = V

CE

f = f

MAX

CE

"A"

Active Po rt Outputs Disabled, f = f

MAX

IH

(1)

= VIL and CE

(1)

"B"

= V

(5)

IH

Both Ports CEL and

CE

R

> VDD - 0.2V, VIN > VDD - 0.2 V

or V

IN

< 0.2V, f = 0

"A"

< 0.2V and CE

CE

VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = f

ZZ

L = ZZR = VIH

(1)

f = f

MAX

(2)

"B"

> VDD - 0.2V

MAX

(1)

COM'L S 350 475 300 405 300 355 225 305

IND S

COM'L S 115 140 90 120 75 105 60 85

IND S

COM'L S 240 315 200 265 180 230 150 200

IND S

COM'LS210210210210

IND S

(5)

COM'L S 240 315 200 265 180 230 150 200

IND S

COM'LS210210210210

IND S

(VDD = 2.5V ± 100mV)

(4)

(6)

70T633/1S10

Com 'l

(6)

& Ind

Max. Typ.

(4)

300 445 300 395

90 145 7 5 130

200 290 180 255

220220

200 290 180 255

220220

Max. Typ.

70T63 3/1S8

Com'l Only

____ ____

70T633/1S12

Com'l & Ind

(4)

Max. Typ.

70T6 33/1S15

Com 'l On ly

(4)

Max. Unit

____ ____

5670 tbl 10

UnitMin. Max.

V

mA

9

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ = 3.3V/2.5V)

Input Pulse Levels

Input Rise/Fall Times

Input Timing Re ference Leve ls

Outp ut Re ference Lev e l s

Output Load

GND to 3.0V / GND to 2.5V

2ns Max.

1.5V/1.25V

Figure 1

5670 tbl 11

∆

t

AA

/

t

ACE

(Typical, ns)

DATA

OUT

3.5

2.5

1.5

0.5

50Ω

,

1.5V/1.25

10pF (Tester)

Figure 1. AC Output Test load.

4

3

2

1

0

20

40 60

80 100

5670drw 03

120 140

160

∆

Capacitance (pF) fromAC TestLoad

Figure 3. Typical Output Derating (Lumped Capacitive Load).

5670 drw 04

10

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

(5)

Com' l Onl y

____

3

0

70T633/1S10

Com 'l

& Ind

____

10

____

8

____

8

____

4

____

4

____

3

____

3

____

0

03.5040608ns

____

0

____

0

____

7

____

4

____

5

Symbol Parameter

READ CYCLE

t

RC

AA

ACE

ABE

AOE

OH

LZ

LZOB

HZ

PU

PD

SOP

SAA

SOE

Read Cyc le Tim e 8

Address Access Time

Chip Enable Ac cess Time

Byte Enable Access Time

(3)

Outp ut E nab le Ac ce s s Time

Outp ut Ho ld from Add re s s Change 3

Output Low-Z Time Chip Enable and Semaphore

Output Low-Z Time Output Enable and Byte Enable

Output High-Z Time

Chip Enable to Po wer Up Time

(1,2)

(2)

Chip Disabl e to Po we r Do wn Tim e

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time 2 8 2 10 2 12 2 15 ns

Semaphore Output Enab le Access Time

70T633/1S8

(1,2)

(2)

(4)

(5)

70T633/1S12

Com' l & Ind

70T633/1S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max. Min. Max.

____

10

5

____

8

4

5

____

12

____

12

____

12

____

6

____

6

____

3

____

3

____

0

____

0

____

8

____

6

____

6

____

15

____

3

0

____

ns

15 ns

7ns

____

ns

____

ns

____

ns

____

ns

12 ns

8ns

7ns

5670 tbl 12

AC Electrical Characteristics Over the

Com'l Onl y

6

0

____

3

4

3.5

____

(4)

(5)

70T633/1S10

Com 'l

(5)

& Ind

10

7

0

7

0

5

0

____

3

5

70T633/1S12

Com'l & Ind

____

4

____

12

____

9

____

9

____

0

____

9

____

0

____

7

____

0

____

6

____

3

____

5

____

5

Operating Temperature and Supply Voltage

70T633/1S8

Symbol Parameter

WRI T E CYCL E

t

WC

EW

t

AW

t

AS

t

WP

WR

t

DW

DH

t

WZ

t

OW

t

SWRD

t

SPS

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE= V

CE

4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

Write Cycle Time 8

Chip Enable to End-o f-Write

(3)

Address Valid to End-of-Write 6

Address Set-up Time

(3)

Write Pulse Width 6

Write Recovery Time 0

Data Valid to End-of-Write 4

Data Ho ld Time 0

Write Enable to Output in High-Z

Outp ut Ac ti ve fro m End-o f- Write

(1,2)

SEM Flag Write to Read Time

SEM Flag Contention Window

0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when

70T633/1S15

Com'l Only

15

12

0

12

0

10

0

____

3

5

UnitMin. Max. Min. Max. Min. Max. Min. Max.

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

____

ns

8ns

____

ns

____

ns

____

ns

5670 tbl 13

11

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Read Cycles

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

CE

(6)

ACE

t

AOE

(4)

OE

(4)

t

ABE

UB, LB

R/W

t

LZOB

(1)

(4)

(3,4)

t

BDD

AOE, tACE, tAA, tABE, or tBDD.

VALID DATA

tLZ/t

DATA

OUT

BUSY

OUT

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

3. t has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last: t

5. SEM = V

6. CE = L occurs when CE

IH.

0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

OH

(2)

t

HZ

.

5670 drw 06

Timing of Power-Up Power-Down

CE

t

PU

I

CC

50% 50%

I

SB

12

t

PD

5670 drw 07

.

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

t

WC

(1,5,8)

ADDRESS

(7)

t

HZ

OE

t

AW

(2)

t

WP

t

WR

(3)

CE or SEM

UB, LB

(9)

(6)

t

AS

DATA

R/W

OUT

(7)

t

WZ

(4) (4)

t

DW

IN

(7)

t

OW

t

DH

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

t

WC

ADDRESS

t

AW

UB, LB

R/W

(9)

(6)

t

AS

(9)

t

EW

(2)

t

DW

t

WR

(3)

t

DH

CE or SEM

(1,5,8)

5670 drw10

.

IN

DATA

5670 drw11

NOTES:

1. R/W or CE or UB or LB = V

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

3. t

IH during all address transitions.

EW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = V

IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 1).

8. If OE = V placed on the bus for the required t specified t

9. To access RAM, CE = V

IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

WP.

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

13

.

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

Care must be taken to still meet the Write Cycle time (t

WC), the time in

which the Address inputs must be stable. Input data setup and hold times

DW and tDH) will now be referenced to the ending address transition. In

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T651/9 is capable of performing multiple back-to-back write operations without having to pulse the R/W, CE, or BEn signals high during address transitions. This RapidWrite Mode functionality allows the system designer to achieve optimum back-to-back write cycle performance without the difficult task of generating narrow reset pulses every cycle, simplifying system design and reducing time to market.

During this new RapidWrite Mode, the end of the write cycle is now

defined by the ending address transition, instead of the R/W or CE or BEn transition to the inactive state. R/W, CE, and BEn can be held active throughout the address transition between write cycles.

(t this RapidWrite Mode the I/O will remain in the Input mode for the duration of the operations due to R/W being held low. All standard Write Cycle specifications must be adhered to. However, tAS and tWR are only applicable when switching between read and write operations. Also, there are two additional conditions on the Address Inputs that must also be met to ensure correct address controlled writes. These specifications, the Allowable Address Skew (t

AAS) and the Address Rise/Fall time (tARF),

must be met to use the RapidWrite Mode. If these conditions are not met there is the potential for inadvertent write operations at random intermediate locations as the device transitions between the desired write addresses.

Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle

t

WC

(4)

t

WC

ADDRESS

t

WC

(1,3)

(2)

t

EW

CE or SEM

(6)

BEn

t

WR

t

WP

R/W

(5)

t

WZ

DA TA

OUT

IN

DA TA

NOTES:

1. OE = V

2. A write occurs during the overlap (t

3. If the CE or SEM = V

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

6. To access RAM, CE = V

IL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.

EW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

(Figure 1).

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

t

DH

t

DW

t

DH

t

DW

t

DW

(5)

t

OW

t

DH

5670 drw08

14

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics over the Operating Temperature Range and Supply Voltage Range for RapidWrite Mode Write Cycle

Symbol Parameter Min Max Unit

t

AAS

t

ARF

NOTE:

1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.

Allowable Address Skew for RapidWrite Mode

Address Rise/Fall Time for RapidWrite Mode 1.5

____

1ns

____

(1)

V/ns

5670 tbl 14

Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle

A

0

t

ARF

t

ARF

A

18

t

AAS

(1)

NOTE:

17 for IDT70T631.

1. A

5670 drw 09

15

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side

t

SAA

A0-A

SEM

R/W

2

(1)

I/O

VALID ADDRESS

t

AW

t

EW

DATA VALID

t

AS

WP

t

WR

DW

IN

t

DH

t

SWRD

VALID ADDRESS

t

ACE

t

SOP

t

SOE

DATA

VALID

t

OUT

OH

(2)

(1)

OE

Write Cycle

NOTES:

0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for

1. CE appropriate UB/LB controls.

2. "DATA

OUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention

A

(2)

SIDE "A"

(2)

SIDE

"B"

0"A"-A2"A"

R/W

SEM

A

0"B"-A2"B"

R/W

"A"

"B"

MATCH

t

SPS

MATCH

t

SOP

ReadCycle

5670 drw 12

(1,3,4)

.

SEM

"B"

NOTES:

OR = DOL = VIL, CE0L = CE0R = VIH; CE1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.

1. D

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W

SPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

4. If t

"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

5670 drw 13

.

16

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

(6)

70T633/1S8

Com'l Only

70T633/1S10

Com 'l

(6)

& Ind

Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max.

IH

BUSY TIMING (M/ S=V

BAA

t

BDA

t

BAC

t

BDC

APS

t

BDD

t

WH

BUSY TIMING (M/ S=V

WB

t

WH

)

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time

BUSY Disable to Valid Data

Write Hold After BUSY

IL

)

BUSY Input to Write

(4)

Write Hold After BUSY

(2)

(3)

(5)

____

2.5

____

8

____

8

____

8

____

8

____

8

____

6

____

0

____

6

2.5

____

7

____

0

____

7

PORT-TO-PORT DELAY TIMING

t

WDD

DDD

Write Pulse to Data Delay

(1)

Write Data Valid to Re ad Data De lay

(1)

____

12

____

12

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

70T633/1S12

Com'l

70T633/1S15

Com'l Only

& In d

____

10

____

10

____

10

____

10

2.5

____

10

9

0

9

____

14

____

14

____

12

16

____

2.5

____

12

____

15 ns

____

15 ns

____

0

____

20 ns

5670 tbl 15

IH)".

Uni t

ns

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

70T633/ 1S8

Com'l Only

Symbol Parameter

IH

SLEEP MODE TIMING (ZZx=V

ZZS

t

ZZR

t

ZZPD

t

ZZPU

Sleep Mode Set Time 8

Sleep Mode Reset Time 8

Sleep Mode Power Down Time

Sleep Mode Power Up Time

)

(5)

Min. Max. Min. Max. Min. Max. Min. Max.

8

____

NOTES:

1. Timing is the same for both ports.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected

during sleep mode. It is recommended that boundary scan not be operated during sleep mode.

3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

5. This parameter is guaranteed by device characterization, but is not production tested.

17

(4)

____

0

(1,2,3)

70T633/1S10

Com'l

(4)

& Ind

10

____

70T6331S 12

Com 'l

70T633/ 1S15

Com'l Only

& Ind

____

12

____

12

____

12

____

0

____

0

15

____

0

5670 tbl 15a

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)

t

WC

(2,4,5)

t

BAA

MATCH

t

WP

t

DW

MATCH

t

WDD

VALID

t

DDD

(3)

ADDR

DATA

ADDR

DATA

R/W

IN "A"

BUSY

OUT "B"

"A"

"B"

t

APS

(1)

NOTES:

1. To ensure that the earlier of the two ports wins. t

0L = CE0R = VIL; CE1L = CE1R = VIH.

2. CE

3. OE = V

4. If M/S = V

IL for the reading port.

IL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

APS is ignored for M/S = VIL (SLAVE).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

t

BDA

t

DH

t

BDD

VALID

.

5670 drw 14

Timing Waveform of Write with BUSY (M/S = VIL)

t

WP

R/W

"A"

(3)

t

WB

BUSY

"B"

R/W

"B"

NOTES:

WH must be met for both BUSY input (SLAVE) and output (MASTER).

1. t

2. BUSY is asserted on port "B" blocking R/W

WB only applies to the slave mode.

3. t

"B", until BUSY"B" goes HIGH.

(2)

18

t

WH

(1)

5670 drw 15

.

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)

(1)

ADDR

and

CE

"A"

CE

"B"

BUSY

"A" "B"

(3)

"B"

t

APS

(2)

ADDRESSES MATCH

t

BAC

t

BDC

Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing

ADDR

"A"

"B"

(M/S = VIH)

(1,3,4)

t

ADDRESS "N"

(2)

APS

MATCHING ADDRESS "N"

5670 drw 16

.

t

BAA

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2. If t

X = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.

3. CE

0X = OEX = LBX = UBX = VIL. CE1X = VIH.

4. CE

t

BDA

5670 drw 17

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

70T633/1S8

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIM ING

t

AS

t

WR

t

INS

t

INR

NOTES:

1. Timing is the same for both ports.

2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

Address Set-up Time 0

Write Recovery Time 0

Interrup t Set Time

Interrup t Re set Time

____

(3)

70T633/1S10

Com'l

& Ind

____

8

0

____

(1,2)

70T633/1S12

____

Com'l

& Ind

____

0

____

0

12

(3)

____

10

70T633/1S15

Com'l Only

0

____

15 ns

5670 tbl 16

ns

19

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

ADDR

CE

R/W

INT

"A"

(3)

"A"

"B"

INTERRUPT SET ADDRESS

(4)

t

AS

(4)

t

INS

(1)

t

WC

(2)

(5)

t

WR

t

RC

ADDR

CE

"B"

OE

INT

"B"

(3)

"B"

INTERRUPT CLEAR ADDRESS

(4)

t

AS

(4)

t

INR

(2)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

X = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.

3. CE

4. Timing depends on which enable signal (CE or R/W) is asserted last.

5. Timing depends on which enable signal (CE

or R/W) is de-asserted first.

5670 drw 18

5670 drw 19

.

Truth Table III — Interrupt Flag

Left Port Right Port

L

CE

L

OE

L

LLX7FFFFXXXX X L

X X X X X X L L 7FFFF H

XXX X L

X L L 7FFFE H

A

18L-A0L

(5)

INT

L

(3)

(2)

(1,4)

R/W

R

CE

R

OE

R

L L X 7FFFE X Se t Left INTL Flag

X X X X X Rese t Left INTL Flag

A

18R-A0R

(5)

NOTES:

1. Assumes BUSY

2. If BUSY

3. If BUSY

L and INTR must be initialized at power-up.

4. INT

18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.

5. A

L = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.

L = VIL, then no change. R = VIL, then no change.

20

INT

R

(2)

Se t Right INTR Flag

(3)

Res et Rig ht INTR Flag

FunctionR/W

5670 tb l 17

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table IV — Address BUSY Arbitration

Inputs Outputs

A0R-A

18L 18R

(4)

BUSY

(1)

L

BUSY

(1)

R

Function

Write Inhibit

(3)

CE

(5)

L

CE

A0L-A

(5)

R

X X NO MATCH H H Normal

HXMATCHHHNormal

XHMATCHH HNormal

LL MATCH (2) (2)

NOTES:

1. Pins BUSY IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t

3. Writes to the left port are internally ignored when BUSY when BUSY

4. A

5. CE

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

R outputs are driving LOW regardless of actual logic level on the pin.

18 is a NC for IDT70T631. Address comparison will be for A0 - A17.

X = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.

Truth Table V — Example of Semaphore Procurement Sequence

5670 tbl 18

input internally inhibits writes.

(1,2,3)

Functions D0 - D17 Left D0 - D17 Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Se mapho re free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Se mapho re free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1.

2. There are eight semaphore flags written to via I/O

0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

3. CE

0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.

5670 tbl 19

Functional Description

The IDT70T633/1 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70T633/1 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt

flag (INT

L) is asserted when the right port writes to memory location

7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFFF. The message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T631) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFFE and 7FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation.

21

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T633/1 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.

A

19

CE

BUSY

CE

BUSY

0

R

1

R

SLAVE Dual Port RAM

BUSY

L

SLAVE Dual Port RAM

BUSY

L

MASTER Dual Port RAM

BUSY

L

MASTER Dual Port RAM

BUSY

L

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70T633/1 Dual-Port RAMs.

CE

BUSY

CE

BUSY

0

R

1

R

5670 drw 20

Width Expansion with Busy Logic Master/Slave Arrays

When expanding an IDT70T633/1 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70T633/1 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.

Semaphores

The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and SEM, the semaphore enable. The CE0, CE1, and SEM pins control onchip power down circuitry that permits the respective port to go into standby mode when not selected.

Systems which can best use the IDT70T633/1 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the hardware

.

semaphores of the IDT70T633/1, which provide a lockout mechanism without requiring complex programming.

Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70T633/1 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then

22

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch.

The eight semaphore flags reside within the IDT70T633/1 in a separate memory space from the Dual-Port RAM array. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE0, CE1, R/W and LB/UB) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE signals need to be active. (Please refer to Truth Table II). Furthermore, the read value is latched into one side’s output register when that side's semaphore select (SEM, BEn) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side.

A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during the gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the opposite side HIGH. This condition will continue until a one is written to the same semaphore request latch. If the opposite side semaphore request latch has been written to zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first request latch. The

LPORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

WRITE

SEMAPHORE

READ

Figure 4. IDT70T633/1 Semaphore Logic

SEMAPHORE

REQUEST FLIP FLOP

Q

RPORT

0

D

WRITE

SEMAPHORE READ

5670 drw 21

opposite side flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other.

One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.

23

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

n o

i

t a

r e p

O

l a

m

r o

N

,

d

e w

o

l

l a

s e

t

i

r w r o s

d a e

r o N

e d o

M p

e e

l S

R Z Z

t

2

2 w

r

d 0

7

6

5

U P Z Z

t

Z Z

I

(1,2)

Timing Waveform of Sleep Mode

d e

w o

l

l a

s e

t

i

r w r o s

d a e

r w

e n

o N

S Z Z

t

n o

i

t a

r e p

O

l a

m

r o

N

0

E C

Z Z

S S E R D D A

D

I L A V

S S E R D D A

A T A D

D

I

L A V

A T A D

D P Z Z

t

D D

I

1 = VIH.

NOTES:

1. CE

2. All timing is same for Left and Right ports.

24

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Sleep Mode

The IDT70T633/1 is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will have the lowest possible power consumption. The sleep mode timing diagram demonstrates the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode.

For a period of time prior to sleep mode and after recovering from sleep

ZZS and tZZR), new reads or writes are not allowed. If a write or read

mode (t operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep).

During sleep mode the RAM automatically deselects itself and disconnects its internal buffer. All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle, but the RAM will not be selected and will not perform any reads or writes.

JTAG Timing Specifications

t

JCYC

t

JCL

JR

t

JCH

TCK

t

JF

Device Inputs

(1)

/

TDI/TMS

t

JStJH

Device Outputs

(2)

TDO

/

t

JRSR

TRST

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical Characteristics

Symbol Parameter Min. Max. Units

JCYC

t

JCH

t

JCL

t

JRST

t

JRSR

t

JCD

t

JDC

t

JR

JF

JS

JH

JTAG Clock Input Period 100

JTAG Clock HIGH 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data Outp ut

JTAG Data Output Hold 0

(1,2,3,4,5)

JTAG Clock Low 40

____

JTAG Reset 50

____

JTAG Setup 15

JTAG Hold 15

70T633/ 1

____

(1)

3

(1)

3

____

25 ns

____

ns

5670 tbl 2 0

t

JDC

JCD

t

x

5670 drw 23

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

5. JTAG cannot be tested in sleep mode.

25

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field Value Description

Revision Numbe r (31:28) 0x0 Rese rve d for version numbe r

IDT Device ID (27:12)

0x33B

(1)

Defines IDT part numb er 70T633

IDT JEDEC ID (11:1) 0x33 Al lows uniq ue id entific ation of d evice ve nd o r as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

NOTE:

1. Device ID for IDT70T631 is 0x33C.

Scan Register Sizes

Register Name Bit Size

Instruction (IR) 4

Bypass (BYR) 1

Ide ntificati o n (IDR) 32

Boundary Scan (BSR) Note (3)

5670 tbl 2 2

5670 tb l 21

System Interface Parameters

Instructi on Code Descri pti on

EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

register between TDI and TDO.

HIGHZ

CLAMP 0011

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

RESERVED All other codes Several combinations are reserved. Do not use codes other than those

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative.

0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to b e c ap ture d in the boundary sc an cells and shifte d serially through TDO. PRE LOAD allows data to be input serially into the boundary scan cells via the TDI.

id entifie d ab ov e .

5670 tbl 23

(1)

.

26

IDT70T633/1S Preliminary High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

XXXXX

IDT

Device

Type

NOTE:

1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank I

BC DD BF

8 10 12 15

S Standard Power

70T633 70T631

Commercial (0°Cto+70°C) Industrial (-40°Cto+85°C)

256-ball BGA (BC-256) 144-pin TQFP (DD-144) 208-ball fpBGA (BF-208)

Commercial Only Commercial & Industrial Commercial & Industrial Commercial Only

9Mbit (512K x 18) 2.5V Asynchronous Dual-Port RAM 4Mbit (256K x 18) 2.5V Asynchronous Dual-Port RAM

(1)

Speed in nanoseconds

.

5670 drw 24

Preliminary Datasheet: Definition

"PRELIMINARY' datasheets contain descriptions for products that are in early release.

Datasheet Document History:

04/25/03: Initial Datasheet 10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table

Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only Page 10 Added Capacitance Derating Drawing Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table Page 12 Added tLZOB to the Waveform of Read Cycles Drawing Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms

10/20/03: Page 15 Corrected tARF to 1.5V/ns Min.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613 Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

27

Datasheet IDT70T633-1S Datasheet (IDT)

Specifications and Main Features

Frequently Asked Questions

User Manual