Datasheet IDT7099S15G, IDT7099S15J, IDT7099S15PF, IDT7099S20G, IDT7099S20GB Datasheet (Integrated Device Technology Inc)
...
Integrated Device Technology, Inc.
HIGH-SPEED
4K x 9 SYNCHRONOUS
DUAL-PORT RAM
IDT7099S
FEATURES:
• High-speed clock-to-data output times
— Military: 20/25/30ns (max.)
— Commercial: 15/20/25ns (max.)
• Low-power operation
— IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• Architecture based on Dual-Port RAM cells
— Allows full simultaneous access from both ports
— Independent bit/byte Read and Write inputs for control
functions
• Synchronous operation
— 4ns setup to clock, 1ns hold on all control, data, and
address inputs
— Data input, address, and control registers
— Fast 15ns clock to data out
— 20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA, 68-pin PLCC, and 80-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7099 is a high-speed 4K x 9 bit synchronous DualPort RAM. The memory array is based on Dual-Port memory
cells to allow simultaneous access from both ports. Registers
on control, data, and address inputs provide low set-up and
hold times. The timing latitude provided by this approach
allow systems to be designed with very short realized cycle
times. With an input data register, this device has been
optimized for applications having unidirectional data flow or
bi-directional data flow in bursts. Changing data direction from
reading to writing normally requires one dead cycle.
These Dual-Ports typically operate on only 900mW of
power at maximum high-speed clock-to-data output times as
fast as 15ns. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
The IDT7099 is packaged in a 68-pin PGA, 68-pin PLCC,
and a 80-pin TQFP. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
REGISTER
I/O
8L
I/O
0-7L
BIT
OE
L
BYTE
OE
L
CLK
L
CLKEN
BIT R/
W
L
BYTE R/
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CE
W
L
L
REG
Write
Control
Logic
WRITE
LOGIC
SENSE
AMPS
MEMOR
MEMORY
Y
ARRAY
ARRAY
DECODER
REG
en
A0L-A
11L
DECODER
REG
en
A0R-A
11R
WRITE
LOGIC
SENSE
AMPS
REGISTER
Write
Control
Logic
REG
I/O
8R
I/O
0-7R
BIT
OE
BYTE
OE
CLK
R
CLKEN
BIT R/
W
BYTE R/
CE
R
3007 drw 01
R
R
R
R
W
R
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-3007/3
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.23 1
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
BYTE
BIT
BYTE R/
BIT R/
INDEX
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
OE
OE
L
V
CC
W
L
W
L
N/C
CE
L
GND
I/O
8L
I/O
7L
I/O
6L
R
L
L
4L
2L
5L
A
98765432168 67 66 65 64 63 62 61
10
11
12
13
14
15
16
L
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
N/C
A
5L
I/O
1L
0L
3L
A
A
A
A
4L
3L
CC
V
I/O
I/O
R
CLKEN
CLK
CLK
IDT7099
J68-1
68-Pin PLCC
Top View
1L
2L
0L
GND
I/O
I/O
I/O
0R
CLKEN
A
(3)
0R
GND
I/O
1R
A
1R
I/O
2R
A
2R
I/O
3R
A
3R
I/O
4R
A
CC
V
5R
A
4R
I/O
6R
A
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
5R
I/O
A
7R
A
8R
A
9R
A
10R
A
11R
BYTE
BIT
OE
GND
GND
BYTE R/
BIT R/
N/C
CE
R
GND
I/O
8R
I/O
7R
I/O
6R
3007 drw 03
OE
W
R
R
W
R
R
51
A
A
A
BIT
OE
BYTE
R/
GND
I/O
I/O
0R
1R
A
A
NC
7L
9L
11L
L
L
W
7L
6L
50 48 46 44 42 40 38 36
A
5L
A
4L
52 49 47 45 43 41 39 37 3553 34
A
3L
A
6L
5455
A
8L
5657
A
10L
5859
BYTE
L
OE
6061
V
CC
6263
BIT
L
R/
W
6465
CE
L
6667
I/O
8L
168
3
V
CC
NC
2
4
I/O5LI/O
INDEX
ABCDEFGHJKL
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. This text does not indicate orientation of the actual
part-marking.
A
A
2L
A
0L
CLK
L
CLKEN
A
1L
CLKEN
L
CLKRA
IDT7099
G68-1
68-Pin PGA
Top View
5
7
9
111213141516181719
I/O
3L
I/O
1L
GND
6
8
10
4L
I/O
2L
I/O
0L
GND
A
1R
R
0R
A
2R
(3)
I/O
0R
I/O
2R
I/O
1R
I/O
3R
I/O
A
3R
A
4R
V
CC
4R
5R
A
6R
32 33
A
9R
30 31
A
11R
28 29
BIT
R
OE
26 27
GND GND
24 25
BIT
R
R/
W
22 23
CE
R
20 21
I/O
8R
I/O
6R
I/O
5R
A
7R
A
8R
A
10R
BYTE
R
OE
BYTE
R
R/
W
NC
GND
I/O
7R
3007 drw 02
6.23 2
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
(1,2)
Reference
1L
3L
BYTE
BIT
BYTE R/
BIT R/
N/C
A
A
A
A
A
10L
A
11L
N/C
OE
OE
V
W
W
N/C
CE
GND
I/O
I/O
I/O
N/C
5L
4L
A
A
N/C
N/C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
6L
2
7L
3
8L
4
9L
5
6
7
8
L
9
L
10
CC
11
L
12
L
13
14
L
15
16
8L
17
7L
18
6L
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4L
5L
CC
V
N/C
N/C
I/O
I/O
0L
2L
A
A
A
A
IDT7099
PN80-1
80-Pin TQFP
Top View
3L
2L
1L
I/O
I/O
I/O
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. This text does not indicate the orientaion of the actual part-marking.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
(3)
V
TERM
T
Terminal Voltage –0.5 to VCC –0.5 to VCC V
A Operating 0 to +70 –55 to +125 °C
Temperature
BIAS Temperature –55 to +125 –65 to +135 °C
T
Under Bias
T
STG Storage –55 to +125 –65 to +150 °C
Temperature
I
OUT DC Output Current 50 50 mA
NOTES: 3007 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
2. V
or 10ns maximum, and is limited to
+ 0.5V.
< 20mA for the period of VTERM > Vcc
R
L
R
L
6R
4R
2R
CLKEN
CLK
0L
I/O
GND
CLK
0R
I/O
GND
0R
CLKEN
A
(3)
1R
2R
I/O
I/O
1R
A
3R
I/O
5R
3R
A
A
A
A
A
4R
CC
V
I/O
5R
I/O
N/C
N/C
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3007 drw 04
N/C
N/C
A
7R
A
8R
A
9R
A
10R
A
11R
N/C
BYTE
BIT
OE
GND
GND
BYTE R/
BIT R/
N/C
CE
R
GND
I/O
8R
I/O
7R
I/O
6R
N/C
OE
W
R
R
W
R
R
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
(2)
(2)
Max. Unit
V
IH Input High Voltage 2.2 — 6.0
IL Input Low Voltage –0.5
V
(1)
— 0.8 V
NOTES: 3007 tbl 03
1. VIL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.5V.
2. V
CAPACITANCE
(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter Condition
CIN Input Capacitance VIN = 3dV 9 pF
COUT Output Capacitance VOUT = 3dV 10 pF
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
3007 tbl 02
V
3007 tbl 04
6.23 3
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Condition Min. Max. Unit
LI| Input Leakage Current
|I
LO| Output Leakage Current
|I
V
OL Output Low Voltage IOL = 4mA — 0.4 V
V
OH Output High Voltage IOL = –4mA 2.4 — V
NOTE: 3007 tbl 05
1. Input leakages are undefined at VCC ≤ 2.0V.
(1)
VCC = 5.5V, VIN = 0V to VCC —10µA
CE
= VIH, VOUT = 0V to VCC —10µA
(VCC = 5.0V ± 10%)
IDT7099S
DC ELECTRICAL CHARACTERISTICS OVER THE
(4)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7099S15 IDT7099S20 IDT7099S25 IDT7099S30
Com'l. Only Mil Only
Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
CC Dynamic
I
Operating Outputs Open
Current (Both f = fm
Ports Active)
SB1 Standby
I
Current (Both
Ports—TTL f = fmAX
Level Inputs)
SB2 Standby
I
Current (One Active Port
Port—TTL Outputs Open, Com’l. 160 210 150 200 140 180 — —
Level Inputs) f = fm
ISB3 Full Standby Both Ports CER Mil. — — 10 20 10 20 10 20 mA
Current (Both and
Ports—CMOS V
Level Inputs) or V
ISB4 Full Standby
Current (One -0.2V
Port—CMOS V
Level Inputs) Outputs Open, f = fm
NOTES: 3007 tbl 06
1. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of the 1/tCLK, using
"AC TEST CONDITIONS" of input levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I
CE
= VIL Mil. — — 170 310 160 290 160 270 mA
(1)
AX
CE
L and Mil. — — 85 140 80 130 80 110 mA
CE
R = V
IH
(1)
CE
'A' = VIL and CE'B' = VIH
(1)
AX
CE
L ≥ VCC – 0.2V
IN ≥ VCC – 0.2V Com’l. 10 15 10 — 10 — —
IN ≤ 0.2V, f = 0
CE
'A'<0.2V and CE'B '> VCC Mil. — — 145 200 135 190 135 170 mA
(3),
VIN ≥ VCC – 0.2V or
IN ≤ 0.2V, Active Port Com’l. 155 200 145 190 135 170 — —
(2)
(1)
AX
Com’l. 180 300 170 290 160 270 — —
Com’l. 90 140 85 130 80 110 — —
(3)
Mil. — — 150 210 140 200 140 180 mA
CC DC = 150mA (Typ).
(VCC = 5V ± 10%)
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1, 2, and 3
3007 tbl 07
6.23 4
IDT7099S
1
2
3
4
5
6
7
8
20 40 10060 80 120 140 160 180 200
∆tCD
(Typical, ns)
Capacitance (pF)
3007 drw 07
-1
0
- 10pF is the I/O capacitance
of this device, and 3pF is the
AC Test Load Capacitance
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Port-to-Port Delay
NOTES:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
5V
893Ω
DATA
OUT
30pF347Ω
Figure 1. AC Output Test load. Figure 2. Output Test Load
3007 drw 05
DATA
OUT
CLZ, tCHZ, tOLZ, and tOHZ).
(For t
5V
893Ω
5pF347Ω
3007 drw 06
Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
Commercial Military
7099S15 7099S20 7099S25 7099S20 7099S25 7099S30
t
CYC Clock Cycle Time 20 — 20 — 25 — 20 — 25 — 30 — ns
t
CH Clock High Time 6 — 8 — 10 — 8 — 10 — 12 — ns
t
CL Clock Low Time 6 — 8 — 10 — 8 — 10 — 12 — ns
t
CD Clock High to Output Valid — 15 — 20 — 25 — 20 — 25 — 30 ns
t
S Registered Signal Set-up Time 4 — 5 — 6 — 5 — 6 — 7 — ns
t
H Registered Signal Hold Time 1 — 1 — 1 — 2 — 2 — 2 — ns
t
DC Data Output Hold After Clock High 3 — 3 — 3 — 3 — 3 — 3 — ns
t
CKLZ Clock High to Output Low-Z
t
CKHZ Clock High to Output High-Z
t
OE Output Enable to Output Valid — 8 — 10 — 12 — 10 — 12 — 15 ns
t
OLZ Output Enable to Output Low-Z
t
OHZ Output Disable to Output High-Z
t
SCK Clock Enable, Disable Set-up Time 4 — 5 — 6 — 5 — 6 — 7 — ns
t
HCK Clock Enable, Disable Hold Time 2 — 2 — 2 — 3 — 3 — 3 — ns
t
CWDD Write Port Clock High to Read — 30 — 35 — 45 — 35 — 45 — 55 ns
Data Delay
(1,2)
(1,2)
(1,2)
(1,2)
2— 2 — 2— 2— 2— 2 — ns
—7 — 9 —12—9 —12—15 ns
0— 0 — 0— 0— 0— 0 — ns
—7 — 9 —11—9 —11—14 ns
3007 tbl 08
6.23 5
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE
t
CYC
t
CLK
CLKEN
CE
CH
t
S
t
H
t
CL
t
SCK
t
HCK
t
SCK
BYTE R/
or BIT R/
ADDRESS
or BIT
DATA
BYTE
OUT
OE
OE
W
W
An An + 1 An + 2 An + 3
t
DC
Qn Qn + 1 Qn + 1
(1)
t
OHZ
t
CKLZ
(1)
t
CD
NOTE:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
CLK
"A"
R/W
ADDR
"A"
"A"
(4)
MATCH
MATCH
(1,2,3)
NO
t
t
OLZ
OE
(1)
t
CKHZ
(1)
3007 drw 08
DATAIN
DATA
NOTES:
1.CEL =
CLK
R/W
ADDR
OUT "B"
CE
"A"
"B"
"B"
"B"
R = VIL,
CLKEN
L =
VALID
MATCH
CLKEN
R = VIL
t
CWDD
VALID
NO
MATCH
t
CD
t
DC
2.OE = VIL for the reading port, port 'B'.
3. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
4. R/
W
'A' was active (VIL) during the previous CLK'A', when enabled the write path.
6.23 6
VALID
3007 drw 09
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1,
t
CLK
CLKEN
CE
BYTE R/
or BIT R/
ADDRESS
DATA
DATA
OUT
CYC
t
CH
t
CL
W
W
An An + 1 An + 3
IN
t
CD
t
CKLZ
(3)
Qn
t
CYC
t
CH
t
CKHZ
t
CL
(3)
CECE
CE
= VIH
CECE
t
S
An + 2
Dn + 2
(2)
t
H
Dn + 3
3007 drw 10
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 2,
t
CLK
CLKEN
CE
BYTE R/
or BIT R/
ADDRESS
DATA
DATA
OUT
CYC
t
CH
t
CL
(1)
W
W
An An + 1
IN
t
CD
t
CKLZ
(3)
Qn
t
CYC
t
CH
t
CKHZ
t
CL
(3)
= VIL
(1)
(1)
(2)
t
H
CECE
CE
CECE
t
S
An + 1 An + 2
Dn + 1 Dn + 2
3007 drw 11
NOTES:
1. During dead cycle, if CE = V
2.OE low throughout.
3. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
IL, then invalid data will be written into array. The An+1 must be rewritten on the following cycle.
6.23 7
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT7099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide very short set-up
and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock
signal. An asynchronous output enable is provided to ease
asynchronous bus interfacing.
The internal write pulse width is dependent on the low to
high transitions of the clock signal allowing the shortest
possible realized cycle times. Clock enable inputs are
provided to stall the operation of the address and data input
registers without introducing clock skew for very fast interleaved memory applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the BYTE R/W and
BIT R/W pins are low for at least one clock cycle before any
write is attempted. A High on the CE input for one clock cycle
will power down the internal circuitry to reduce static power
consumption.
The device has separate Bit Write, Byte Write, Bit Enable,
and Byte Enable pins to allow for independent control.
TRUTH TABLE I – READ/WRITE CONTROL
Inputs
Synchronous
CLK
CECE
CE
Byte R/
CECE
h h h X X High-Z High-Z Deselected, Power Down, Data I/O Disabled
h l h X X DATAIN High-Z Deselected, Power Down, Byte Data Input Enabled
h h l X X High-Z DATAIN Deselected, Power Down, Bit Data Input Enabled
h l l X X DATAIN DATAIN Deselected, Power Down, Data Input Enabled
l l h X L DATAIN DATAOUT Write Byte, Read Bit
l l h X H DATAIN High-Z Write Byte Only
l h l L X DATAOUT DATAIN Read Byte, Write Bit
l h l H X High-Z DATAIN Write Bit Only
l l l X X DATAIN DATAIN Write Byte, Write Bit
l h h L L DATAOUT DATAOUT Read Byte, Read Bit
l h h H L High-Z DATAOUT Read Bit Only
l h h L H DATAOUT High-Z Read Byte Only
l h h H H High-Z High-Z Data I/O Disabled
(3)
Asynchronous Outputs
WW
W
WW
Bit R/
WW
W
WW
Byte
OEOE
OE
OEOE
Bit
TRUTH TABLE II – CLOCK ENABLE FUNCTION TABLE
Inputs Register Inputs Register Outputs
Operating Mode CLK
Load "1"
Load "0"
Hold (do nothing)
NOTES: 3007 tbl 10
1. 'H' = High voltage level steady state, 'h' = High voltage level one set-up time prior to the low-to-high clock transition, 'L' = Low voltage level steady state
'l' = Low voltage level one set-up time prior to the Low-to-High clock transition, 'X' = Don't care, 'NC' = No change
2.
CLKEN
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are low, a write cycle is initiated
on the low-to-high transition of the CLK. Termination of a write cycle is done on the next low-to-high transistion of the CLK.
IL must be clocked in during Power-Up.
= V
(3)
X H X X NC NC
CLKENCLKEN
CLKEN
CLKENCLKEN
(1)
OEOE
OE
I/O0-7 I/O8 Mode
OEOE
3007 tbl 09
(1)
(2)
lhhHH
lllLL
hXXNCNC
ADDR DATAIN ADDR DATAOUT
6.23 8
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
Device
Type
A
Power
999
SpeedAPackage
A
Process/
Temperature
Range
BlankBCommercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class C
J
G
PF
15
20
25
30
68-pin PLCC (J68-1)
68-pin PGA (G68-1)
80-pin TQFP (PN80-1)
Commercial Only
Speed in nanoseconds
Military Only
S Standard Power
7099
36K (4K x 9-Bit) Synchronous Dual-Port RAM
3007 drw 12
6.23 9
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