Integrated Device Technology, Inc.
HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
ADVANCED
IDT707288S/L
FEATURES:
• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
• Fast asynchronous address-to-data access time: 20ns
• User-controlled input pins included for bank selects
• Independent port controls with asynchronous address &
data busses
• Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option
• Interrupt flags with programmable masking
• Dual Chip Enables allow for depth expansion without
external logic
•
UB
and LB are available for bus matching to x8 or x16
busses; also support very fast banking
• TTL-compatible, single 5V (±10%) power supply
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
FUNCTIONAL BLOCK DIAGRAM
R/
L
0L
I/O
I/O
CE
8L-15L
0L-7L
A
A
0L
13L
CONTROL
1L
L
L
L
(1)
LOGIC
I/O
CONTROL
ADDRESS
DECODE
MEMORY
(BANK 0)
MEMORY
(BANK 1)
DESCRIPTION:
The IDT707288 is a high-speed 64K x 16 (1M bit) BankSwitchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(
CE
0 and CE1) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
MUX
16Kx16
ARRAY
MUX
MUX
16Kx16
ARRAY
MUX
CONTROL
LOGIC
I/O
CONTROL
ADDRESS
DECODE
R/
CE
I/O
I/O
A
A
0R
1R
R
R
R
8R-15R
0R-7R
13R
0R
R
(1)
BA
BA
BKSEL
BKSEL
1L
BA
0L
(2)
3
(2)
0
L
L
BANK
DECODE
BANK
SELECT
A
5L
A
0L
L/L
R/
(1)
(1)
L
L
L
NOTES:
1. The first six address pins for each port serve dual functions. When
BANK
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
(1)
A
5R
(1)
A
R/
0R
R/R
R
R
R
MAILBOX
INTERRUPT
LOGIC
MBSEL
= VIH, the pins serve as memory address inputs. When
DECODE
BA
1R
0R
R
R
3592 drw 01
MBSEL
= VIL, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-3592/-
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.29
1
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
FUNCTIONALITY:
The IDT707288 is a high-speed asynchronous 64K x 16
Bank-Switchable Dual-Ported SRAM, organized in four 16K x
16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array.
There are four user-controlled Bank Select input pins , and
each of these pins is associated with a specific bank within the
memory array. Access to a specific bank is gained by placing
the associated Bank Select pin in the appropriate state: VIH
assigns the bank to the left port, and VIL assigns the bank to
the right port (See Truth Table I). Once a bank is assigned to
a particular port, the port has full access to read and write
within that bank. Each port can be assigned as many banks
within the array as needed, up to and including all four banks.
The IDT707288 provides mailboxes to allow inter-processor communications. Each port has four 16-bit mailbox
registers available to which it can write and read and which the
opposite port can read only. These mailboxes are external to
the common SRAM array, and are accessed by setting
MBSEL
associated interrupt: a port can generate an interrupt to the
opposite port by writing to the upper byte of any one of its four
16-bit mailboxes. The interrupted port can clear the interrupt
by reading the upper byte. This read will not alter the contents
of the mailbox.
masked via software. Two registers are provided to permit
interpretation of interrupts: the Interrupt Cause Register and
the Interrupt Status Register. The Interrupt Cause Register
gives the user a snapshot of what has caused the interrupt to
be generated - the specific mailbox written to. The information
= VIL while setting CE = VIH. Each mailbox has an
If desired, any source of interrupt can be independently
in this register provides post-mask signals: Interrupt sources
that have been masked will not be updated. The Interrupt
Status Register gives the user the status of all bits that could
potentially cause an interrupt regardless of whether they have
been masked. Truth Table II gives a detailed explanation of
the use of these registers.
PIN NAMES
0 - BA1
(1)
(2)
(1)
W
(1)
, CE1
(1)
0 – I/O15
(1)
(4)
(5)
(1,6)
(1)
(1)
(1)
Address Inputs
Bank Address Inputs
Mailbox Access Control Gate
Bank Select Inputs
Read/Write Enable
Output Enable
Chip Enables
I/O Byte Enables
Bidirectional Data Input/Output
Interrupt Flag (Output)
+5V Power
Ground
= VIL, the pins serve as mailbox address inputs.
(3)
3592 tbl 01
MBSEL
A0 - A13
BA
MBSEL
BKSEL
R/
OE
CE0
UB, LB
I/O
INT
VCC
GND
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the
assignment of that bank between the two ports. Refer to Table I for more
details.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins for each port serve dual functions. When
= VIH, the pins serve as bank address or memory address inputs. When
MBSEL
PIN CONFIGURATIONS
(1,2)
INDEX
A
A
A
BKSEL
UB
CE
CE
MBSEL
R/
OE
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
5L
A
A
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
6L
A
7L
2
A
8L
3
A
9L
4
10L
5
11L
6
13L
7
NC
8
0
9
LB
L
10
L
11
0L
12
1L
13
14
L
Vcc
15
W
L
16
L
17
18
19
15L
20
14L
21
13L
22
12L
23
11L
24
10L
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
9L
8L
I/O
I/O
A
Vcc
L
7
I/O
A
A1LA
6L
4L
5L
I/O
I/O
I/O
1L
0L
2L
4L
3L
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
BA0LBA
3L
I/O
12L
A
NC
TOP VIEW
2L
GND
I/O
1
L
INT
GND
BKSEL
IDT707288
PN100-1
100-PIN
TQFP
L
0L
I/O
GND
I/O1
GND
(3)
0R
I/O
R
INT
1R
I/O
2
12R
BKSEL
A
2R
3R
I/O
I/O
0RBA1R
BA
4R
I/O
5R
I/O
A1RA
Vcc
4R
2R
3R
A
A
A
A
6R
75
A
7R
74
A
8R
73
A
9R
72
A
10R
71
A
11R
70
A
13R
69
NC
68
BKSEL
LB
R
R
UB
CE
0R
CE
1R
MBSEL
GND
R/
W
R
R
OE
GND
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
3592 drw 02
3
R
7R
I/O
8R
I/O
9R
I/O
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
0R
A
6R
I/O
5R
6.29 2
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CON'T.)
81 57 54
12
11
A
A
10
BA
09
08
SEL
GND
07
INT
06
A
05
80 77 74 72 69 68 65 63 60
A
7R
8R
A
11R
SEL
83 78 76 73 70 67 64 61 5984 56
A
10R
82 79 75 71 66 62 58 50
A
6R
85
3R
89
BA
1R
93
INT
R
98
NC
1
102
A
0L
A
BK
12L
4R
1R
0R
L
A
5R
8687
A
2R
8890
A
0R
9192
A
12R
2
9495
GND
9796
BK
SEL
10099
BA
0L
BK
A
A
(1,2)
13R
9R
UB
3
LB
R
NC
R
SEL
CE
CE
R/
1R
0R
IDT707288
G108-1
108-Pin PGA
Top View
MB
R
GND
W
OE
GND
R
GND
R
I/O
15R
I/O
I/O
NC
14R
11R
I/O
I/O
55 51
52 49
48 46
I/O
44 43
I/O
39 40
(3)
I/O
35 37
I/O
NC
NC
13R
12R
6R
2R
1L
4L
I/O
I/O
I/O
VccA
I/O
I/O
I/O
10R
9R
8R
4R
1R
0L
2L
NC
53
NC
I/O
47
I/O
45
I/O
42
I/O
41
GND
38
GNDI/O
7R
5R
3R
0R
04
03
BA
A
103101
1L
105104
2L
106
A
A
1L
3L
A
4L
1
4
A
7L
8
A
10L
BK
SEL
02
01
107
A
108
A
2
A
5L
369111415182023
6L
5
8L
A
9L
A
7
A
11L
13L
NC
LB
10
UB
CE
L
0L
ABCDEFGHJKLM
I NDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
31 34
11L
12L
I/O
32
I/O7L
29 30
26 27
I/O
Vcc
12
CE
0
13
L
SEL
MB
Vcc
1L
17
GND
16
OE
L
R/
W
21
I/O
19
L
GND
L
14L
25
I/O
22
I/O
I/O
10L
13L
15L
28
NC
24
I/O
I/O
NC
5L
9L
36
3L
I/O
33
I/O
6L
I/O
8L
NCNC
3592 drw 03
6.29 3
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
ASSIGNING THE BANKS VIA THE EXTERNAL BANK
SELECTS
There are four bank select pins available on the IDT707288,
and each of these pins is associated with a specific bank within
the memory array. The pins are user-controlled inputs:
access to a specific bank is assigned to a particular port by
setting the input to the appropriate level. The process of
assigning the banks is detailed in Truth Table I. Once a bank
is assigned to a port, the owning port has full access to read
and write within that bank. The opposite port is unable to
a port to a bank which it does not control will have no effect if
written, and if read unknown values on D0-D15 will be returned.
Each port can be assigned as many banks within the array as
needed, up to and including all four banks.
The bank select pin inputs must be set at either VIH or VIL
- these inputs are not tri-statable. When changing the bank
select inputs (changing the bank assignments), the device
must be write-disabled (CE and/or R/W set to VIH).
access that bank until the user reassigns the port. Access by
TRUTH TABLE I –
MEMORY BANK ASSIGNMENT
CECE
(
CE
AND/OR R/
CECE
BKSEL0 BKSEL1 BKSEL2 BKSEL3 DIRECTION
H X X X BANK 0 LEFT
X H X X BANK 1 LEFT
X X H X BANK 2 LEFT
X X X H BANK 3 LEFT
L X X X BANK 0 RIGHT
X L X X BANK 1 RIGHT
X X L X BANK 2 RIGHT
X X X L BANK 3 RIGHT
NOTES:
1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second
16Kx16 memory spaces, Bank 2 to the third 16Kx16 memory spaces,
and Bank 3 to the fourth 16Kx16 memory spaces. 'LEFT' indicates the
bank is assigned to the left port; 'RIGHT' indicates the bank is assigned
to the right port.
2. The bank select pin inputs must be set at either VIH or VIL - these inputs
are not tri-statable. When changing the bank select inputs (changing
the bank assignments), the device must be write-disabled (CE and/or
R/W set to VIH).
3. 'H' = VIH, 'L' = VIL, 'X' = Don't Care.
WW
W
= VIH)
WW
(2,3)
BANK AND
(1)
3592 tbl 02
MAILBOX INTERRUPTS AND INTERRUPT CONTROL
REGISTERS
If the user chooses to use the mailbox interrupt function,
four mailbox locations are assigned to each port. These
mailbox locations are external to the memory array. The
mailboxes are accessed by taking
CE
High.
MBSEL
Low while holding
The mailboxes are 16 bits wide: the message is userdefined since these are addressable SRAM locations. An
interrupt is generated to the opposite port upon writing to the
upper byte of any mailbox location. A port can read the
message it has just written in order to verify it: this read will
not alter the status of the interrupt sent to the opposite port.
The interrupted port can clear the interrupt by reading the
upper byte of the applicable mailbox. This read will not alter
the contents of the mailbox. The use of mailboxes to generate
interrupts to the opposite port and the reading of mailboxes to
clear interrupts is detailed in Truth Table II.
If desired, any of the mailbox interrupts can be independently masked via software. Masking of the interrupt sources
is done in the Mask Register. The masks are individual and
independent: a port can mask any combination of interrupt
sources with no effect on the other sources. Each port can
modify only its own Mask Register. The use of this register is
detailed in Truth Table II.
Two registers are provided to permit interpretation of
interrupts: these are the Interrupt Cause Register and the
Interrupt Status Register. The Interrupt Cause Register gives
the user a snapshot of what has caused the interrupt to be
generated - a specific semaphore granted to that port or a
specific mailbox written to by the opposite port. The information in this register provides post-mask signals: interrupt
sources that have been masked will not be updated. The
Interrupt Status Register gives the user the status of all bits
that could potentially cause an interrupt regardless of whether
they have been masked. The use of the Interrupt Cause
Register and the Interrupt Status Register is detailed in Truth
Table II.
6.29 4
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE II – MAILBOX INTERRUPTS (
MB
SELR/WUB LB
L X X X L L L L L L RESERVED (7) RESERVED (7)
L X X X RESERVED (7) RESERVED (7)
L(1)(1)(1)HLLLLL XXXXXXXXXXXXXXXX MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
L(1)(1)(1)HLLLLHXXXXXXXXXXXXXXXX MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
L(1)(1)(1)HLLLHLXXXXXXXXXXXXXXXX MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
L(1)(1)(1)HLLLHHXXXXXXXXXXXXXXXX MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
H(2)(2)HLLH LLXXXXXXXXXXXXXXXX MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
H(2)(2)HLLH LHXXXXXXXXXXXXXXXX MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
H(2)(2)HLLHHLXXXXXXXXXXXXXXXX MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
H(2)(2)HLLHHHXXXXXXXXXXXXXXXX MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
L (3) (3) (3) H L H L L L (4) (4) (4) (4) (5) (5) (5) (5) (6) (6) (6) (6) X X X X MAILBOX INTERRUPT CONTROLS
L X X X RESERVED (7) RESERVED (7)
L X X X H H H H H H RESERVED (7) RESERVED (7)
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DESCRIPTION
CECE
CE
CECE
= VIH)
NOTES:
(8,9)
3592 tbl 03
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in
either 8-bit or 16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be
individually masked if desired, and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port
can read its own mailboxes to verify the data written, without affecting the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a
particular mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the
actual clearing of the interrupt is triggered by the transition of
MBSEL
from VIH to VIL.
3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The
controls for R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are
"Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 =
Mailbox 0, D1 = Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this
register must be written at the same time. This register can be read at any time to verify the mask settings. The masks are individual and
independent: any single interrupt source can be masked with no effect on the other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific
bit (D4 = Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt.
Acknowledging the interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt
source has been masked, the associated bit in this register will not update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of
whether they have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates
that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for
this table). This register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this
register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these
registers.
9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
6.29 5
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device
Type
A
Power
999
SpeedAPackage
A
Process/
Temperature
Range
Blank
PF
G
20
25
S
L
707288
Commercial (0°C to +70°C)
100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
Commercial Only
Commercial Only
Speed in nanoseconds
Standard Power
Low Power
1Mbit (4 x 16K x 16)
Bank-Switchable Dual-Ported SRAM
with External Bank Selects
3592 drw 19
6.29 6
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