Datasheet IDT7027L20G, IDT7027L20PF, IDT7027L25G, IDT7027L25GB, IDT7027L25PF Datasheet (Integrated Device Technology Inc)
...
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
Features
◆◆
◆
◆◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆◆
◆
◆◆
High-speed access
– Military: 25/35/55ns (max)
– Industrial: 25ns (max.)
– Commercial: 20/25/35/55ns (max.)
◆◆
◆
◆◆
Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆◆
◆
◆◆
Separate upper-byte and lower-byte control for bus
matching capability.
◆◆
◆
◆◆
Dual chip enables allow for depth expansion without
Functional Block Diagram
IDT7027S/L
external logic
◆◆
◆
◆◆
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆◆
◆
◆◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆
◆◆
Busy and Interrupt Flags
◆◆
◆
◆◆
On-chip port arbitration logic
◆◆
◆
◆◆
Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆
◆◆
Fully asynchronous operation from either port
◆◆
◆
◆◆
TTL-compatible, single 5V (±10%) power supply
◆◆
◆
◆◆
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
◆◆
◆
◆◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
R/
W
L
UB
L
CE
0L
CE
1L
OE
L
LB
L
8-15L
I/O
0-7L
I/O
(1,2)
BUSY
L
14L
A
A
SEM
INT
0L
L
(2)
L
Address
Decoder
A
14L
A
0L
CE
0L
CE
1L
OE
W
R/
L
L
NOTES:
1. BUSY is an input as a Slave (M/S=V
IL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
I/O
Control
32Kx16
MEMORY
ARRAY
7027
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
(2)
M/
S
1
I/O
Control
Address
Decoder
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
R
R/
UB
CE
CE
OE
LB
BUSY
A
A
SEM
INT
3199 drw 01
W
R
R
0R
1R
R
R
I/O
8-15R
I/O
0-7R
(1,2)
R
.
14R
0R
R
(2)
R
MAY 2000
DSC 3199/7
IDT7027S/L
.
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. The IDT7027 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic
Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
INDEX
9L
A
A
10L
11L
A
A
12L
A
13L
A
14L
NC
NC
NC
LB
UB
CE
0L
CE
1L
SEM
Vcc
R/
W
OE
GND
GND
15L
I/O
I/O
14L
13L
I/O
12L
I/O
I/O
11L
I/O
10L
(1,2,3)
L
L
L
7
6
8
A
A
A
100999897969594939291908988878685848382818079787776
1
2
3
4
5
6
7
8
9
L
10
L
11
12
13
L
14
15
L
16
L
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
L
L
c
8
9
c
V
O
O
/
/
I
I
L
L
L
L
2
3
5
4
A
A
A
A
L
L
L
L
4
5
6
7
O
O
O
O
/
/
/
/
I
I
I
I
Pin Configurations
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
L
L
C
0
1
N
A
A
100-Pin TQFP
L
L
2
3
O
O
/
/
I
I
L
Y
L
D
S
T
N
U
N
I
B
G
IDT7027PF
PN100-1
Top View
L
L
D
D
0
1
N
N
O
O
/
/
G
G
I
I
(4)
(5)
R
Y
R
S
R
R
T
U
/S
0
1
N
I
B
A
M
R
0
O
/
I
A
R
R
R
R
4
3
2
1
O
O
O
O
/
/
/
/
I
I
I
I
R
R
R
R
R
R
R
5
4
7
8
6
3
2
A
A
A
A
A
A
A
A
9R
75
A
10R
74
A
11R
73
A
12R
72
A
13R
71
A
14R
70
NC
69
NC
68
NC
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
c
R
R
R
R
6
5
O
O
/
/
I
I
R
c
7
8
9
V
O
O
O
/
/
/
I
I
I
3199 drw 02
C
N
LB
UB
CE
CE
SEM
GND
R/
W
OE
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
R
R
0R
1R
R
R
R
15R
14R
13R
12R
11R
10R
6.42
2
IDT7027S/L
.
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Pin Configurations
81 57 54
A
10R
12
A
11
A
10
A
09
INT
08
GND
07
BUSY
06
A
05
A
04
A
03
107
A
02
108
A
01
(1,2,3)
(con't.)
80 77 74 72 69 68 65 63 60
A
A
11R
83 78 76 73 70 67 64 61 5984 56
A
8R
7R
8687
82 79 75 71 66 62 58 50
A
5R
4R
85
8890
A
3R
1R
89
9192
R
A
0R
93
9495
BUSY
S
M/
98
9796
L
INT
L
102
10099
A
0L
2L
5L
8L
9L
1L
106
103101
A
4L
105104
1
A
6L
2
5
A
A
11L
3 6 9 111415182023
12L
A
A
A
A
A
A
14R
NC
10L
14L
NCA
13R
9R
6R
2R
3L
7L
NC
NC
A
12R
R
4
8
A
13L
7
10
NC
LB
L
UB
LB
UB
CE
R
R
NC
NC
0L
SEM
CE
CE
IDT7027G
G108-1
108-Pin P GA
Top View
12
CE
13
SEM
L
Vcc
GND
R/
OE
(4)
17
GND
16
OE
R/
GND
W
GND
R
R
I/O
(5)
21
I/O
19
GND
L
W
L
15R
14L
I/O
I/O
25
I/O
22
I/O
I/O
NC
14R
11R
10L
13L
15L
R
1R
0R
1L
L
I/O
13R
I/O
12R
55 51
NC
52 49
NC
48 46
I/O
6R
44 43
I/O
2R
39 40
I/O
1L
35 37
I/O
4L
31 34
Vcc
28
NC
24
I/O
11L
I/O
12L
I/O
10R
I/O
9R
I/O
8R
VccA
I/O4RI/O
I/O
1R
I/O
0L
2L
I/O
5L
32
I/O7L
29 30
NC
26 27
I/O
9L
NC
53
NC
I/O
47
I/O
45
42
I/O
41
GND
38
GNDI/O
36
I/O
33
I/O
I/O
NCNC
7R
5R
3R
0R
3L
6L
8L
ABCDEFGHJK LM
INDEX
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
3
3199 drw 03
Pin Names
Left Port Right Port Names
CE
0L
, CE
W
L
R/
OE
L
14L
A0L - A
I/O0L - I/O
SEM
L
UB
L
LB
L
INT
L
BUSY
L
1L
15L
CE
R/
OE
A0R - A
I/O0R - I/O
SEM
UB
LB
INT
BUSY
S
M/
CC
V
0R
, CE
W
R
R
14R
R
R
R
R
R
GND Ground
1R
15R
Chip Enables
Read /Write En able
Output Enable
Address
Dat a In p ut/ O ut p ut
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interr up t Flag
Busy Flag
Master or Slave Select
Power
3199 tbl 01
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table I Chip Enable
CE CE
CE
0
1
Mode
IL
V
L
0.2V >VCC -0.2V Port Selected (CMOS Active)
<
IH
V
XV
H
VCC -0. 2V X P o rt De s e le cte d (C MO S Inac tiv e )
>
X<
NOTES:
1. Chip Enable references are shown above with the actual CE
2. Port "A" and "B" references are located where CE is used.
3. "H" = V
IH and "L" = VIL.
IH
V
Port Se lected (TTL Active)
X Port Deselected (TTL Inactive)
IL
Port Deselected (TTL Inactive)
0.2V Port Deselected (CMOS Inactive)
0 and CE1 levels, CE is a reference only.
Truth Table II Non-Contention Read/Write Control
(1)
Inputs
CE
(2)
R/W
OE UB LB SEM
HXXXXHHigh-ZHigh-ZDeselected: Power-Down
X X X H H H High-Z High-Z Both By tes Des ele cted
LLXLHHDATAINHigh-Z Write to Upper Byte Only
L L X H L H High-Z DAT A
I/O
Outputs
8-15
I/O
0-7
IN
Wri te to Lo we r B y te O nly
Mode
3199 tbl 02
LLXLLHDATAINDAT AINWri te to Bo th By te s
LHLLHHDATA
LHLHLHHigh-ZDATA
LHLLLHDATA
OUT
OUT
High-Z Read Upper Byte Only
OUT
Re ad Lo we r By te Only
OUT
DAT A
Read Both Bytes
X X H X X X High-Z High-Z Outputs Disabled
NOTES:
0L — A14L ≠ A0R — A14R.
1. A
2. Refer to Chip Enable Truth Table.
Truth Table III Semaphore Read/Write Control
(1)
Inputs
CE
(2)
R/
W
OE U B LB SEM
HHLXXLDATA
XHLHHLDATA
H
X
↑
↑
XXXLDATAINDAT AINWrite I/O0 into Semaphore Flag
XHHLDATAINDAT AINWrite I/O0 into Semaphore Flag
LXXLXL
LXXXLL
NOTES:
1. There are eight semaphore flags written to via I/O
2. Refer to Chip Enable Truth Table.
0
and read from all the I/Os (I/O0 __I/O15). These eight semaphore flags are addressed by A0-A2.
6.42
4
Outputs
8-15
I/O
OUT
OUT
______ ______
______ ______
I/O
DAT A
DAT A
0-7
OUT
Read Data in Semaphore Flag
OUT
Read Data in Semaphore Flag
No t All o we d
No t All o we d
3199 t bl 03
Mode
3199 tbl 04
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
Symbol Rating Commercial
(2)
V
TERM
Te rminal Vol tage
with Res pe c t
to GND
T
BIAS
T emperature
Und e r B ia s
STG
T
Storage
T emperature
I
OUT
DC Output
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
2. V
maximum, and is limited to
& Industrial
-0.5 to +7.0 -0.5 to +7.0 V
-55 to + 125 -65 to + 135oC
-65 to + 150 -65 to + 150oC
50 50 mA
< 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit
V
Supply Voltage 4.5 5.0 5.5 V
CC
(1,3)
Military Unit
3199 tbl 05
Maximum Operating
Temperature and Supply Voltage
Grade
Military -55OC to+ 125OC0V 5.0V + 10%
Commercial 0
Industrial -40OC to +85OC0V 5.0V + 10%
NOTES:
1. This is the parameter T
2. Industrial temperature: for other speeds packages and powers, contact your
sales office.
Capacitance
(TA = +25°C, f = 1.0mhz) TQFP ONLY
Symbol Parameter Conditions
IN
C
Inp ut Cap a ci tanc e VIN = 3dV 9 pF
Output
OUT
C
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Capacitance V
Ambient
Temperature GND Vcc
O
C to +70OC0V5.0V + 10%
A. This is the "instant on" case temperature.
(1)
(2)
Max. Unit
OUT
= 3dV 10 pF
3199 tbl 06
3199 tbl 08
GND Ground 0 0 0 V
V
Input Hi g h Vol tag e 2.2
IH
V
Inp ut Lo w Vol tag e -0.5
IL
NOTES:
IL > -1.5V for pulse width less than 10ns.
1. V
TERM must not exceed Vcc + 10%.
2. V
____
(1)
____
(2)
6.0
0.8 V
3199 tbl 07
V
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
Symbol Parameter Test Conditions
|ILI| Input Le akag e Curre nt
LO
|I
| Outp ut Le akag e Curre nt
OL
V
V
NOTE:
1. At Vcc
Outpu t Low Voltag e IOL = 4mA
OH
Output High Voltage IOH = -4mA 2.4
< 2.0V, input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to V
IH
OUT
, V
CE
= V
= 0V to V
6.42
(VCC = 5.0V ± 10%)
CC
CC
5
7027S 7027L
___
___
___
10
10
0.4
___
2.4
UnitMin. Max. Min. Max.
___
___
___
5µA
5µA
0.4 V
___
V
3199 t bl 09
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
S
L
S
L
S
L
S
L
S
L
(1,6,7)
7027X20
Com'l Only
(2)
185
____
____
____
____
120
____
____
0.2
____
____
115
____
____
(VCC = 5.0V ± 10%)
7027X25
Com'l, Ind
& Military
Max. Typ.
325
180
285
170
____
170
____
170
404085
70
____
4040100803030100802020100
____
215
105
185
105
____
105
____
105
1551.0
0.2
____
1.0
____
0.23010
190
100
160
100
____
100
____
100
Temperature and Supply Voltage Range
Symbol Param eter Test Condition Version Typ.
Dynam ic Op e rati ng
I
CC
Current
(Both Ports Active)
I
Standby Current
SB1
(Both Po rts - TTL Lev e l
Inputs)
I
Standby Current
SB2
(On e Po rt - TTL Lev e l
Inputs)
I
Full Standb y Current
SB3
(Both Po rts - Al l CMO S
Le v e l In p uts )
I
Full Standb y Current
SB4
(On e Po rt - A ll CMOS
Le v e l In p uts )
CE
, Outputs Disabled
= V
IL
SEM
= V
IH
(3)
f = f
MAX
CE
CE
=
= V
L
R
SEM
R
f = f
MAX
CE
"A"
Active Port Outputs Disabled,
f=f
MAX
SEM
R
Bo th P o rts
CE
> VCC - 0.2V
R
V
> VCC - 0.2V o r
IN
V
< 0.2V, f = 0
IN
SEM
R
CE
"A"
CE
"B"
SEM
R
V
> VCC - 0.2V o r
IN
V
< 0.2V, Ac tiv e P o rt Outp uts
IN
Disable d , f = f
IH
SEM
=
= V
L
(3)
= VIL and
(3)
SEM
=
= V
L
CE
and
L
SEM
=
> VCC - 0.2V
L
< 0.2V a nd
> VCC - 0.2V
SEM
=
> VCC - 0.2V
L
MAX
CE
(4)
IH
= V
"B"
IH
(5)
(3)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. V
3. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
COM'L SL185
MIL &
IND
COM'L SL555590
MIL &
IND
(5)
COM'L SL120
IH
MIL &
IND
COM'L SL1.0
MIL &
IND
COM'L SL115
MIL &
IND
(2)
Max. Typ.
305
160
265
160
345
160
305
160
60
200
1709595
230
2009595
1551.0
170
1459090
200
1759090
7027X35
Com 'l &
Military
(2)
Max. Typ.
295
255
335
295
30
30
215
0.2
1.0
0.23010
85
60
185
1558585
1858585
15
5
160
1358080
190
1658080
7027X55
Com 'l &
Military
(2)
Max. Unit
150
270
150
230
150
310
150
270
20
20
165
135
195
165
1.0
0.2
1.0
0.23010
135
110
175
150
mA
8560mA
80
mA
155mA
mA
3199 tbl 1 0
6.42
6
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
dInp ut Pul s e Le v el s
Input Ri se /F all Time s
Input Timi ng R efe re nce Le v el s
Output R e fe re nc e Le v e l s
Output L o ad
GND to 3.0V
5ns Max.
1.5V
1.5V
Fig ure s 1 and 2
319 9 tb l 11
5V
893
DATA
OUT
BUSY
INT
347
Ω
30pF
Figure 1. AC Output Test Load
Ω
DATA
OUT
Ω
347
Figure 2. Output Test Load
(for t
5V
893
5pF*
LZ, tHZ, tWZ, tOW)
Ω
3199drw 04
*Including scope and jig.
AC Electrical Characteristics Over the
7027X25
____
25
25
25
13
____
____
15
____
25
____
25
(4,6)
7027X35
Com'l &
Military
35
____
____
____
____
3
3
____
0
____
15
____
____
____
____
____
____
7027X55
Com'l &
Military
____
55
____
35
35
35
20
15
35
35
____
____
____
____
____
____
55 ns
55 ns
55 ns
30 ns
____
3
____
3
25 ns
____
0
50 ns
____
15
55 ns
3199 t bl 12
Operating Temperature and Supply Voltage Ranges
7027X20
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
READ CYCLE
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
t
SOP
t
SAA
t
Read Cyc le Time 20
Address Access Time
Chip Enable Access Time
Byte Enable Acce ss Time
Output Enable Access Time
(3)
(3)
____
____
____
____
Outpu t Hol d fr om Ad d re ss Chang e 3
Output Low-Z Time
Output High-Z Time
Chip Enab le to Po wer Up Time
Chi p Dis ab l e to P o we r Down Time
Semaphore Flag Update Pulse (OE or
Semaphore Address Access Time
(1,2)
(1,2)
(2,5)
____
(2,5)
)10
SEM
____
____
3
0
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
____
____
____
____
____
20
20
20
12
12
20
20
Com'l, Ind.
& Military
25
____
____
____
____
3
3
____
0
____
12
____
ns
ns
ns
ns
ns
6.42
7
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles
(5)
t
RC
ADDR
(4)
t
AA
(4)
t
CE
(6)
ACE
t
AOE
(4)
OE
(4)
t
ABE
UB,LB
R/
W
t
OH
(2)
t
HZ
3199 drw 05
DATA
BUSY
OUT
OUT
(1)
t
LZ
VALID DATA
(3,4)
t
BDD
(4)
Timing of Power-Up Power-Down
(6)
CE
PU
CC
I
t
50% 50%
SB
I
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
3. t
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
6. Refer to Chip Enable Truth Table.
IH.
AOE, tACE, tAA or tBDD.
PD
t
3199 drw 06
.
6.42
8
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
7027X20
Com'l Only
Symbol Parameter
WRITE C YC L E
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
t
SWRD
t
SPS
t
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM CE= V
Truth Table.
4. The specification for t
and temperature, the actual t
5. 'X' in part numbers indicates power rating (S or L).
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
Write Cy cl e Tim e 20
Chip E nab le to End -o f-Write
(3)
15
Address Valid to End-of-Write 15
Address Set-up Time
(3)
0
Write Pu ls e Wid th 15
Write Recovery Time 0
Data Valid to End -o f-Wri te 15
Output High-Z Time
Data Hold Time
Write Enable to Output in High-Z
Outpu t Ac tiv e fro m End -o f-Write
Flag Write to Re ad Time
SEM
Flag Co nte ntio n Wi nd o w
SEM
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
(1,2)
(4)
(1,2)
(1, 2,4)
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
DH will always be smaller than the actual tOW.
____
0
____
0
5
5
(5,6)
____
____
____
____
____
____
____
12
____
12
____
____
____
7027X25
Com'l, Ind
& Military
25
20
20
0
20
0
15
____
0
____
0
5
5
____
____
____
____
____
____
____
____
____
____
____
7027X35
Com'l &
Military
7027X55
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
____
35
____
30
____
30
____
0
____
25
____
0
____
15
____
15
15
____
15
____
0
15
____
0
____
5
____
5
55
45
45
40
30
____
____
____
ns
____
ns
____
ns
____
0
0
____
____
____
ns
ns
ns
ns
25 ns
____
0
ns
25 ns
____
0
5
5
____
____
ns
ns
ns
3199 t bl 13
6.42
9
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
t
WC
(1,5,8)
ADDRESS
(7)
t
HZ
OE
t
AW
CEorSEM
(9,10)
R/
DATA
OUT
(9)
(6)
t
AS
(2)
t
WP
(3)
t
WR
W
(7)
t
WZ
(4) (4)
t
DW
IN
t
OW
t
DH
UBorLB
DATA
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
t
WC
ADDRESS
t
AW
CEorSEM
UBorLB
(9,10)
(9)
(6)
t
AS
t
EW
(2)
t
WR
(3)
3199drw 07
(1,5)
R/
W
DATA
t
DW
IN
t
DH
3199 drw 08
NOTES:
1. R/W or CE or UB and LB = V
2. A write occurs during the overlap (t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
3. t
IH during all address transitions.
EW or tWP) of a CE = VIL and a R/ W = VIL for memory array writing cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = V
placed on the bus for the required t
specified t
9. To access RAM, CE = V
IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
WP.
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
6.42
10
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side
OH
SAA
t
t
(1)
A0-A
SEM
I/O
R/
W
2
0
VALID ADDRESS
AW
t
EW
t
DATA
VALID
AS
t
t
WP
t
WR
t
DW
IN
DH
t
SWRD
t
VALID ADDRESS
ACE
t
SOP
t
AOE
t
DATA
VALID
OE
Read CycleWrite Cycle
NOTES:
1.
CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATA
Timing Waveform of Semaphore Write Contention
OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
0"A"-A2"A"
A
MATCH
(1,3,4)
OUT
(2)
3199 drw 09
(2)
SIDE
SIDE
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
4. If t
"A "
A
(2)
"B"
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
"A"
W
R/
"A"
SEM
0"B"-A2"B"
"B"
W
R/
"B"
SEM
MATCH
SPS
t
3199 drw 10
6.42
11
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7027X20
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
BUSY
TIMI NG (M/S=V
BAA
t
BDA
t
BAC
t
BDC
t
APS
t
BDD
t
WH
t
BUSY
WB
t
WH
t
BUSY
BUSY
BUSY
BUSY
Arbitration Priority Set-up Time
BUSY
Write Ho ld A fter
TIMI NG (M/S=V
BUSY
Write Ho ld A fter
PORT-TO -PORT DEL AY TIMI NG
WDD
t
DDD
t
Write Pu ls e to Data De lay
Wri te Da ta Vali d to Rea d Data De l ay
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
2. To ensure that the earlier of the two ports wins.
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
3. t
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
)
IH
Access Time from Address Match
Disable Time from Address Not Matched
Acce ss Time from Chip Enable Low
Acce ss Time from Chip Enable High
(2)
Disable to Valid Data
BUSY
)
IL
Inpu t to Wri te
BUSY
(3)
(5)
(4)
(5)
(1)
(1)
____
____
____
____
____
____
____
20
20
20
17
____
5
30
____
15
____
0
____
15
45
30
(6,7)
7027X25
Com'l, Ind.
& Military
____
20
____
20
____
20
____
____
5
____
30
____
17
____
0
____
17
____
50
____
35
7027X35
Com'l &
Military
____
20
____
20
____
20
____
17
____
____
____
20
____
5
35
____
25
____
0
____
25
60
45
7027X55
Com'l &
Military
____
____
____
____
5
____
25
0
25
____
____
45 ns
40 ns
40 ns
35 ns
____
40 ns
____
____
____
80 ns
65 ns
3199 t bl 14
IH)".
ns
ns
ns
ns
6.42
12
IDT7027S/L
.
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V IH)
t
WC
(2,4,5)
t
BAA
MATCH
t
WP
t
DW
VALID
MATCH
t
WDD
(3)
t
DDD
ADDR
DATA
ADDR
DATA
R/
IN "A"
BUSY
OUT "B"
"A"
"A"
W
(1)
APS
t
"B"
"B"
NOTES:
1. To ensure that the earlier of the two ports wins. t
L = CER = VIL (refer to Chip Enable Truth Table).
2. CE
3. OE = V
4. If M/S = V
IL for the reading port.
IL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
APS is ignored for M/S = VIL (slave).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
t
BDA
t
DH
t
BDD
VALID
3199 drw 11
Timing Waveform of Write with BUSY (M/S = VIL)
t
WP
"A"
R/
W
(3)
t
WB
"B"
BUSY
R/
"B"
W
NOTES:
WH must be met for both BUSY input (SLAVE) and output (MASTER).
1. t
2. BUSY is asserted on port "B" blocking R/W
WB is only for the "Slave" version.
3. t
"B", until BUSY"B" goes HIGH.
(2)
t
WH
(1)
3199 drw 12
6.42
13
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)
ADDR
and
CE
CE
BUSY
"A"
"B"
"A"
"B"
"B"
t
APS
(2)
ADDRESSES MATCH
t
BAC
t
BDC
(1,3)
3199 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing
ADDR
ADDR
BUSY
(M/S = VIH)
"A"
"B"
"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
2. If t
3. Refer to Chip Enable Truth Table.
(1)
t
APS
ADDRESS "N"
(2)
MATCHING ADDRESS "N"
t
BAA
t
BDA
3199 drw 14
AC Electrical Characteristics Over the
____
____
20
20
(1,2)
7027X35
Com'l &
Military
0
0
____
____
____
____
7027X55
Com'l &
Military
____
0
____
0
____
25
____
25
40 ns
40 ns
3199 tbl 15
Operating Temperature and Supply Voltage Range
7027X20
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
AS
t
WR
t
INS
t
INR
t
Address Set-up Time 0
Write Re co v e ry Time 0
Interru pt Se t Tim e
Interru pt Re se t Tim e
____
____
____
____
20
20
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
7027X25
Com'l, Ind
& Military
0
0
____
____
ns
ns
6.42
14
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing
ADDR
"A"
(3)
t
AS
"A"
CE
R/
"A"
W
(3)
t
INS
"B"
INT
ADDR
CE
"B"
"B"
t
AS
INTERRUPT CLEAR ADDRESS
(3)
(1,5)
t
WC
INTERRUPT SET ADDRESS
t
RC
(2)
(4)
t
WR
3199 drw 15
(2)
"B"
OE
(3)
t
INR
"B"
INT
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE
or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV Interrupt Flag
(1,4)
Left Port Right Port
W
L
CE
OE
L
A
L
14L-A0L
INT
L
LLX7FFFXXXX X L
XXX X XXLL7FFFH
XXX X L
XLL7FFEH
(3)
(2)
W
R/
R
CE
OE
R
A
R
14R-A0R
INT
R
(2)
(3)
L L X 7FFE X Set Left
X X X X X Res et L e ft
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
L = BUSYR =VIH.
L = VIL, then no change.
R = VIL, then no change.
4. Refer to Chip Enable Truth Table.
Set Right
Rese t Rig ht
INT
FunctionR/
INT
INT
R
INT
Flag
L
Flag
R
Flag
L
3199 drw 16
Flag
3199 tbl 16
6.42
15
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table V
Address Bus Arbitration
Inputs Outputs
14L
AOL-A
14R
L
CE
CE
XXNO MATCH H H Normal
HXMATCHHHNormal
XHMATCHHHNormal
LL MATCH (2) (2)
NOTES:
1. Pins BUSY
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
3. Writes to the left port are internally ignored when BUSY
ignored when BUSY
4. Refer to Chip Enable Truth Table.
AOR-A
R
L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are
R outputs are driving LOW regardless of the actual logic level on the pin.
L
BUSY
APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
Truth Table VI Example of Semaphore Procurement Sequence
Functions D0 - D15 Left D0 - D15 Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left po rt has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Write s " 1" to S em apho re 1 1 Se m apho re free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Write s " 1" to S em apho re 1 1 Se m apho re free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O
3. CE = V
IH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
(4)
(1)
(1)
Function
R
BUSY
Write
(3)
Inhibit
3199 tbl 17
L outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
(1,2,3)
3199 tbl 18
Functional Description
The IDT7027 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7027 has an automatic power down feature controlled
by CE0 and CE1. The CE0 and CE1 control the on-chip power down
circuitry that permits the respective port to go into a standby mode when
not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
6.42
(INT
L) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when CEL= OEL= VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFE and 7FFF are not used as
mail-boxes by ignoring the interrupt, but as part of the random access
memory. Refer to Truth Table IV for the interrupt operation.
16
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of busy logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/S pin. Once in slave mode the BUSY pin operates solely as a
write inhibit input pin. Normal operation can be programmed by tying the
BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7027 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
15
A
0
MASTER
DualPort RAM
BUSY
MASTER
DualPort RAM
BUSY
Figure 3. Busy and chip enable routing for both width and depth
BUSY
L
CE
BUSY
L
CE
BUSY
L
expansion with IDT7027 RAMs.
R
1
R
SLAVE
Dual Port RAM
BUSY
L
SLAVE
Dual Port RAM
BUSY
L
CE
BUSY
CE
BUSY
0
R
1
BUSY
R
R
3199 drw 17
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7027 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7027 RAM the
BUSY pin is an output if the part is used as a Master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a Slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7027 is a fast Dual-Port 32K x 16 CMOS Static RAM with an
additional 8 address locations dedicated to binary semaphore flags. These
flags allow either processor on the left or right side of the Dual-Port SRAM
to claim a privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore can be used
by one processor to inhibit the other from accessing a portion of the DualPort SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM = VIH.
Systems which can best use the IDT7027 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7027 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
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IDT7027S/L
.
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7027 in a separate
memory space from the Dual-Port SRAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
LPORT
SEMAPHORE
REQUEST FLIP FLOP
0
D
D
WRITE
SEMAPHORE
READ
SEMAPHORE
REQUEST FLIP FLOP
Q
Figure 4. IDT7027 Semaphore Logic
Q
RPORT
0
D
D
WRITE
SEMAPHORE
READ
3199drw 18
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests
arrive at the same time, the assignment will be arbitrarily made to one port
or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
6.42
18
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
IDT
Device
Type
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
A
Power
999
SpeedAPackage
A
Process/
Temperature
Range
S
L
Blank
(1)
I
B
PF
G
20
25
35
55
Commercial (0°Cto +70°C)
Industrial (-40°C to + 85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
100-pinTQFP (PN100-1)
108-pinPGA (G108-1)
Commercial Only
Commercial, Industrial & Military
Commercial & Military
Commercial & Military
StandardPower
Low Power
512K (32K x 16) Dual-Port RAM7027
Speed in
nanoseconds
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Datasheet Document History
1/15/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
5/19/99: Pages 4 and 16 Fixed typographical errors
6/3/99: Changed drawing format
Page 1 Corrected DSC number
11/10/99: Replaced IDT logo
5/22/00: Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
www.idt.com
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