Datasheet IDT7026L20G, IDT7026S35JB, IDT7026S55GB, IDT7026S55J, IDT7026S55JB Datasheet (Integrated Device Technology Inc)

HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

• True Dual-Ported memory cells which allow simulta­neous access of the same memory location

• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)

• Low-power operation
— IDT7026S

Active: 750mW (typ.)
Standby: 5mW (typ.)

— IDT7026L

Active: 750mW (typ.)
Standby: 1mW (typ.)

• Separate upper-byte and lower-byte control for
multiplexed bus compatibility

FUNCTIONAL BLOCK DIAGRAM

IDT7026S/L

• IDT7026 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device

•M/S = H for
M/S = L for

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling
between ports

• Fully asynchronous operation from either port

• TTL-compatible, single 5V (±10%) power supply

• Available in 84-pin PGA and 84-pin PLCC

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

BUSY

output flag on Master,

BUSY

input on Slave

I/O8L-I/O

I/O0L-I/O

BUSY

R/

UB

CE
OE

A

LB

A

W

15L

(1,2)
L

13L

L

L

L
L
L

I/O

14

Control

MEMORY

ARRAY

ARBITRATION

SEMAPHORE

LOGIC

7L

Address

0L

Decoder

CE

L

I/O

Control

Address
Decoder

14

CE

R

W

R

R/

UB

R

LB

R

CE

R

OE

R

I/O8R-I/O

I/O0R-I/O

BUSY

R

A

13R

A

0R

15R

7R

(1,2)

SEM

SEM

L

NOTES:

1. (MASTER):

2.

BUSY

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

BUSY

outputs are non-tri-stated push-pull.

is output; (SLAVE):

BUSY

is input.

M/

S

R

2939 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC 2939/3

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.17

1

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION:

The IDT7026 is a high-speed 16K x 16 Dual-Port Static
RAM. The IDT7026 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual­Port RAM for 32-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in

memory. An automatic power down feature controlled by

CE

permits the on-chip circuitry of each port to enter a very low
standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 750mW of power.

The IDT7026 is packaged in a ceramic 84-pin PGA, and a
84-pin PLCC. Military grade product is manufactured in com­pliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.

PIN CONFIGURATIONS

INDEX

8L

I/O
I/O

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

I/O

8R

(1,2)

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

I/O

GND

1L

I/O

0L

I/O

L

OE

CC

V

11109876543218483

12
13
14
15
16
17
18
19
20
21
22
23

IDT7026

J84-1

84-PIN PLCC
TOP VIEW

24
25
26
27
28
29
30
31
32

33 34 35 36 37 38 39 40 41 42 43 44 45

R

GND

15R

I/O

R

OE

W

R/

GND

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

L

L

W

R/

SEM

L

CE

L

UB

L

LB

13L

A

82 81 80 79 78 77 76 75

(3)

46 47 48 49 50 51 52 53

R

R

R

R

12R

UB

LB

13R

A

A

SEM

CE

12L

A

11R

A

11L

A

10R

A

9R

A

10L

A

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

8R

A

9L

A

A

8L

A

7L

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L
0L

A

L

BUSY

GND
M/

S

BUSY

R

0R

A
A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

2939 drw 02

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

6.17 2

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D)

63 61 60 58 55 54 51 48 46 45

11

I/O

7L

I/O

5L

I/O

4L

66

10

67

09

69

08

72

07

75

06

76

05

79

04

81

03

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

10L

11L

13L

15L

0R

1R

3R

5R

64

I/O

65

I/O

68

I/O

71

I/O

70

GND

77

I/O

80

I/O

83

I/O

8L

9L

12L

14L

2R

4R

7R

62

I/O

73

V

CC

74

GND

78

V

CC

6L

(1,2)

A

A

I/O

2L

I/O

0L

59 56 49 50 40

I/O

3L

I/O

1L

57 53 52

GND

IDT7026

84-PIN PGA

TOP VIEW

7

OE

L

UB

L

V

CC

G84-3

GNDGND

SEM

CE

R/

(3)

12

SEM

L

L

W

L

R

LB

47 44

A

13L

L

12L

A

10L

33 35

BUSY

32 31

GND

28 29

A

1R

11L

43

A

9L

41

A

7L

38

A

4L

A

1L

L

M/

S

A

0R

26

A

3R

23

A

6R

42

A

8L

A

6L

39

A

5L

37

A

3L

34

A

0L

36

A

2L

30

BUSY

27

A

2R

25

A

4R

R

82

02

84346915131618

01

125

I/O

6R

I/O

9R

I/O8RI/O

11R

I/O

I/O

10R

12R

I/O

I/O

13R

14R

81110

I/O

OE

ABCDEFGHJ KL

Index

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. This text does not indicate orientation of the actual part-marking.

PIN NAMES

Left Port Right Port Names

CE

L

R/

W

L R/WR Read/Write Enable

OE

L

A

0L – A13L A0R – A13R Address

I/O

0L – I/O15L I/O0R – I/O15R Data Input/Output

SEM

L

UB

L

LB

L

BUSY

L

CE

R Chip Enable

OE

R Output Enable

SEM

R Semaphore Enable

UB

R Upper Byte Select

LB

R Lower Byte Select

BUSY

R Busy Flag

M/

S

V

CC Power

Master or Slave Select

GND Ground

15R

R

2939 tbl 01

A

A

9R

11R

22 24

A

7R

19 21

A

10R

A

5R

A

8R

2939 drw 03

14 17 20

R

R/

W

LB

R

UB

CE

A

12R

R

R

A

13R

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2939 tbl 02

6.17 3

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

(1)

Inputs

CECE

CE

CECE

R/

WW

W

WW

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

H X X X X H High-Z High-Z Deselected: Power-Down
X X X H H H High-Z High-Z Both Bytes Deselected

L L X L H H DATA
L L X H L H High-Z DATA
L L X L L H DATA
L H L L H H D ATA
L H L H L H High-Z DATA
L H L L L H DATA

X X H X X X High-Z High-Z Outputs Disabled

NOTE: 2939 tbl 03

1. A0L — A13L ≠ A0R — A13R.

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

Inputs Outputs

CECE

CE

CECE

H H L X X L DATA
X H L H H L DATA
H X X X L DATA
X

L X X L X L — — Not Allowed
L X X X L L — — Not Allowed

NOTE:

1. There are eight semaphore flags written to via I/O

R/

WW

W

WW

OEOE

OE

OEOE

UBUB

UB

UBUB

LBLB

LB

LBLB

SEMSEM

SEM

SEMSEM

X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag

0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

Outputs

8-15 I/O0-7 Mode

I/O

IN High-Z Write to Upper Byte Only

IN Write to Lower Byte Only

IN DATAIN Write to Both Bytes

OUT High-Z Read Upper Byte Only

OUT Read Lower Byte Only

OUT DATAOUT Read Both Bytes

(1)

8-15 I/O0-7 Mode

I/O

OUT DATAOUT Read Data in Semaphore Flag
OUT DATAOUT Read Data in Semaphore Flag

IN DATAIN Write I/O0 into Semaphore Flag

2939 tbl 04

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

TERM

V

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 2939 tbl 05

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

2. V
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

RECOMMENDED DC OPERATING
CONDTIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — 6.0

V
V

IL Input Low Voltage –0.5

NOTES: 2939 tbl 06

1. VIL > -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz)

Symbol Parameter Conditions

IN Input Capacitance VIN = 3dv 9 pF

C

OUT Output VOUT = 3dv 10 pF

C

(1)

— 0.8 V

(2)

Capacitance

NOTES: 2939 tbl 07

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.

(2)

V

Max. Unit

6.17 4

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = –4mA 2.4 — 2.4 — V

V

NOTE: 2939 tbl 08

1. At Vcc = 2.0V, input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

(VCC = 5.0V ± 10%)

IDT7026S IDT7026L

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test Com'l. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

SB2 Standby Current

I

(One Port — TTL Active Port Outputs Open, L — — 105 200
Level Inputs) f = f

SB3 Full Standby Current Both Ports CEL and MIL. S — — 1.0 30 mA

I

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 2939 tbl 09

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S — — 170 345 mA

SEM

= V

IH L — — 170 305

(3)

MAX

CE

R = CEL = VIH MIL. S — — 25 100 mA

SEM

R =

SEM

L = VIH L——2580

(3)

MAX

CE

"A" = VIL and CE"B" = VIH

(3)

MAX

SEM

R =

SEM

L = VIH L 115 180 105 170

CE

R > VCC - 0.2V L — — 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2V and MIL. S — — 100 200 mA

CE

"B" > VCC - 0.2V

SEM

R =

V

IN > VCC - 0.2V or COM’L. S 110 185 100 170
IN < 0.2V L 110 160 100 145

V
Active Port Outputs Open,
f = f

MAX

(3)

SEM

L > VCC - 0.2V

SEM

L > VCC - 0.2V

(4)

(5)

(5)

(1)

(VCC = 5.0V ± 10%)

7026X20 7026X25

(2)

Max. Typ.

(2)

Max. Unit

COM’L. S 180 315 170 305

L 180 275 170 265

COM’L. S 30 85 25 85

L 30602560

MIL. S — — 105 230 mA

COM’L. S 115 210 105 200

L 0.2 5 0.2 5

L — — 100 175

6.17 5

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

SB2 Standby Current

I

(One Port — TTL Active Port Outputs Open, L 95 185 85 165
Level Inputs) f = f

SB3 Full Standby Current Both Ports CEL and MIL. S 1.0 30 1.0 30 mA

I

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 2939 tbl 10

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using

“AC Test Conditions” of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S 160 335 150 310 mA

SEM

= V

IH L 160 295 150 270

(3)

MAX

CE

L = CER = VIH MIL. S 20 100 13 100 mA

SEM

R =

SEM

L = VIH L 20801380

(3)

MAX

CE

"A"=VIL and CE"B"=VIH

(3)

MAX

SEM

R =

SEM

L = VIH L 95 155 85 135

CE

R > VCC - 0.2V L 0.2 10 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2V and MIL. S 90 190 80 175 mA

CE

"B" > VCC - 0.2V

SEM

R =

IN > VCC - 0.2V or COM’L. S 90 160 80 135 mA

V
V

IN < 0.2V L 90 135 80 110

SEM

L >VCC - 0.2V

SEM

L >VCC - 0.2V

(4)

(5)

(5)

COM’L. S 160 295 150 270

COM’L. S 20 85 13 85

MIL. S 95 215 85 195 mA

COM’L. S 95 185 85 165

Active Port Outputs Open,

MAX

(3)

f = f

(1)

(Con't.) (VCC = 5.0V ± 10%)

7026X35 7026X55

(2)

Max. Typ.

(2)

L 160 255 150 230

L 20601360

L 0.2 5 0.2 5

L 90 165 80 150

Max. Unit

6.17 6

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

5V

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V

DATA

OUT

BUSY

INT

893Ω

30pF347Ω

DATA

OUT

Output Load Figures 1 and 2

2939 tbl 11

2939 drw 04

Figure 1. AC Output Load Figure 2. Output Test Load

(for t
* Including scope and jig.

LZ, tHZ, tWZ, tOW)

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 20 — 25 — ns

t

AA Address Access Time — 20 — 25 ns

t

(1, 2)

(1, 2)

(3)
(3)

(2)

OE

(2)

or

SEM

)10—12—ns

ACE Chip Enable Access Time

t

ABE Byte Enable Access Time

t

AOE Output Enable Access Time — 12 — 13 ns

t

OH Output Hold from Address Change 3 — 3 — ns

t

LZ Output Low-Z Time

t

HZ Output High-Z Time

t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

t

SOP Semaphore Flag Update Pulse (

t

SAA Semaphore Address Access Time — 20 — 25 ns

t

(4)

IDT7026X20 IDT7026X25
Com'l. Only

—20—25ns
—20—25ns

3—3—ns

—12—15ns

0—0—ns

—20—25ns

5V

893Ω

5pF347Ω

2939 drw 05

IDT7026X35 IDT7026X55

Symbol Parameter Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 35 — 55 — ns

t

AA Address Access Time — 35 — 55 ns

t

ACE Chip Enable Access Time

t

ABE Byte Enable Access Time

t

AOE Output Enable Access Time — 20 — 30 ns

t

OH Output Hold from Address Change 3 — 3 — ns

t

LZ Output Low-Z Time

t

HZ Output High-Z Time

t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

t

SOP Semaphore Flag Update Pulse (

t

SAA Semaphore Address Access Time — 35 — 55 ns

t

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. "X" in part numbers indicates power rating (S or L).

IL and

SEM

(3)
(3)

(1, 2)

(1, 2)

(2)

(2)

OE

or

SEM

)15—15—ns

= VIH. To access semaphore, CE = VIH and

6.17 7

SEM

—35—55ns
—35—55ns

3—3—ns

—15—25ns

0—0—ns

—35—50ns

2939 tbl 12

= VIL.

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF READ CYCLES

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

ACE

CE

(4)

t

AOE

OE

(4)

t

ABE

UB, LB

R/

W

t

(1)

t

LZ

DATA

OUT

BUSY

OUT

(3, 4)

t

BDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE,

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

3. t

BUSY

4. Start of valid data depends on which timing becomes effective last t

5.

has no relation to valid output data.

= V

IH.

SEM

LB

, or UB.

AOE, tACE, tAA or tBDD.

VALID DATA

(4)

OH

(2)

t

HZ

2939 drw 06

TIMING OF POWER-UP POWER-DOWN

CE

t

I

CC

I

SB

PU

t

PD

50% 50%

2939 drw 07

6.17 8

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Symbol Parameter Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 20 — 25 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 15 — 20 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 15 — 20 — ns

t

WR Write Recovery Time 0 — 0 — ns

t

DW Data Valid to End-of-Write 15 — 15 — ns

t

HZ Output High-Z Time

t

DH Data Hold Time

t

WZ Write Enable to Output in High-Z

t

OW Output Active from End-of-Write

t

SWRD

t

SPS

t

SEM

Flag Write to Read Time 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — ns

(1, 2)

(4)

(3)

(3)

(1, 2)

(1, 2, 4)

(5)

IDT7026X20 IDT7026X25
Com'l. Only

15 — 20 — ns

0—0—ns

—12—15ns

0—0—ns

—12—15ns

0—0—ns

IDT7026X35 IDT7026X55

Symbol Parameter Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 35 — 55 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 30 — 45 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 25 — 40 — ns

t

WR Write Recovery Time 0 — 0 — ns

t

DW Data Valid to End-of-Write 15 — 30 — ns

t

HZ Output High-Z Time

t

DH Data Hold Time

t

WZ Write Enable to Output in High-Z

t

OW Output Active from End-of-Write

t

SWRD

t

SPS

t

NOTES: 2939 tbl 13

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. The specification for t
over voltage and temperature, the actual t

5. "X" in part numbers indicates power rating (S or L).

SEM

Flag Write to Read Time 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — ns

IL and

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

(1, 2)

(4)

SEM

(3)

(3)

(1, 2)

(1, 2, 4)

= VIH. To access semaphore, CE = VIH and

DH will always be smaller than the actual tOW.

30 — 45 — ns

0—0—ns

—15—25ns

0—0—ns

—15—25ns

0—0—ns

SEM

= VIL. Either condition must be valid for the entire tEW time.

6.17 9

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

t

WC

ADDRESS

OE

t

t

WZ

AW

(2)

t

WP

(7)

CE

UB

DATA

DATA

or

SEM

or

R/

OUT

LB

W

(9)

(9)

(6)

t

AS

(4) (4)

IN

WW

W

CONTROLLED TIMING

WW

(3)

t

WR

t

OW

t

DW

t

DH

(1,5,8)

t

HZ

(7)

2939 drw 08

CECE

UBUB

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

t

WC

CE

CECE

,

UB

UBUB

LBLB

,

LB

CONTROLLED TIMING

LBLB

ADDRESS

t

AW

CE

or

UB

or

DATA

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured

Test Load (Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t

to be placed on the bus for the required t
be as short as the specified t

9. To access RAM, CE = V

(9)

SEM

(6)

t

AS

(9)

LB

R/

W

IN

EW or tWP) of a LOW

CE

or R/W (or

SEM

LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

DW. If

OE

IL and

WP.

SEM

= VIH. To access semaphore, CE = VIH and

CE

SEM

is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

and a LOW R/W for memory array writing cycle.

or R/W) going HIGH to the end of write cycle.

t

EW

(2)

t

DW

SEM

= VIL. tEW must be met for either condition.

(3)

t

WR

t

DH

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data

(1,5)

2939 drw 09

+ 200mV from steady state with the Output

6.17 10

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

tSAA

A0-A2

SEM

VALID ADDRESS

tAW

tEW

tWR

VALID ADDRESS

tACE

tSOP

tDW

I/O0

R/

DATAIN

VALID

tAS

tWP

tDH

W

DATAOUT

tSWRD tAOE

OE

Read CycleWrite Cycle

NOTES:

1.CE = V

2. "DATA

IH or

UB

OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

and LB = VIH for the duration of the above timing (both write and read cycle).

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION

VALID

(1,3,4)

tOH

(2)

2939 drw 10

(1)

A

0"A"-A2"A"

(2)

SIDE

SIDE

NOTES:

OR = DOL = VIL, CER = CEL = VIH, or both

1. D

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/

SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

4. If t

(2)

“A”

“B”

R/

SEM

A

0"B"-A2"B"

R/

SEM

A" or

W"

W

W

"A"

"A"

"B"

"B"

UB

SEM"

& LB = VIH.

MATCH

t

SPS

MATCH

A" going HIGH to R/W"B" or

SEM"

B" going HIGH.

2939 drw 11

6.17 11

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY TIMING (M/

WB

t

WH Write Hold After

t

PORT-TO-PORT DELAY TIMING

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 20 — 20 ns

BUSY

Disable Time from Address Not Matched — 20 — 20 ns

BUSY

Access Time from Chip Enable Low — 20 — 20 ns

BUSY

Disable Time from Chip Enable High — 17 — 17 ns

(2)

BUSY

Disable to Valid Data

SS

IL)

S

= V

SS

BUSY

Input to Write

BUSY

BUSY

(3)

(5)

(4)

(5)

(1)

(1)

(6)

IDT7026X20 IDT7026X25
Com'l. Only

5—5—ns
—30—30ns
15 — 17 — ns

0—0—ns
15 — 17 — ns

—45—50ns
—30—35ns

IDT7026X35 IDT7026X55

Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY TIMING (M/

WB

t

WH Write Hold After

t

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 20 — 45 ns

BUSY

Disable Time from Address Not Matched — 20 — 40 ns

BUSY

Access Time from Chip Enable Low — 20 — 40 ns

BUSY

Disable Time from Chip Enable High — 20 — 35 ns

BUSY

Disable to Valid Data

SS

S

= VIL)

SS

BUSY

Input to Write

BUSY

(4)

BUSY

(2)

(3)

(5)

(5)

5—5—ns
—35—40ns
25 — 25 — ns

0—0—ns
25 — 25 — ns

PORT-TO-PORT DELAY TIMING

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

NOTES: 2939 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

2. To ensure that the earlier of the two ports wins.

3. t

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

(1)

(1)

—60—80ns
—45—65ns

BUSY

(M/S = VIH)".

6.17 12

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

t

WDD

BUSYBUSY

BUSY

BUSYBUSY

VALID

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

t

WC

t

BAA

BUSY

MATCH

S

= VIL (slave).

"A" = VIH and

t

WP

t

DW

MATCH

BUSY

"B" input is shown above.

ADDR

"A"

R/

W

"A"

DATA

IN "A"

(1)

t

APS

ADDR

"B"

"B"

BUSY

DATA

OUT "B"

NOTES:

1. To ensure that the earlier of the two ports wins. t

2.

CE

L = CER = VIL.

3.OE = VIL for the reading port.

4. If M/S = V

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

IL (slave),

BUSY

is an input. Then for this example

APS is ignored for M/

(M/

t

DDD

SS

S

= VIH)

SS

t

BDA

(3)

t

DH

(2,4,5)

t

BDD

VALID

2939 drw 12

TIMING WAVEFORM OF WRITE WITH BUSY (M/

R/

W

"A"

(3)

t

WB

BUSY

"B"

"B"

R/

W

NOTES:

WH must be met for both

1. t

2.

BUSY

is asserted on port "B" blocking R/

BUSY

input (SLAVE) and output (MASTER).

"B", until

W

BUSY

"B" goes High.

SS

S

= VIL)

SS

t

WP

(2)

(1)

t

WH

2939 drw 13

6.17 13

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

and

CE

CE

BUSY

"A"

"B"

"A"

"B"

"B"

t

APS

(2)

ADDRESSES MATCH

t

BAC

CECE

CE

TIMING (M/

CECE

t

BDC

SS

S

= VIH)

SS

(1)

2939 drw 15

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING

"A"

"B"

IH)

(1)

t

APS

ADDRESS "N"

(2)

MATCHING ADDRESS "N"

t

BAA

t

BDA

(M/

SS

S

= V

SS

ADDR

ADDR

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2. If t

TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE

(1,2)

2939 drw 15

Functions D0 - D15 Left D0 - D15 Right Status

No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES: 2683 tbl 16

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.

2. There are eight semaphore flags written to via I/O

0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

6.17 14

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A13L

A

CECE

CECE

CE

CE

L

CECE

XX
HX
XH
LL

NOTES: 2683 tbl 17

1. Pins
a master. Both are inputs when configured as a slave.
the IDT7026 are push pull, not open drain outputs. On slaves the
input internally inhibits writes.

2. LOW if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. HIGH if the inputs to the opposite port became
stable after the address and enable inputs of this port. If t
either
cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.

R A0R-A13R

CECE

BUSY

L and

L or

BUSY

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs when the part is configured as

BUSY

R = LOW will result.

BUSYBUSY

BUSY

BUSYBUSY

BUSY

(1)

L

R outputs are driving LOW regard-

BUSYBUSY

BUSY

BUSYBUSY

BUSY

(1)

R

L and

Function

BUSY

APS is not met,

BUSY

BUSY

L outputs are

X outputs on

R outputs

(3)

BUSY

FUNCTIONAL DESCRIPTION

The IDT7026 provides two ports with separate control,

address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7026 has an
automatic power down feature controlled by CE. The

CE

controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports

of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all

applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
pin operates solely as a write inhibit input pin. Normal opera­tion can be programmed by tying the

BUSY

pins HIGH. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.

The busy outputs on the IDT 7026 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.

BUSY

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an IDT7026 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7026 RAM the busy pin is
an output if the part is used as a master (M/S pin = H), and the
busy pin is an input if the part used as a slave (M/S pin = L) as
shown in Figure 3.

X

BUSY

Figure 3. Busy and chip enable routing for both width and depth

L

MASTER
Dual Port
RAM

BUSY

L

MASTER
Dual Port
RAM

BUSY

L

CE

BUSY

R

CE

BUSY

R

expansion with IDT7026 RAMs.

SLAVE
Dual Port
RAM

BUSY

L

SLAVE
Dual Port
RAM

BUSY

L

BUSY

BUSY

CE

CE

R

BUSY

R

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.

SEMAPHORES

The IDT7026 is an extremely fast Dual-Port 16K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the sema­phore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.

The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard

DECODER

R

2939 drw 16

6.17 15

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and

SEM

, the semaphore enable. The CE and

SEM

pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and

SEM

are both HIGH.

CE

Systems which can best use the IDT7026 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7026's hardware semaphores, which pro­vide a lockout mechanism without requiring complex pro­gramming.

Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7026 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.

An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.

The semaphore flags are active LOW. A token is re­quested by writing a zero into a semaphore latch and is
released when the same side writes a one to that latch.

The eight semaphore flags reside within the IDT7026 in a
separate memory space from the Dual-Port RAM. This

address space is accessed by placing a low input on the

SEM

pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D

0 is used. If

a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica­tions. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (

SEM

) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (

SEM

or OE)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the sema­phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.

It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema­phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW
and the other side HIGH. This condition will continue until a

6.17 16

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

L PORT

SEMAPHORE

REQUEST FLIP FLOP
D

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT7026 Semaphore Logic

Q

R PORT

D

0

D

WRITE

SEMAPHORE
READ

2939 drw 17

one is written to the same semaphore request latch. Should
the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay LOW until
its semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.

One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.

Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.

USING SEMAPHORES—SOME EXAMPLES

Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7026’s Dual-Port
RAM. Say the 16K x 16 RAM was to be divided into two 8K
x 16 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.

To take a resource, in this example the lower 8K of

Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success­fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 8K. Mean­while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore

0. At this point, the software could choose to try and gain
control of the second 8K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.

Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.

The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.

Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces­sors can access their assigned RAM segments at full speed.

Another application is in the area of complex data struc­tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads and
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.

6.17 17

IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank
B

G
J

20
25
35
55

S
L

7026

Commercial (0°C to +70°C)
Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

84-pin PGA (G84-3)
84-pin PLCC (J84-1)

Commercial Only

Speed in nanoseconds

Standard Power
Low Power

256K (16K x 16) Dual-Port
RAM

2939 drw 18

6.17 18