Datasheet IDT7015S15G, IDT7015S15J, IDT7015S15PF, IDT7015S17G, IDT7015S17J Datasheet (Integrated Device Technology Inc)
...
Integrated Device Technology, Inc.
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
IDT7015S/L
FEATURES:
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• High-speed access
— Military: 20/25/35ns (max.)
— Commercial: 12/15/17/20/25/35ns (max.)
• Low-power operation
— IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7015 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
•M/S = H for
M/S = L for
BUSY
output flag on Master
BUSY
input on Slave
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
• Interrupt and Busy Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• TTL-compatible, single 5V (±10%) power supply
• Available in ceramic 68-pin PGA, 68-pin PLCC, and an
80-pin TQFP
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static
RAMs. The IDT7015 is designed to be used as stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 18-bit-or-more word systems. Using the IDT
OE
R
CE
R
R/
W
R
I/O0L- I/O
NOTES:
1. In MASTER mode:
In SLAVE mode:
2.
BUSY
outputs and
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
BUSY
SEM
INT
8L
(1,2)
L
A
12L
A
0L
L
(2)
L
BUSY
is an output and is a push-pull driver
BUSY
is input.
INT
outputs are non-tri-stated push-pull drivers.
Address
Decoder
CE
OE
R/
W
L
L
L
13
I/O
Control
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/
S
I/O
Control
I/O0R-I/O
Address
Decoder
13
CE
R
OE
R
R/
W
R
SEM
INT
2954 drw 01
BUSY
A
12R
A
0R
R
8R
(1,2)
R
R
(2)
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2954/2
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.12 1
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
PIN CONFIGURATIONS
L
L
8L
1L
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
0R
I/O
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
0L
I/O
I/O
98765432168676665
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39
I/O
OE
W
R/
(1,2)
L
L
CE
SEM
N/C
IDT7015
(8K x 9)
J68-1
PLCC
TOP VIEW
N/C
CC
V
12L
A
(3)
A
A
64 63 62 61
40 41 42 43
A
A
A
A
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
6L
7L
8L
9L
10L
11L
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7015 is packaged in a ceramic 68-pin PGA, a 64pin PLCC and an 80-pin TQFP (Thin Quad FlatPack). Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
A
5L
4L
A
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
R
BUSY
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
R
R
R
7R
8R
OE
I/O
I/O
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. This text does not imply orientation of Part-Mark.
W
R/
SEM
R
CE
N/C
N/C
12R
GND
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
2954 drw 02
PIN NAMES
CE
R/
W
OE
A
0L – A12L A0R – A12R Address
I/O
SEM
INT
BUSY
Left Port Right Port Names
L
L R/WR Read/Write Enable
L
0L – I/O8L I/O0R – I/O8R Data Input/Output
L
L
L
CE
R Chip Enable
OE
R Output Enable
SEM
R Semaphore Enable
INT
R Interrupt Flag
BUSY
R Busy Flag
M/
S
V
CC Power
Master or Slave Select
GND Ground
2954 tbl 01
6.12 2
IDT7015S/L
2954 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
676866
13579
11 13 15
20
22
24
26
28
30
32
35
ABCDEFGH JK L
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
525449 39 37
A
5L
INT
L
N/C
SEM
L
CE
L
V
CC
OE
L
R/
W
L
I/O
0L
I/O
8L
GND GND
I/O
0R
V
CC
I/O
8R
OE
R
R/
W
R
SEM
R
CE
R
GND
BUSY
R
BUSY
L
M/
S
INT
R
N/C
GND
A
1R
N/C
N/C
INDEX
A
4LA2LA0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3LA1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O2RI/O3RI/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
IDT7015
(8K x 9)
G68-1
68-PIN PGA
TOP VIEW
(3)
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CON'T.)
L
L
L
W
CE
SEM
R/
77
NC
75
76
74
CC
V
NC
NC
70
72
73
71
IDT7015
(8K X 9)
PN-80
TQFP
TOP VIEW
31
27
26
25
30
28
29
INDEX
NC
I/O
I/O
I/O
I/O
GND
I/O
I/O
CC
V
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
L
8L
1L
0L
OE
I/O
I/O
I/O
78
79
80
1
2
2L
3
3L
4
4L
5
5L
6
7
6L
8
7L
9
10
11
12
13
14
15
16
17
18
19
20
22
21
23
24
(1,2)
12L
A
69
32
11L
10L
A
A
68
67
(3)
34
33
7L
9L
A
66
35
6L
8L
A
A
A
65
64
36
37
NC
NC
62
61
63
60
NC
59
5L
A
58
A
4L
57
A
3L
56
A
2L
55
A
1L
54
A
0L
53
INT
BUSY
GND
M/
S
BUSY
INT
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
L
L
R
R
52
51
50
49
48
47
46
45
44
43
42
41
40
38
39
R
R
W
R/
R
NC
NC
CE
SEM
NC
GND
12R
A
11R
A
R
8R
7R
OE
I/O
I/O
NOTES:
1. All Vcc must be connected to power supply.
2. All GND must be connected to ground supply.
3. This text does not imply orientation of Part-Mark.
9R
8R
10R
A
A
A
7R
A
5R
6R
NC
A
A
2954 drw 03
NC
6.12 3
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs
CECE
CE
CECE
R/
WW
W
WW
H X X H High-Z Deselected: Power-Down
L L X H DATA
L H L H DATA
X X H X High-Z Outputs Disabled
NOTE: 2954 tbl 02
1. Condition: A0L — A12L is not equal to A0R — A12R.
(1)
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
Outputs
0-8 Mode
I/O
IN Write to Memory
OUT Read Memory
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL
(1)
Inputs Outputs
CECE
CE
CECE
H H L L DATA
H
R/
WW
W
WW
u
OEOE
OE
OEOE
SEMSEM
SEM
SEMSEM
I/O
X L DATA
0-8 Mode
OUT Read Semaphore Flag Data Out (I/O0-8)
IN Write I/O0 into Semaphore Flag
L X X L — Not Allowed
NOTE: 2954 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from I/O0-8 . These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
T
A Operating 0 to +70 –55 to +125 °C
Temperature
BIAS Temperature –55 to +125 –65 to +135 °C
T
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND V
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
CC
2954 tbl 05
Under Bias
T
STG Storage –55 to +125 –65 to +150 °C
Temperature
OUT DC Output 50 50 mA
I
Current
NOTES: 2954 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
2. V
or 10ns maximum, and is limited to
+ 0.5V.
< 20mA for the period of VTERM > Vcc
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CC Supply Voltage 4.5 5.0 5.5 V
V
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.2 — 6.0
V
V
IL Input Low Voltage –0.5
NOTES: 2954 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
2. V
TERM must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(1)
— 0.8 V
(2)
V
(TA = +25°C, f = 1.0MHz) TQFP ONLY
Symbol Parameter Conditions
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Output VOUT = 3dV 10 pF
C
Capacitance
2954 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V .
(2)
Max. Unit
6.12 4
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
|I
LI| Input Leakage Current
LO| Output Leakage Current
|I
OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V
V
OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V
V
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to VCC —10—5µA
CE
= VIH, VOUT = 0V to VCC —10—5µA
(VCC = 5.0V ± 10%)
7015S 7015L
2954 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
7015X12 7015X15 7015X17
Test Com'l. Only Com'l. Only Com'l. Only
Symbol Parameter Condition Version Typ.
CC Dynamic Operating
I
Current
(Both Ports Active) f = f
I
SB1 Standby Current CER = CEL = VIH MIL. S — — — — — — mA
(Both Ports — TTL
Level Inputs) f = f
SB2 Standby Current CE"A"=VIL and CE"B" = VIH
I
(One Port — TTL Active Port Outputs Open L — — — — — —
Level Inputs) f = f
I
SB3 Full Standby Current Both Ports CEL and MIL. S — — — — — — mA
(Both Ports — All
CMOS Level Inputs) V
I
SB4 Full Standby Current CE"A"< 0.2V and MIL. S — — — — — — mA
(One Port — All
CMOS Level Inputs)
NOTES: 2954 tbl 09
1. "X" in part numbers indicates power rating (S or L).
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
2. V
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
CE
= VIL, Outputs Open MIL. S — — — — — — mA
SEM
= V
IH L— —— ———
(3)
MAX
COM’L. S 170 325 170 310 170 310
L 170 275 170 260 170 260
SEM
R =
SEM
L = VIH L— —— ———
(3)
MAX
COM’L. S 25 70 25 60 25 60
L256025 502550
(5)
MIL. S — — — — — — mA
(3)
MAX
SEM
R =
SEM
L = VIH L 105 170 105 160 109 160
CE
R > VCC - 0.2V L — — — — — —
IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15 1.0 15
V
IN < 0.2V, f = 0
SEM
R =
CE
"B" > VCC - 0.2V
R =
SEM
V
V
Active Port Outputs Open,
f = f
SEM
IN > VCC - 0.2V or COM’L. S 100 180 100 170 100 170 mA
IN < 0.2V L 100 150 100 140 100 140
(3)
MAX
(4)
SEM
L > VCC - 0.2V
L > VCC - 0.2V
(5)
COM’L. S 105 200 105 190 105 190
L 0.2 5 0.2 5 0.2 5
L— —— ———
(1)
(VCC = 5.0V ± 10%)
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
6.12 5
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Test
Symbol Parameter Condition Version Typ.
CC Dynamic Operating
I
Current
(Both Ports Active) f = f
SB1 Standby Current
I
(Both Ports — TTL
Level Inputs) f = f
I
SB2 Standby Current
(One Port — TTL Active Port Outputs Open L — — 90 180 85 160
Level Inputs) f = f
I
SB3 Full Standby Current Both Ports CEL and MIL. S — — 1.0 30 1.0 30 mA
(Both Ports — All
CMOS Level Inputs) V
I
SB4 Full Standby Current
(One Port — All
CMOS Level Inputs)
NOTES: 2954 tbl 10
1. "X" in part numbers indicates power rating (S or L).
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
2. V
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
CE
= VIL, Outputs Open MIL. S — — 155 340 150 300 mA
SEM
= V
IH L — — 155 280 150 250
(3)
MAX
COM’L. S 160 290 155 265 150 250
L 160 240 155 220 150 210
CE
L = CER = VIH MIL. S — — 16 80 13 80 mA
SEM
R =
SEM
L = VIH L— — 16651365
(3)
MAX
COM’L. S 20 60 16 60 13 60
L2050 16501350
(5)
(5)
MIL. S — — 90 215 85 190 mA
COM’L. S 95 180 90 170 85 155
L 0.2 5 0.2 5 0.2 5
L — — 85 170 80 150
CE
"A"=VIL and CE"B"=VIH
(3)
MAX
SEM
R =
SEM
L = VIH L 95 150 90 140 85 130
CE
R > VCC - 0.2V L — — 0.2 10 0.2 10
IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15 1.0 15
V
IN < 0.2V, f = 0
SEM
R =
SEM
CE
"A"< 0.2V and MIL. S — — 85 200 80 175 mA
CE
"B" > VCC - 0.2V
R =
SEM
V
V
SEM
IN > VCC - 0.2V or COM’L. S 90 155 85 145 80 135
IN < 0.2V L 90 130 85 120 80 110
(4)
L > VCC - 0.2V
L > VCC - 0.2V
Active Port Outputs Open,
(3)
f = f
MAX
(1)
(Cont'd) (VCC = 5.0V ± 10%)
7015X20 7015X25 7015X35
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
OUTPUT LOADS AND AC TEST
CONDITIONS
Input Pulse Levels GND to 3.0V
(1)
Input Rise/Fall Times
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figure 1 and 2
NOTE:
1. 3ns Max. for t
AA=12ns
5ns Max.
5V
DATA
OUT
BUSY
INT
Figure 1. AC Output Test Load
6.12 6
893Ω
30pF347Ω
2954 drw 05
DATA
5V
893Ω
OUT
5pF347Ω
Figure 2. Output Test Load
LZ, tHZ, tWZ, tOW)
(For t
Including scope and jig.
*
2954 drw 06
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7015X12 IDT7015X15 IDT7015X17
Com'l. Only Com'l. Only Com'l. Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
RC Read Cycle Time 12 — 15 — 17 — ns
t
AA Address Access Time — 12 — 15 — 17 ns
t
ACE Chip Enable Access Time
t
t
AOE Output Enable Access Time — 8 — 10 — 10 ns
t
OH Output Hold from Address Change 3 — 3 — 3 — ns
LZ Output Low-Z Time
t
t
HZ Output High-Z Time
t
PU Chip Enable to Power Up Time
PD Chip Disable to Power Down Time
t
t
SOP Semaphore Flag Update Pulse (
SAA Semaphore Address Access Time — 12 — 15 — 17 ns
t
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC Read Cycle Time 20 — 25 — 35 — ns
AA Address Access Time — 20 — 25 — 35 ns
t
ACE Chip Enable Access Time
t
AOE Output Enable Access Time — 12 — 13 — 20 ns
t
OH Output Hold from Address Change 3 — 3 — 3 — ns
t
LZ Output Low-Z Time
t
t
HZ Output High-Z Time
t
PU Chip Enable to Power Up Time
PD Chip Disable to Power Down Time
t
t
SOP Semaphore Flag Update Pulse (
t
SAA Semaphore Address Access Time — 20 — 25 — 35 ns
NOTES:
1. Transition is measured ±200mV from Low- or High-impedance voltage with the Output test load (Figure 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = V
4. "X" in part numbers indicates power rating (S or L).
IL and
SEM
(3)
(1, 2)
3 — 3 — 3 — ns
(1, 2)
(2)
0 — 0 — 0 — ns
(2)
— 12 — 15 — 17 ns
OE
or
SEM
— 12 — 15 — 17 ns
— 10 — 10 — 10 ns
) 10 — 10 — 10 — ns
IDT7015X20 IDT7015X25 IDT7015X35
(3)
(1, 2)
(1, 2)
(2)
(2)
OE
or
SEM
) 10—10—15—ns
= VIH. To access semaphore, CE = VIH and
—20—25—35ns
3—3—3—ns
—12—15—20ns
0—0—0—ns
—20—25—35ns
SEM
= VIL.
(4)
2954 tbl 11
6.12 7
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES
(5)
t
RC
ADDR
(4)
t
AA
(4)
t
CE
ACE
t
AOE
(4)
OE
R/
W
t
(1)
t
LZ
DATA
OUT
BUSY
OUT
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
4. Start of valid data depends on which timing becomes effective last t
5.
has no relation to valid output data.
= V
IH.
SEM
OE.
AOE, tACE, tAA or tBDD.
t
BDD
(3, 4)
VALID DATA
(4)
OH
(2)
t
HZ
2954 drw 07
TIMING OF POWER-UP / POWER-DOWN
CE
t
I
I
CC
SB
PU
t
PD
50% 50%
2954 drw 08
6.12 8
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
IDT7015X12 IDT7015X15 IDT7015X17
Com'l. Only Com'l. Only Com'l. Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
WC Write Cycle Time 12 — 15 — 17 — ns
t
(3)
(3)
(1, 2)
(1, 2, 4)
10 — 12 — 12 — ns
0 — 0 — 0 — ns
— 10 — 10 — 10 ns
0 — 0 — 0 — ns
— 10 — 10 — 10 ns
3 — 3 — 0 — ns
EW Chip Enable to End-of-Write
t
AW Address Valid to End-of-Write 10 — 12 — 12 — ns
t
AS Address Set-up Time
t
WP Write Pulse Width 10 — 12 — 12 — ns
t
WR Write Recovery Time 2 — 2 — 2 — ns
t
t
DW Data Valid to End-of-Write 10 — 10 — 10 — ns
t
HZ Output High-Z Time
DH Data Hold Time
t
t
WZ Write Enable to Output in High-Z
t
OW Output Active from End-of-Write
SWRD
t
t
SPS
SEM
Flag Write to Read Time 5 — 5 — 5 — ns
SEM
Flag Contention Window 5 — 5 — 5 — ns
(1, 2)
(4)
(5)
IDT7015X20 IDT7015X25 IDT7015X35
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
WC Write Cycle Time 20 — 25 — 35 — ns
t
EW Chip Enable to End-of-Write
t
AW Address Valid to End-of-Write 15 — 20 — 30 — ns
t
AS Address Set-up Time
t
WP Write Pulse Width 15 — 20 — 25 — ns
t
WR Write Recovery Time 2 — 2 — 2 — ns
t
DW Data Valid to End-of-Write 15 — 15 — 15 — ns
t
HZ Output High-Z Time
t
t
DH Data Hold Time
t
WZ Write Enable to Output in High-Z
OW Output Active from End-of-Write
t
t
SWRD
t
SPS
NOTES: 2954 tbl 12
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output test load (Figure 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = V
4. The specification for t
over voltage and temperature, the actual t
5. "X" in part numbers indicates power rating (S or L).
SEM
Flag Write to Read Time 5 — 5 — 5 — ns
SEM
Flag Contention Window 5 — 5 — 5 — ns
IL and
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
(1, 2)
(4)
SEM
(3)
(3)
(1, 2)
(1, 2, 4)
= VIH. To access semaphore, CE = VIH and
DH will always be smaller than the actual tOW.
15 — 20 — 30 — ns
0—0—0—ns
—12—15—20ns
0—0—0—ns
—12—15—20ns
3—3—3—ns
SEM
= VIL. Either condition must be valid for the entire tEW time.
6.12 9
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
t
WC
ADDRESS
OE
t
AW
SEM
R/
OUT
IN
W
(9)
(6)
t
AS
(7)
t
WZ
(4) (4)
t
WP
(2)
CECE
CE
CECE
CE
or
DATA
DATA
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
WW
W
CONTROLLED TIMING
WW
(3)
t
WR
t
OW
t
DW
t
DH
CONTROLLED TIMING
(1,5,8)
t
(1,5)
HZ
(7)
2954 drw 09
t
WC
ADDRESS
t
AW
SEM
R/
(9)
(6)
t
AS
t
EW
(2)
t
WR
(3)
W
t
DW
IN
EW or tWP) of a Low
CE
or R/W (or
SEM
Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
DW. If
= VIH. To access Semaphore, CE = VIH and
IL and
WP.
SEM
CE
and a Low R/W for memory array writing cycle.
SEM
or R/W) going High to the end of write cycle.
OE
is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
SEM
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data
= VIL. tEW must be met for either condition.
t
DH
2954 drw 10
CE
or
DATA
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (t
3. t
WR is measured from the earlier of
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested, transition is measured +/-200mV from steady state with the Output
Test load (Figure 2).
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the specified t
9. To access RAM, CE = V
6.12 10
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
t
OH
(2)
2954 drw 11
A0-A
SEM
I/O
R/
OE
NOTES:
1.CE = V
2. "DATA
t
SAA
2
VALID ADDRESS
t
AW
t
EW
t
DATA
t
WR
DW
VALID ADDRESS
t
SOP
IN
VALID
t
AS
t
WP
t
DH
W
t
SWRD
Read CycleWrite Cycle
IH for the duration of the above timing (both write and read cycle).
OUT VALID" represents all I/O's (I/O0-I/O8) equal to the semaphore value.
t
ACE
t
AOE
DATA
VALID
OUT
(1)
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION
A
0"A"-A2 "A"
(2)
SIDE "A"
(2)
SIDE
"B"
NOTES:
OR = DOL =VIH, CER = CEL =VIH.
1. D
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/
SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
4. If t
R/
SEM
A
0"B"-A2 "B"
R/
SEM
W
W
"A"
"A"
"B"
"B"
W
"A" or
MATCH
MATCH
SEM
"A" going high to R/W"B" or
t
SPS
SEM
"B" going High.
(1,3,4)
2954 drw 12
6.12 11
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7015X12 IDT7015X15 IDT7015X17
Com'l. Only Com'l. Only Com'l. Only
Symbol Parameter Min. Max. Min. Max Min Max. Unit
BUSY TIMING (M/
BAA
t
BDA
t
BAC
t
BDC
t
APS Arbitration Priority Set-up Time
t
BDD
t
WH Write Hold After
t
BUSY TIMING (M/
WB
t
t
WH Write Hold After
PORT-TO-PORT DELAY TIMING
WDD Write Pulse to Data Delay
t
t
DDD Write Data Valid to Read Data Delay
SS
S
= V
IH)
SS
BUSY
Access Time from Address Match — 12 — 15 — 17 ns
BUSY
Disable Time from Address Not Matched — 12 — 15 — 17 ns
BUSY
Access Time from Chip Enable Low — 12 — 15 — 17 ns
BUSY
Disable Time from Chip Enable High — 12 — 15 — 17 ns
BUSY
Disable to Valid Data
SS
IL)
S
= V
SS
BUSY
Input to Write
BUSY
(4)
BUSY
(2)
(3)
(5)
(5)
(1)
5 — 5 — 5 — ns
— 15 — 18 — 18 ns
11 — 13 — 13 — ns
0 — 0 — 0 — ns
11 — 13 — 13 — ns
— 25 — 30 — 30 ns
(1)
— 20 — 25 — 25 ns
IDT7015X20 IDT7015X25 IDT7015X35
(6)
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
SS
BUSY TIMING (M/
BAA
t
BDA
t
BAC
t
BDC
t
APS Arbitration Priority Set-up Time
t
t
BDD
WH Write Hold After
t
BUSY
BUSY
BUSY
BUSY
BUSY
BUSY TIMING (M/
t
WB
t
WH Write Hold After
BUSY
IH)
S
= V
SS
Access Time from Address Match — 20 — 20 — 20 ns
Disable Time from Address Not Matched — 20 — 20 — 20 ns
Access Time from Chip Enable Low — 20 — 20 — 20 ns
Disable Time from Chip Enable High — 17 — 17 — 20 ns
Disable to Valid Data
(5)
BUSY
SS
S
= V
IL)
SS
Input to Write
(4)
BUSY
(5)
(2)
(3)
5—5—5—ns
—30—30—35ns
15 — 17 — 25 — ns
0—0—0—ns
15 — 17 — 25 — ns
PORT-TO-PORT DELAY TIMING
t
WDD Write Pulse to Data Delay
t
DDD Write Data Valid to Read Data Delay
NOTES: 2940 tbl 13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and
2. To ensure that the earlier of the two ports wins.
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
3. t
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
(1)
(1)
—45—50—60ns
—30—35—45ns
BUSY
(M/S = VIH)".
6.12 12
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH
ADDR
"A"
R/
W
"A"
DATA
IN "A"
(1)
t
APS
ADDR
"B"
"B"
BUSY
DATA
OUT "B"
BUSYBUSY
BUSY (M/
BUSYBUSY
SS
S
= VIH)
SS
t
WC
MATCH
(2,4,5)
t
WP
t
DW
MATCH
t
WDD
VALID
t
DDD
t
DH
t
BDA
(3)
t
2954 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. t
2.
CE
L = CER = VIL.
APS is ignored for M/
S
=VIL.
3.OE = VIL for the reading port.
4. If M/S = V
IL (slave),
BUSY
is an input. Then for this example
BUSY
"A" = VIH and
BUSY
"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
BDD
VALID
TIMING WAVEFORM OF WRITE WITH
BUSYBUSY
BUSY
BUSYBUSY
tWP
R/
W
"A"
tWB
BUSY
"B"
R/
W
"B"
(2)
NOTES:
WH must be met for both
1. t
2.
BUSY
is asserted on port "B" blocking R/W"B", until
BUSY
input (SLAVE) and output (MASTER).
BUSY
"B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
tWH
(1)
2954 drw 14
6.12 13
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
ADDR
and
CE
CE
BUSY
"A"
"B"
"A"
"B"
"B"
t
APS
(2)
ADDRESSES MATCH
t
BAC
CECE
CE
TIMING (M/
CECE
t
BDC
SS
S
= VIH)
SS
(1)
2954 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
BUSY
IH)
"A"
"B"
"B"
(1)
t
APS
ADDRESS "N"
(2)
MATCHING ADDRESS "N"
t
BAA
t
BDA
2954 drw 16
SS
(M/
S
= V
SS
ADDR
ADDR
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
2. If t
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT7015X12 IDT7015X15 IDT7015X17
Com'l. Only Com'l. Only Com'l. Only
Symbol Parameter Min. Max. Min. Max. Min Max. Unit
INTERRUPT TIMING
t
AS Address Set-up Time 0 — 0 — 0 — ns
WR Write Recovery Time 0 — 0 — 0 — ns
t
INS Interrupt Set Time — 12 — 15 — 17 ns
t
INR Interrupt Reset Time — 12 — 15 — 17 ns
t
IDT7015X20 IDT7015X25 IDT7015X35
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
AS Address Set-up Time 0 — 0 — 0 — ns
t
WR Write Recovery Time 0 — 0 — 0 — ns
t
INS Interrupt Set Time — 20 — 20 — 25 ns
t
INR Interrupt Reset Time — 20 — 20 — 25 ns
t
NOTE: 2739 tbl 14
1. "X" in part numbers indicates power rating (S or L).
(1)
6.12 14
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING
ADDR
CE
R/
INT
ADDR
CE
"A"
t
AS
"A"
W
"A"
"B"
"B"
t
AS
"B"
INTERRUPT SET ADDRESS
(3)
(3)
t
INS
INTERRUPT CLEAR ADDRESS
(3)
(1)
t
WC
t
RC
(2)
(4)
t
WR
2954 drw 17
(2)
OE
"B"
(3)
t
INR
INT
"B"
2954 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG
Left Port Right Port
CECE
WW
CE
L
R/
W
CECE
WW
L L X 1FFF X XXXXL
X X X X X X L L 1FFF H
XXXXL
X L L 1FFE H
NOTES: 2954 tbl 15
1. Assumes
2. If
3. If
BUSY
BUSY
L = VIL, then no change.
R = VIL, then no change.
BUSY
L
L =
OEOE
OE
OEOE
BUSY
L A12L-A0L
R = VIH.
INTINT
INT
INTINT
L R/
(3)
(2)
(1)
CECE
WW
CE
W
R
CECE
WW
L L X 1FFE X Set Left
OEOE
OE
R
R A12R-A0R
OEOE
INTINT
INT
R Function
INTINT
(2)
(3)
Set Right
Reset Right
INT
XXXXXReset Left
INT
L Flag
INT
R Flag
INT
R Flag
L Flag
6.12 15
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II —
ADDRESS BUSY ARBITRATION
Inputs Outputs
0L-A12L
A
CECE
CECE
CE
CE
L
CECE
XX
HX
XH
LL
NOTES: 2954 tbl 16
1. Pins
IDT7015 are push-pull, not open drain outputs. On slaves the
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If t
simultaneously.
3. Writes to the left port are internally ignored when
internally ignored when
R A0R-A12R
CECE
BUSY
L and
NO MATCH H H Normal
MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit
BUSY
R are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
(1)
BUSYBUSY
BUSY
L
BUSYBUSY
R outputs are driving low regardless of actual logic level on the pin.
BUSYBUSY
BUSY
BUSYBUSY
(1)
R
Function
(3)
BUSY
X input internally inhibits writes.
APS is not met, either
L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
BUSY
BUSY
L or
BUSY
R = Low will result.
BUSY
L and
BUSY
X outputs on the
BUSY
R outputs can not be low
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
(1,2)
Functions D0 - D8 Left D0 - D8 Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
NOTES: 2954 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2. There are eight semaphore flags written to via I/O
0 and read from I/O0-8. These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT7015 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7015 has an
automatic power down feature controlled by CE. The
CE
controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (
CE
High). When a port is enabled, access to the entire memory
array is permitted.
memory location 1FFF and to clear the interrupt flag (
the right port must access memory location 1FFF. The
message (9 bits) at 1FFE or 1FFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not
used, address locations 1FFE and 1FFF are not used as mail
boxes but are still part of the random access memory. Refer
to Truth Table for the interrupt operation.
INT
R),
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location 1FFE where a write is defined as
the CE = R/W = V
IL per the Truth Table. The left port clears
the interrupt by an address location 1FFE access when
=
OE
R =VIL, R/
interrupt flag (
W
is a "don't care". Likewise, the right port
INT
R) is asserted when the left port writes to
INT
L) is asserted when the right port
CE
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
R
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.12 16
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY
BUSY
CE
(R)
CE
(R)
MASTER
Dual Port
RAM
BUSY
(L)
MASTER
Dual Port
RAM
BUSY
BUSY
(L)
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7015 RAMs.
(L)
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the
BUSY
pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT7015 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7015 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7015 RAM the busy pin is
an output if the part is used as a master (M/S pin = H), and the
busy pin is an input if the part used as a slave (M/S pin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
BUSY
BUSY
CE
CE
(R)
(R)
DECODER
BUSY
2954 drw 19
(R)
SLAVE
Dual Port
RAM
BUSY
(L)
SLAVE
Dual Port
RAM
BUSY
(L)
can be initiated with the R/W signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
SEMAPHORES
The IDT7015 are extremely fast Dual-Port 8Kx9 Static
RAMs with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and
SEM
Systems which can best use the IDT7015 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7015's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
SEM
, the semaphore enable. The CE and
are both high.
SEM
CE
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Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7015 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7015 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
SEM
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (
SEM
) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (
SEM
or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
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resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7015’s Dual-Port
RAM. Say the 8K x 9 RAM was to be divided into two 4K x 9
blocks which were to be dedicated at any one time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 4K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 4K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
SEMAPHORE
REQUEST FLIP FLOP
D
0
D
WRITE
SEMAPHORE
READ
SEMAPHORE
REQUEST FLIP FLOP
Q
Figure 4. IDT7015 Semaphore Logic
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R PORT
D
Q
D0
WRITE
SEMAPHORE
READ
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HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
Device
Type
A
Power
999
SpeedAPackage
A
Process/
Temperature
Range
Blank
B
PF
G
J
12
15
17
20
25
35
S
L
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
Commercial Only
Commercial Only
Commercial Only
Speed in nanoseconds
Standard Power
Low Power
72K (8K x 9) Dual-Port RAM7015
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