Datasheet IDT70121L25J, IDT70121L35J, IDT70121L45J, IDT70121L55J, IDT70121S25J Datasheet (Integrated Device Technology Inc)
...
Integrated Device Technology, Inc.
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
FEATURES:
• High-speed access
– Commercial: 25/35/45/55ns (max.)
• Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
•
BUSY
output flag on Master;
•
INT
flag for port-to-port communication
BUSY
input on Slave
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by CE, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
OE
R
CE
R
R/
W
R
I/O0L- I/O
NOTES:
1. 70121 (MASTER):
BUSY
is non-tristated push-pull
output.
70125 (SLAVE):
BUSY
2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
is input.
INT
is totem-pole
output.
8L
(1,2) (1,2)
BUSY
L
A
INT
10L
A
0L
(2)
L
Address
Decoder
CE
OE
R/
W
L
L
L
I/O
Control
MEMORY
ARRAY
11
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
I/O
Control
Address
Decoder
11
CE
R
OE
R
R/
W
R
2654 drw 01
I/O0R-I/O
BUSY
A
11R
A
0R
INT
R
8R
R
(2)
COMMERCIAL TEMPERATURE RANGE OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2654/4
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.10
1
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Cont'd):
Fabricated using IDT’s CMOS high-performance
technology, these devices typically operate on only 500mW of
power. Low-power (L) versions offer battery backup data
PIN CONFIGURATIONS
NDEX
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the orientation of the actual part-marking.
L
0L
10L
OE
A
A
7
6
8
9
10
11
12
13
14
15
16
17
18
19
20
5
2122232425262728293031
4L
6L
5L
I/O
I/O
I/O
(1,2)
L
L
L
L
W
BUSY
CE
INT
R/
3
2
4
1
IDT70121/125
J52-1
PLCC
TOP VIEW
8L
7L
0R
I/O
I/O
GND
I/O
CC
V
52
1R
I/O
R
R
R
R
W
10R
INT
CE
BUSY
A
R/
51
50
49
48
4733
46
OE
R
45
A
0R
44
A
1R
43
A
2R
42
A
3R
41
A
4R
40
A
5R
3R
I/O
4R
I/O
32
5R
I/O
39
38
37
36
35
34
6R
I/O
A
A
A
A
I/O
I/O
6R
7R
8R
9R
8R
7R
2654 drw 02
(3)
2R
I/O
retention capability with each port typically consuming 200µW
from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin
PLCC.
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
Grade Ambient Temperature GND VCC
Commercial 0°C to +70°C 0V 5.0V ± 10%
2654 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5 5.5 V
GND Supply Voltage 0 0 0.0 V
V
IH Input High Voltage 2.2 – 6.0
IL Input Low Voltage –0.5
V
(1)
– 0.8 V
NOTES: 2654 tbl 03
1. VIL > -1.5V for pulse width less than 10ns.
2. V
TERM must not exceed Vcc + 0.5V.
(2)
V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 V
with Respect to GND
T
A Operating 0 to +70 °C
Temperature
T
BIAS Temperature –55 to +125 °C
Under Bias
T
STG Storage –55 to +125 °C
Temperature
I
OUT DC Output 50 mA
Current
NOTES: 2654 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. V
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to
0.5V.
< 20mA for the period of VTERM > Vcc +
CAPACITANCE
Symbol Parameter Condition
C
IN Input Capacitance VIN = 3dV 9 pF
OUT Output Capacitance VOUT = 3dV 10 pF
C
NOTES:
(1)
(TA = +25°C, f = 1.0MHz)
(2)
Max. Unit
2654 tbl 13
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.10 2
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Test Condition Min. Max. Min. Max. Unit
|I
LI| Input Leakage Current
|I
LO| Output Leakage Current
VOL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V
V
OH Output High Voltage IOH = –4mA 2.4 — 2.4 — V
1. At Vcc
< 2.0V leakages are undefined.
(5)
(5)
VCC = 5.5V, VIN = 0V to VCC —10 — 5µA
VCC = 5.5V, CE = VIH —10 — 5µA
OUT = 0V to VCC
V
(VCC = 5.0V ± 10%)
70121S 70121L
70125S 70125L
2654 tbl 04NOTE:
DC ELECTRICAL CHARACTERISTICS OVER THE
(1,4)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
70121X25 70121X35 70121X45 70121X55
Test 70125X25 70125X35 70125X45 70125X55
Symbol Parameter Condition Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
I
CC Dynamic Operating
Current (Both Ports f = f
Active)
SB1 Standby Current
I
(Both Ports—TTL f = f
Level Inputs)
SB2 Standby Current
I
(One Port—TTL Active Port Outputs Open, L 80 145 80 135 80 130 80 125
Level Inputs) f = f
ISB3 Full Standby
Current (Both Ports V
CMOS Level Inputs) or V
ISB4 Full Standby
Current (One Port V
CMOS Level Inputs) V
NOTES: 2654 tbl 05
1. “X” in part numbers indicates power rating (S or L).
2. At f = f
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST
CONDITIONS” of input levels of GND to 3V.
A=+25°C for Typical values, and they are not production tested.
CE
= VIL,Outputs Open, Com’l. S 125 260 125 250 125 245 125 240 mA
(2)
MAX
CE
"A" and CE"B" = VIH, Com’l. S 30 65 30 65 30 65 30 65 mA
(2)
MAX
(3)
MAX
(2)
(5)
Com’l. S 80 175 80 165 80 160 80 155 mA
(5
)
Com’l. S 70 170 70 160 70 155 70 150 mA
CE
"A"=VIL and CE"B"=VIH
(2)
MAX
CE
"A" and CE"B" ≥ VCC – 0.2V, Com’l. S 1.0 15 1.0 15 1.0 15 1.0 15 mA
IN ≥ VCC – 0.2V L 0.2 5 0.2 5 0.2 5 0.2 5
IN ≤ 0.2V, f = 0
CE
"A"<0.2V and CE"B">VCC-0.2V
IN ≥ VCC – 0.2V or L 70 140 70 130 70 125 70 120
IN ≤ 0.2V, Active Port
Outputs Open, f = f
L 125 220 125 210 125 205 125 200
L3045304530453045
(VCC = 5V ± 10%)
6.10 3
IDT 70121/70125S/L
1250Ω
30pF775Ω
DATA
OUT
BUSY
INT
5V
5V
1250Ω
5pF775Ω
DATA
OUT
2654 drw 04
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS (L Version Only)
70121L/70125L
Symbol Parameter Test Condition Min. Typ.
V
DR VCC for Data Retention 2 — — V
I
CCDR Data Retention Current VCC = 2.0V,
(3)
CDR
t
(3)
t
R
NOTES: 2654 tbl 06
1. VCC = 2V, TA = +25°C, and are not production tested.
RC = Read Cycle Time.
2. t
3. This parameter is guaranteed by device characterization but is not production tested.
Chip Deselect to Data Retention Time VIN ≥ VCC – 0.2V or VIN ≤ 0.2V 0 — — ns
Operation Recovery Time tRC
CE
≥ VCC – 0.2V Com’l. — 100 1500 µA
(2)
(1)
Max. Unit
——ns
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
CE
V
t
CDR
IH
4.5V
≥
V
DR
2V
V
DR
4.5V
t
R
V
IH
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2
2654 tbl 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
t
RC Read Cycle Time 25 — 35 — 45 — 55 — ns
t
AA Address Access Time — 25 — 35 — 45 — 55 ns
t
ACE Chip Enable Access Time — 25 — 35 — 45 — 55 ns
t
AOE Output Enable Access Time — 12 — 25 — 30 — 35 ns
t
OH Output Hold from Address Change 0 — 0 — 0 — 0 — ns
t
LZ Output Low-Z Time
t
HZ Output High-Z Time
t
PU Chip Enable to Power-Up Time
t
PD Chip Disable to Power-Down Time
NOTES: 2654 tbl 08
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. “X” in part numbers indicates power rating (S or L).
(1,2)
(1,2)
(2)
(2)
6.10 4
(3)
70121X25 70121X35 70121X45 70121X55
70125X25 70125X35 70125X45 70125X55
0—0—0—0—ns
—10—15—20—30ns
0—0—0—0—ns
—50—50—50—50ns
2654 drw 03
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
t
RC
ADDRESS
t
AA
t
OH
DATA
BUSY
OUT
OUT
PREVIOUS DATA VALID
t
BDD
(3,4)
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
t
ACE
CE
(4)
t
AOE
OE
(1)
t
LZ
OUT
DATA
t
I
CC
CURRENT
I
SS
NOTES:
1. Timing depends on which signal is aserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. t
BDD delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY
4. Start of valid data depends on which timing becomes effective last, t
5. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low.
6. R/W = V
has no relationship to valid output data.
IH,
CE
= VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.
PU
50%
(1)
t
LZ
AOE, tACE, tAA, or tBDD.
(1,2,4)
(5,6)
t
OH
t
HZ
VALID DATA
t
PD
2654 drw 05
(2)
(2)
t
HZ
(4)
50%
2654 drw 06
6.10 5
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
WC Write Cycle Time
t
t
EW Chip Enable to End-of-Write 20 — 30 — 35 — 40 — ns
t
AW Address Valid to End-of-Write 20 — 30 — 35 — 40 — ns
t
AS Address Set-up Time 0 — 0 — 0 — 0 — ns
t
WP Write Pulse Width
t
WR Write Recovery Time 0 — 0 — 0 — 0 — ns
t
DW Data Valid to End-of-Write 12 — 20 — 20 — 20 — ns
t
HZ Output High-Z Time
t
DH Data Hold Time
t
WZ Write Enabled to Output in High-Z
t
OW Output Active from End-of-Write
NOTES: 2654 tbl 09
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, t
4. “X” in part numbers indicates power rating (S or L).
5. The specified t
and temperature. The actual t
6. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
write pulse can be as short as the specified t
DH must be met by the device supplying write date to the RAM under all operating conditions.Although tDH and tow values will vary over voltage
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
(3)
(6)
(1,2)
(5)
(1,2)
(1,2)
WC = tBAA + tWP, since R/
DH will always be smaller than the actual tOW.
DW. If
WP.
W
= VIL must occur after tBAA .
OE
is High during a R/W controlled write cycle, this requirement does not apply and the
WW
W
CONTROLLED TIMING
WW
(4)
70121X25 70121X35 70121X45 70121X55
70125X25 70125X35 70125X45 70125X55
25 — 35 — 45 — 55 — ns
20 — 30 — 35 — 40 — ns
—10—15—20—30ns
0—0—0—0—ns
—10—15—20—30ns
0—0—0—0—ns
(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
(3)
tWR
CE
(7)
tHZ
R/
DATAOUT
W
(6)
tAS
(7)
tWZ
(4) (4)
tWP
(2)
tOW
tDW tDH
DATA
IN
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (t
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
write pulse can be as short as the specified t
EW or tWP) of a
DW. If
WP.
CE
= VIL and a R/W = VIL
OE
is High during a R/W controlled write cycle, this requirement does not apply and the
WP or (tWZ + tDW) to allow the I/O drivers to turn off
2654 drw 07
6.10 6
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CECE
CE
CONTROLLED TIMING
CECE
(1,5)
tWC
ADDRESS
tAW
CE
tWR
(3)
R/
W
(6) (2)
tAS
tEW
tDW tDH
IN
DATA
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (t
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
write pulse can be as short as the specified t
EW or tWP) of a
DW. If
WP.
CE
= VIL and a R/W = VIL
OE
is High during a R/W controlled write cycle, this requirement does not apply and the
WP or (tWZ + tDW) to allow the I/O drivers to turn off
2654 drw 08
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Busy Timing (For Master IDT70121 Only)
BAA
t
t
BDA
t
BAC
t
BDC
t
WDD Write Pulse to Data Delay
t
DDD Write Data Valid to Read Data Delay
t
APS Arbitration Priority Set-up Time
t
BDD
t
WH Write Hold After
Busy Timing (For Slave IDT70125 Only)
t
WB Write to
t
WH Write Hold After
t
WDD Write Pulse to Data Delay
t
DDD Write Data Valid to Read Data Delay
NOTES: 2654 tbl 10
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. “X” in part numbers indicates power rating (S or L).
BUSY
Access Time from Address — 20 — 20 — 20 — 30 ns
BUSY
Disable Time from Address — 20 — 20 — 20 — 30 ns
BUSY
Access Time from Chip Enable — 20 — 20 — 20 — 30 ns
BUSY
Disable Time from Chip Enable — 20 — 20 — 20 — 30 ns
BUSY
Disable to Valid Data
BUSY
BUSY
Input
BUSY
(1)
(1)
(2)
(3)
(5)
(4)
(5)
(1)
(1)
(6)
70121X25 701 21X35 70121X45 70121X55
70125X25 701 25X35 70125X45 70125X55
—50—60—70—80ns
—35—45—55—65ns
5—5—5—5—ns
—30—30—35—45ns
15 — 20 — 20 — 20 — ns
0—0—0—0—ns
15 — 20 — 20 — 20 — ns
—50—60—70—80ns
—35—45—55—65ns
BUSY
“.
6.10 7
IDT 70121/70125S/L
t
APS
ADDR
'A'
DATA
IN 'A'
MATCH
t
WC
t
WP
R/
W
'A'
ADDR
'B'
DATA
OUT 'B'
MATCH
BUSY
'B'
t
BDA
t
DW
t
DH
VALID
VALID
t
DDD
(4)
t
WDD
t
BDD
2654 drw 09
(1)
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
NOTES:
1. To ensure that the earlier of the two ports wins. t
L = CER = VIL
2.
CE
3.OE = VIL for the reading port.
4.
All
timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
APS is ignored for Slave (IDT 70125).
BUSYBUSY
BUSY
BUSYBUSY
(1,2,3)
TIMING WAVEFORM OF WRITE WITH
R/
W
'A'
BUSY
'B'
W
'B'
W
'B', until
BUSY
NOTES:
1. tWH must be met for both
2.
BUSY
is asserted on port 'B' blocking R/
3. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
R/
BUSY
input (slave) and output (master).
BUSY
t
WB
'B' goes High.
BUSYBUSY
BUSYBUSY
t
WP
(2)
t
WH
(1)
2654 drw 10
6.10 8
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
(1)
2654 drw 12
(1)
t
BDC
CECE
CE
TIMING
CECE
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
ADDR
L and R
CE
R
t
APS
CE
L
t
BAC
BUSY
L
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only).
ADDRESSES MATCH
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS
OR
t
WC
ADDR
'A'
t
RC
ADDRESSES MATCH ADDRESSES DO NOT MATCH
t
APS
ADDR
'B'
t
BAA
BUSY
'B'
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
tAPS is not satisified, the
2. If
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
t
BDA
BUSY
will be asserted (70121 only).
2654 drw 13
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Interrupt Timing
t
AS Address Set-up Time 0 — 0 — 0 — 0 — ns
t
WR Write Recovery Time 0 — 0 — 0 — 0 — ns
t
INS Interrupt Set Time — 25 — 25 — 40 — 45 ns
t
INR Interrupt Reset Time — 25 — 35 — 40 — 45 ns
NOTE: 2654 tbl 11
1. "X" in part numbers indicates power rating (S or L).
(1)
70121X25 701 21X35 70121X45 70121X55
70125X25 701 25X35 70125X45 70125X55
6.10 9
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF INTERRUPT MODE
t
WC
ADDR
R/
INT
W
'A'
'A'
'B'
INTERRUPT SET ADDRESS
(3)
t
AS
(3)
t
INS
(2)
(4)
t
WR
NOTES:.
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I –
NON-CONTENTION READ/WRITE CONTROL
Left or Right Port
WW
CECE
CE
CECE
OEOE
OE
OEOE
R/
W
WW
X H X Z Port Disabled and in Power-
XHX Z
L L X DATAIN Data on Port Written I nto Memory
H L L DATAOUT Data in Memory Output on Port
H L H Z High-impedance Outputs
NOTES: 2654 tbl 12
1. A0L – A10L ≠ A0R – A10R.
2. If
BUSY
3. If
BUSY
4. 'H' = V
IL, data is not written.
= V
IL, data may not be valid, see tWDD and tDDD timing.
= V
IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
(1)
D0–8 Function
Down Mode, I
CE
R = CEL = H, Power-Down
Mode, I
SB2 or ISB4
SB1 or ISB3
(4)
(2)
(3)
2654 drw 14
TRUTH TABLE II – INTERRUPT FLAG
(1,4)
Left Port Right Port
WW
R/
CECE
W
CE
L
WW
CECE
LLX 7FF XXXX X L
X X X X X X L L 7FF H
XXX X L
X L L 7FE H
NOTES: 2654 tbl 13
1. Assumes
2. If
3. If
4. 'H' = V
BUSY
BUSY
L = VIL, then No Change.
R = VIL, then No Change.
BUSY
IH,' L' = VIL,' X' = DON’T CARE.
OEOE
OE
L
L =
OEOE
BUSY
L A0L – A10L
R = VIH
INTINT
INT
INTINT
(3)
L R/
(2)
CECE
WW
CE
W
R
CECE
WW
L L X 7FE X Set Left
OEOE
OE
R
R A0L – A10R
OEOE
INTINT
INT
R Function
INTINT
(2)
(3)
Set Right
Reset Right
INT
X X X X X Reset Left
6.10 10
INT
L Flag
INT
R Flag
INT
L Flag
R Flag
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT70121/125 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70121/125 has an
automatic power down feature controlled by CE. The
CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
L) is asserted when the right port
INT
writes to memory location 7FE (HEX), where a write is defined
as the CE = R/W = VIL per the Truth Table. The left port clears
the interrupt by access address location 7FE access when
CE
R = OER = VIL, R/
interrupt flag (
W
is a "Don't Care". Likewise, the right port
INT
R) is asserted when the left port writes to
memory location 7FF (HEX) and to clear the interrupt flag
(
INT
R), the right port must access the memory location 7FF.
The message (9 bits) at 7FE or 7FF is user-defined, since it is
an addressable SRAM location. If the interrupt function is not
used, address locations 7FE and 7FF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the
BUSY
pins high. Once in slave mode the
BUSY
pin
operates solely as a write inhibit input pin. Normal operation
can be programmed by tying the
BUSY
pins high. If desired,
unintended write operations can be prevented to a port by
tying the busy pin for that port low.
The busy outputs on the IDT70121/125 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70121/125 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70121 RAM the busy pin
is an output of the part, and the busy pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
IDT70121
MASTER
Dual Port
RAM
BUSY
L
IDT70121
MASTER
Dual Port
RAM
BUSY
BUSY
L
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70121 (Master) and IDT70125 (Slave) RAMs.
L
BUSY
BUSY
CE
R
CE
R
IDT70125
SLAVE
Dual Port
RAM
BUSY
L
IDT70125
SLAVE
Dual Port
RAM
BUSY
L
BUSY
BUSY
CE
CE
DECODER
R
BUSY
R
R
2654 drw 15
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.10 11
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device
Type
A
Power
999
SpeedAPackage
A
Process/
Temperature
Range
Blank
J
25
35
45
55
L
S
70121
70125
Commercial (0°C to +70°C)
52-pin PLCC (J52-1)
Speed in nanoseconds
Low Power
Standard Power
18K (2K x 9-Bit) MASTER Dual-Port RAM
w/ Interrupt
18K (2K x 9-Bit) SLAVE Dual-Port RAM
w/ Interrupt
2654 drw 16
6.10 12
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