Datasheet IDT7008S-L Datasheet (IDT)

查询IDT7008L20G供应商

HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous
reads of the same memory location

◆

High-speed access

– Military: 25/35/55ns (max.)
– Industrial: 55ns (max.)
– Commercial: 20/25/35/55ns (max.)

◆

Low-power operation

– IDT7008S

Active: 750mW (typ.)
Standby: 5mW (typ.)

– IDT7008L

Active: 750mW (typ.)
Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without
external logic

Functional Block Diagram

IDT7008S/L

◆

IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device

◆

M/S = VIH for BUSY output flag on Master,
M/S = V

◆

◆

◆

◆

◆

◆

◆

IL for BUSY input on Slave

Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds

R/

W

L

CE

0L

CE

1L

OE

L

I/O

0-7L

(1,2)

BUSY

L

A

15L

A

0L

SEM

L

(2)

INT

L

NOTES:

1. BUSY is an input as a Slave (M/S = V

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

©2000 Integrated Device Technology, Inc.

Address
Decoder

CE

0L
1L

CE

OE

L
L

R/

W

IL) and an output when it is a Master (M/S = VIH).

Control

16 16

I/O

64Kx8

MEMORY

ARRAY

7008

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

(1)

M/

S

1

I/O

Control

Address
Decoder

CE

0R
1R

CE

OE

R

R

R/

W

R

R/

W

CE

0R

CE

1R

OE

R

3198 drw 01

I/O

0-7R

(1,2)

BUSY

R

15R

A
A

0R

R

SEM

(2)

INT

R

MAY 2000

DSC 3198/6

IDT7008S/L

,

High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error­free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE

0 and CE1) permit the on-chip

circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 750mW of power.

The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA),
a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad
Flatpack (TQFP).

Pin Configurations

INDEX

6R

A

12

5R

A

13

4R

A

14

3R

A

15

A

2R

16

A

1R

17

0R

A

18

R

INT

BUSY

M/

GND

BUSY

INT

NC
A
A
A
A
A
A
A

19

R

20

S

21
22

L

23

L

24
25

0L

26

1L

27

2L

28

3L

29

4L

30

5L

31

6L

32

33 34 35 36 37 38 39 40 41 42 43 44 45

(1,2,3)

R

R

9

8

7

A

A

A

1

1

1

A

A

A

R

R

R

2

1

0

R

R

R

R

4

3

1

1

A

A

D

5

N

C

C

1

A

N

G

N

11 10 9 8 7 6 5 4 3 2 1 84 83

IDT7008J

(4)

J84-1

84-Pin PLCC

Top View

(5)

R

R
0

E

C

C

N

R

R

1

E
C

R

D

M

W

E

/

S

R

D

E

N

N

O

G

G

82 81 80 79 78 77 76 75

46 47 48 49 50 51 52 53

74
73
72
71

70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

C
N

NC

7R

I/O

6R

I/O
I/O

5R

I/O

4R
3R

I/O
Vcc

2R

I/O

1R

I/O
I/O

0R

GND
Vcc

0L

I/O

L

I/O1
GND

2L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

L

8

7

9

A

A

A

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

2

0

1

1

1

1

A

A

A

L

L

L

L

c

3
1

A

C

5

4

1

A

c

1

N

V

A

L

C

C

0

N

N

E
C

L

L

L
1

E
C

L

D

E

M

W

I

N

O

E

R

S

G

D
N
G

3198drw 02

C
N

L

L

L

L

2

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

Index

A
A

A
A
A
A
A
A
A

Vcc

CE

CE

SEM

R/

OE

GND

NC
NC

7L
8L

9L
10L
11L
12L
13L
14L
15L

NC

NC
NC
NC
NC

0L

1L

W

NC
NC

L

Y

L

L

L

L

C

C

6

N

N

A

100999897 969594939291908988 8786 85848382818079 7877 76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

L

20

L

21

L

22
23
24
25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

L

D

C

7

N

N

O

/

G

I

L

5

4

3

A

A

A

L

L

L

6

4

5

O

O

O

/

/

/

I

I

I

L

L

L

0

1

2

A

A

A

L

L

D

2

3

N

O

O

/

/

I

G

I

S

T

U

C

N

I

B

N

IDT7008PF

PN100-1

100-Pin TQFP

Top View

L

L

c

0

1

c

O

V

O

/

/

I

I

R

Y

D
N
G

D
N
G

R

S

S

/
M

(

4)

(5)

R

0

O

/

I

R

T

U

0

N

B

I

A

c

R

R

c

1

2

V

O

O

/

/

I

I

R

R

R

3

2

1

A

A

A

R

R

4

3

O

O

/

/

I

I

R

R

R

5

4

A

A

C

C

6

N

N

A

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
NC

7R

A
A

8R
9R

A
A

10R
11R

A

12R

A

13R

A

14R

A
A

15R

NC
GND
NC
NC
NC
NC

CE

CE

SEM

W

R/

OE

GND
GND
NC

0R
1R

R

R

R

,

C
N

3198 drw 03

C
N

R

R

R

5

O

/

I

C

7

6

N

O

O

/

/

I

I

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

6.42

3

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

(1,2,3)

Pin Configurations

(con't)

63 61 60 58 55 54 51 48 46 45

11

66

10

67

09

69

08

72

BUSY

07

75

06

BUSY

76

INT

05

79

04

81

03

82

02

84346915131618

01

A

A

A

A

A

A

A

A

A

9R

7R

64

62

A

6R

4R

65

A

5R

3R

68

A

2R

1R

73

71

R

R

INT

74

70

A

0R

L

78

77

L

NC

80

A

2L

1L

83

A

3L

5L

12578

A

7L

4L

A

9L

6L

A

A

10R

59 56 49 50 40

A

A

8R

M/

S

GND

A

0L

A

A

8L

A

A

10L

ABC DEF GHJK L

INDEX

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

A

15R

12R

A

14R

11R

57 53 52

A

13R

84-Pin PGA
Top View

A

13L

A

14L

11L

A

15L

12L

NC

NC

0R

CE

CE

1R

NC

GND

IDT7008G

(4)

G84-3

(5)

11

12

NC

Vcc

10

14 17 20

0L

CE

NC

CE

NC

1L

Pin Names

Left Port Right Port Names

R

SEM

47 44

R/

R

W

R/

L

W

L

SEM

R

OE

GND

33 35

I/O

0R

32 31

GND

28 29

GND

GND

L

OE

GND

43

NC

41

I/O

7R

38

I/O4RI/O

I/O

2R

Vcc

I/O1

L

26

I/O

3L

23

I/O

6L

22 24

I/O

7L

19 21

GND

3198 drw 04

42

NC

I/O

6R

39

I/O

5R

37

3R

34

I/O

1R

36

Vcc

30

I/O

0L

27

I/O

2L

25

I/O

4L

I/O

5L

NC

,

4

CE

0L

W

R/

OE

L

A0L - A

0L

I/O

SEM

INT

L

BUS Y

, CE

L

- I/O

L

L

15L

1L

7L

CE

W

R/

OE

A0R - A

I/O0R - I/O

SEM

INT

BUS Y

S

M/

CC

V

0R

, CE

R

R

15R

R

R

R

GND Ground

1R

Chip Enables
Read /Wri te En able
Output Enable

Address

7R

Dat a In p ut/ O ut p ut
Semaphore Enable
Interr up t Flag
Busy Flag
Master or Slave Select
Power

3198 tbl 01

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable

1

CE CE

V

L

< 0. 2V >VCC -0.2V Po rt Se lec te d (CMOS Ac tive )

V

H

>

VCC -0.2V X Po rt Des e lec te d (CMOS Inactive )

0

IL

IH

XV

CE

IH

V

X Port Deselected (TTL Inactive)

IL

(1)

Mode

Port Selected (TTL Active)

Port Deselected (TTL Inactive)

X<

NOTES:

1. Chip Enable references are shown above with the actual CE

0.2V Po rt Deselected (CMOS Inactive)

0 and CE1 levels, CE is a reference only.

Truth Table II: Non-Contention Read/Write Control

(1)

Inputs

(2)

W

CE

R/

OE SEM

H X X H High-Z Dese le c ted : P o wer-Do wn

LLXHDATAINWrite to me mory
LHLHDATA

X X H X Hig h-Z Outputs Dis abl e d

NOTES:

0L – A15L ≠ A0R – A15R.

1. A

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control

Inputs Outputs

(2)

W

R/

CE

HHLLDATA

OE SEM

Outputs

I/O

0-7

I/O

OUT

0-7

OUT

Read me mory

Read Semaphore Flag Data Out

Mode

(1)

Mode

3198 tbl 02

3198 t bl 03

↑

H
LXXL

NOTES:

1. There are eight semaphore flags written to via I/O

2. Refer to Chip Enable Truth Table.

XLDATAINWrite I/ O0 into Semaphore Flag

______

Not Al lo wed

0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.

6.42

5

3198 tbl 04

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings

Symbol Rating Commercial

(2)

V

TERM

Terminal Voltage
with Re s p e ct
to G ND

T

BIAS

T emperature

Unde r Bias

T

I

OUT

STG

Storage

T emperature

DC Output Current 50 50 mA

NOTES:

& Industrial

-0.5 to +7.0 -0.5 to +7.0 V

-55 to +125 -65 to +135oC

-65 to +150 -65 to +150oC

(1)

Military Unit

3198 t bl 05

Recommended DC Operating
Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

V

Sup p ly Vo ltag e 4.5 5. 0 5.5 V

GND Ground 0 0 0 V

IH

V

Inp u t Hi g h Vo l ta g e 2. 2

IL

V

Input Lo w Voltag e -0.5

NOTES:

1. V

IL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 10%.

2. V

____

(1)

____

(2)

6.0

0.8 V

3198 tbl 07

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

2. V
maximum, and is limited to

< 20mA for the period of VTERM > Vcc + 10%.

Maximum Operating Temperature
and Supply Voltage

Grade

Ambient

Temperature GND Vcc

(1,2)

Capacitance

(TA = +25°C, f = 1.0mhz) (TQFP Only)

)1(

ecnaticapaCtupnIV

ecnaticapaCtuptuOV

C

NI

C

TUO

lobmySretemaraP

NOTES:

1. This parameter is determined by device characterization but is not production
tested.

2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.

snoitidnoC

NI

Vd3=9Fp

TUO

Vd3=01Fp

)2(

.xaMtinU

Military -55OC to+1 25OC0V 5.0V + 10%

O

Commercial 0

C to +7 0OC0V 5.0V + 10%

Industrial -40OC to +8 5OC0V 5.0V + 10%

NOTES:

1. This is the parameter T

A. This is the "instant on" case tempreature.

3198 tbl 06

2. Industrial Temperature: for other speeds, packages and powers contact your
sales office.

V

80lbt8913

DC Electrical Characteristics Over the Operating

(2)

Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

|ILI| Input Leak ag e Current

|I

Output Leak age Current

LO

|

V

Output Low Voltag e IOL = 4mA

OL

V

Output High Vol tage IOH = -4mA 2.4

OH

NOTES:

1. At Vcc

< 2.0V, input leakages are undefined.

2. Refer to Chip Enable Truth Table.

(1)

VCC = 5.5V, VIN = 0V to V

CE

= V

, V

= 0V to V

IH

OUT

CC

CC

6

(VCC = 5.0V ± 10%)

7008S 7008L

___

___

___

10
10

0.4

___

2.4

UnitMin. Max. Min. Max.

___

___

___

5µA
5µA

0.4 V

___

V

3198 tbl 09

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(1,6,7)

Temperature and Supply Voltage Range

Symb ol Parameter Test Conditi on Version Typ.

CC

Dynamic Op e rating

I

Current
(Bo th Po rts Ac tiv e)

SB1

Standby Current

I

(Both Ports - TTL Level
Inputs)

SB2

Standby Current

I

(On e Po rt - TTL L e v e l
Inputs)

SB3

Full S tandb y Curre nt

I

(Bo th Po rts - Al l CMO S
Lev e l Inputs)

SB4

Full S tandb y Curre nt

I

(On e Po rt - A l l C MO S
Lev e l Inputs)

Symb ol Parameter Test Conditi on Version Typ.

CC

Dynamic Ope rating Current

I

(Bo th Po rts Ac tiv e)

SB1

Standby Current

I

(Both Ports - TTL Level
Inputs)

SB2

Standby Current

I

(On e Po rt - TTL L e v e l
Inpu ts)

SB3

Full S tandb y Curre nt

I

(Bo th Po rts - Al l CMO S
Lev e l Inputs)

SB4

I

Full S tandb y Curre nt
(On e Po rt - A l l C MO S
Lev e l Inputs)

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

IL

, Outputs Disabled

CE = V

IH

SEM = V

(3)

MAX

f = f

L

= CER = V

CE
SEM

MAX

f = f

"A"

CE

Active Port Outputs Disabled,

MAX

f=f

SEM

Both Ports CEL and

R

> VCC - 0.2V

CE

IN

> VCC - 0.2V o r

V

IN

< 0.2V, f = 0

V

SEM

"A"

CE

"B"

CE
SEM

IN

> VCC - 0.2V or VIN < 0.2V

V
Ac ti v e P o rt Outp u ts D is ab l e d

MAX

f = f

CE = V
SEM = V

MAX

f = f

L

= CER = V

CE
SEM

"A"

CE

Active Port Outputs Disabled,

MAX

f=f

SEM

Both Ports CE

R

> VCC - 0.2V

CE

IN

> VCC - 0.2V o r

V

IN

< 0.2V, f = 0

V

SEM

"A"

CE

"B"

CE
SEM

IN

> VCC - 0.2V or VIN < 0.2V

V
Ac ti v e P o rt Outp u ts D is ab l e d

MAX

f = f

IH

R

= SEML = V

= VIL and CE

(3)

R

= SEML = V

R

= SEML > VCC - 0.2V

< 0.2V and
> VCC - 0.2V

R

= SEML > VCC - 0.2V

IL

R

= SEML = V

= VIL and CE

(3)

R

= SEML = V

R

= SEML > VCC - 0.2V

< 0.2V and
> VCC - 0.2V

R

= SEML > VCC - 0.2V

IH

(3)

"B"

IH

(4)

(5)

(3)

, Outputs Disabled

IH

(3)

IH

IH

"B"

IH

L

and

(4)

(5)

(3)

= V

= V

(5)

IH

(5)

IH

(VCC = 5.0V ± 10%)

COM'L SL190

MIL &
IND

COM'L SL50

MIL &
IND

COM'L SL115

MIL &
IND

COM'L SL1.0

MIL &
IND

COM'L SL110

MIL &
IND

COM'L SL160

MIL &
IND

COM'L SL30

MIL &
IND

COM'L SL95

MIL &
IND

COM'L SL1.0

MIL &
IND

COM'L SL90

MIL &
IND

180

S
L

S
L

115

S
L

0.2

S
L

110

S
L

160

SL160

160

SL20

SL95

0.2

SL1.0

0.2

SL90

7008X20

Com'l On ly

(2)

___
___

50

___
___

___
___

___
___

___
___

7008X35
Com'l &

Military

(2)

30

20

95

95

90

90

Max. Typ.

325
285

___
___

90
70

___
___

215
185

___
___

15

5

___
___

190
160

___
___

Max. Typ.

295
255

335
295

85
60

100

80

185
155

215
185

15

5

30
10

160
135

190
165

7008X25
Com'l &
Military

(2)

180
170

170
170

40
40

40
40

105
105

105
105

1.0

0.2

1.0

0.2
100

100
100

100

7008X55

Com'l, Ind

& Military

(2)

150
150

150
150

20
20

13
13

85
85

85
85

1.0

0.2

1.0

0.2
80

80
80

80

Max. Unit

305

mA

265
345

305

85

mA

60

100

80

mA

200
170

230
200

15

mA

5

30
10

mA

170
145

200
175

3198 tbl 10a

Max. Unit

270

mA

230
310

270

85

mA

60

100

80

mA

165
135

195
165

mA

15

5

30
10

mA

135

110

175
150

3198 tbl 10b

6.42

7

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Test Conditions

Input Pulse Levels
Inp ut Rise / Fal l Time s
Inp ut Timing Re fe re nce Le v el s
Output Reference Leve ls
Output Load

Waveform of Read Cycles

ADDR

AA

t

CE

OE

(6)

ACE

t

t

AOE

GND to 3.0V

5ns M ax .

1.5V

1.5V

Fi g ure s 1 and 2

(5)

(4)

(4)

(4)

3198 tbl 11

RC

t

DATA

OUT

BUSY

INT

Figure 1. AC Output Test Load

347

Ω

5V

893

30pF

3198 drw 05

5V

Ω

DATA

OUT

Ω

347

Figure 2. Output Test Load

LZ, tHZ, tWZ, tOW)

(for t

* Including scope and jig.

Ω

893

5pF*

3198 drw 06

W

R/

DATA

BUSY

OUT

OUT

(1)

LZ

t

VALID DATA

(3,4)

BDD

t

(4)

OH

t

(2)

HZ

t

3198 drw 07

Timing of Power-Up Power-Down

(6)

CE

PU

CC

I

SB

I

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

3. t
has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t

5. SEM = V

6. Refer to Chip Enable Truth Table.

IH.

t

AOE, tACE, tAA or tBDD.

PD

t

3198 drw 08

,

8

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range

READ CY CLE

RC

t

AA

t

ACE

t

AOE

t

OH

t

LZ

t

HZ

t

PU

t

PD

t

SOP

t

SAA

t

Rea d Cyc l e Time 20
Address Access Time
Chip Enable Access Time

(4)

Output Enable Access Time
Output Ho ld fro m A dd re s s Change 3
Output Lo w-Z Time
Output Hig h-Z Time
Chip Enab le to P o we r Up Ti me
Chip Dis ab le to P o we r Do wn Tim e
Semaphore Flag Update Pulse (OE or

(1,2)

(1,2)

(2)

(2)

SEM

)10

Semaphore Address Access Time

7008X20

Com'l Only

____

____

____

3

____

0

____

____

____

20
20
12

____

____

12

____

20

____

20

7008X25 Com 'l

& Military

25

____

____

____

3
3

____

0

____

12

____

AC Electrical Characteristics Over the

____

____

____

____

____

____

____

12

____

12

____

____

____

(6,7)

7008X25
Com 'l &

Military

25
20
20

0

20

0

15

____

0

____

0
5
5

Operating Temperature and Supply Voltage

7008X20

Com'l Only

Symbol Parameter

WR I T E C Y CL E

WC

t

EW

t

AW

t

AS

t

WP

t

WR

t

DW

t

HZ

t

DH

t

WZ

t

OW

t

SWRD

t

SPS

t

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranted by device characterization, but is not production tested.

3. To access RAM, CE= V

4. To access RAM, CE = V

5. The specification for t

6. 'X' in part numbers indicates power rating (s or L).

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

Write Cycle Time 20
Chip Enable to End-of-Write

(3)

Add ress Valid to End-of-Write 15
Add ress Set-up Time

(3)

Write Pulse Width 15
Write Rec o v e ry Time 0
Data Va li d to E nd - o f-Wr ite 15
Output Hig h-Z Time
Data Ho ld Ti me
Write Enable to Output in High-Z
Outp u t Acti v e fro m E nd -o f- Wri te

(1,2)

(5)

(1,2)

(1, 2,5 )

SEM Flag Write to Read Time 5
SEM Flag Contention Window 5

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

IL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t

DH will always be smaller than the actual tOW.

15

0

____

0

____

0

(6,7)

____

25
25

13

____

____

15

____

25

____

25

____

____

____

____

____

____

____

15

____

15

____

____

____

7008X35 Com 'l

& Military

____

35

____

35

____

35

____

20

____

3

____

3

____

15

____

0

____

35

____

15

____

35

7008X35
Com 'l &

Military

____

35

____

30

____

30

____

0

____

25

____

0

____

15

____

15

____

0

____

15

____

0

____

5

____

5

7008X55

Com'l, Ind

& Military

55

____

____

____

3
3

____

0

____

15

____

7008X55

Com'l, Ind

& Military

55
45
45

0

40

0

30

____

0

____

0
5
5

____

55 ns
55 ns
30 ns

____

____

25 ns

____

50 ns

____

55 ns

3198 tb l 12

____

____

____

____

____

____

____

25 ns

____

25 ns

____

____

____

3198 tb l 13

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.

ns

ns
ns

ns

ns

UnitMin. Max. Min. Max. Min. Max. Min. Max.

ns
ns
ns
ns
ns
ns
ns

ns

ns
ns
ns

6.42

9

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

WC

t

(1,5,8)

ADDRESS

(7)

t

HZ

OE

t

AW

CEorSEM

(9,10)

(3)

t

WR

t

OW

t

DH

DATA

DATA

R/

OUT

(6)

t

AS

t

WP

(2)

W

(7)

t

WZ

(4) (4)

t

DW

IN

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

t

WC

ADDRESS

t

AW

R/

DATA

(9,10)

(6)

t

AS

t

EW

(2)

t

WR

(3)

W

DW

t

IN

DH

t

CEorSEM

3198 drw 09

(1,5)

3198 drw 10

NOTES:

1. R/W or CE

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

3. t

must be HIGH during all address transitions.

EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE

6. Timing depends on which enable signal is asserted last, CE

or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
placed on the bus for the required t
the specified t

9. To access RAM, CE

WP.

= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

WP or (tWZ + t DW) to allow the I/O drivers to turn off and data to be

10. Refer to Chip Enable Truth Table.

10

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side

(1)

SAA

t

2

NOTES:

1. CE = V

2. "DATA

A0-A

SEM

0

DATA

W

R/

OE

IH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

OUT VALID" represents all I/O's (I/O0 - I/O15) equal to the semaphore value.

VALID ADDRESS

AW

t

EW

t

DATAINVALID

AS

t

WP

t

Write Cycle

t

DW

t

WR

VALID ADDRESS

SOP

t

DH

t

SWRD

t

SOP

t

Read Cycle

Timing Waveform of Semaphore Write Contention

ACE

t

AOE

t

(1,3,4)

DATA

VALID

OUT

(2)

OH

t

3198 drw11

0"A"-A2"A"

A

(2)

SIDE "A"

A

(2)

SIDE

NOTES:

OR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).

1. D

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W

SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

4. If t

"B"

"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

"A"

R/

W

"A"

SEM

0"B"-A2"B"

"B"

W

R/

"B"

SEM

MATCH

MATCH

SPS

t

3198 drw12

6.42

11

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

7008X25
Com ' l &

Military

5

0

(6,7)

20
20
20

17

____

25

____

____

____

50
35

7008X35
Com ' l &

Military

____

____

____

____

5

____

25

0

25

____

____

20
20
20
20

____

35

____

____

____

60
45

7008X55

Com'l, Ind &

Military

____

45 ns

____

40 ns

____

40 ns

____

35 ns

____

5

____

55 ns

____

25

____

0

____

25

____

80 ns

____

65 ns

ns

ns

ns
ns

3198 t bl 14

IH)".

Operating Temperature and Supply Voltage Range

7008X20

Com ' l O nl y

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

TIMING (M/S=V

BUSY

t

BAA

t

BDA

t

BAC

t

BDC

t

APS

t

BDD

t

WH

BUSY

t

WB

t

WH

BUSY

BUSY

BUSY

BUSY

Arbitration Priority Set-up Time

BUSY

Write Hol d A fter

TIMING (M/S=V

BUSY

Write Hol d A fter

PO RT-TO-PO RT DE L AY TI M I NG

t

WDD

t

DDD

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V

2. To ensure that the earlier of the two ports wins.

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

Write Pulse to Data Delay
Write Data Valid to Read Data Delay

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

)

IH

Access Time from Address Match
Disable Time from Address Not Matched
Access Time from Chip Enable Low
Access Time from Chip Enable High

(2)

Disable to Valid Data

BUSY

)

IL

Inp ut to W rite

BUSY

(3)

(5)

(4)

(5)

(1)

(1)

____

____

____

____

____

____

____

____

20

____

20

____

20

____

17

____

5

____

20

____

15

0

15

____

____

17

17

____

45

____

30

12

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

(2,5)

Timing Waveform of Write with Port-to-Port Read and BUSY

t

WC

ADDR

"A"

R/

"A"

W

DATA

IN "A"

(1)

t

APS

ADDR

"B"

"B"

BUSY

DATA

OUT "B"

NOTES:

1. To ensure that the earlier of the two ports wins. t

L = CER = VIL, refer to Chip Enable Truth Table.

2. CE

3. OE = V

4. If M/S = V

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

IL for the reading port.

IL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

APS is ignored for M/S = VIL (SLAVE).

MATCH

t

WP

t

DW

VALID

MATCH

t

WDD

t

DDD

(M/S = V IH)

t

DH

t

BDA

(3)

t

BDD

VALID

3198 drw 13

(4)

Timing Waveform of Write with BUSY (M/S = VIL)

WP

t

"A"

W

R/

(3)

WB

t

"B"

BUSY

"B"

W

R/

NOTES:

WH must be met for both BUSY input (SLAVE) and output (MASTER).

1. t

2. BUSY is asserted on port "B" blocking R/W

WB is only for the 'Slave' version.

3. t

"B", until BUSY"B" goes HIGH.

(2)

t

WH

(1)

3198 drw 14

6.42

13

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

(1,3)

Waveform of BUSY Arbitration Controlled by CE Timing

"A"

ADDR

and

CE

CE

"B"

"A"

"B"

APS

t

(2)

ADDRESSES MATCH

(M/S = VIH)

BUSY

"B"

BAC

t

BDC

t

3198 drw15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

(1)

Timing

ADDR

ADDR

BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2. If t

3. Refer to Chip Enable Truth Table.

(M/S = VIH)

"A"

"B"

"B"

ADDRESS "N"

(2)

APS

t

MATCHING ADDRESS "N"

BAA

t

BDA

t

3198 drw 16

AC Electrical Characteristics Over the

____

____

(1,2)

7008X35

Com 'l &

Military

____

0

____

0
20
20

____

____

25
25

7008X55

Com'l, Ind

& Military

0
0

____

____

____

____

40 ns
40 ns

3198 t bl 15

ns
ns

Operating Temperature and Supply Voltage Range

7008X20

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

t

AS

t

WR

t

INS

t

INR

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. Industrial Temperature: for other speeds, packages and powers contact your sales office.

Address Set-up Time 0

Write Recovery Time 0
Inte rrupt Se t Tim e
Inte rrup t Re s et Tim e

____

____

____

____

20
20

14

7008X25

Com 'l &
Military

0
0

____

____

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

"A"

ADDR

CE

R/

INT

ADDR

CE

W

"A"

"A"

"B"

"B"

"B"

INTERRUPT SET ADDRESS

(3)

AS

t

(3)

INS

t

INTERRUPT CLEAR ADDRESS

(3)

AS

t

(1,5)

t

WC

RC

t

(2)

(4)

WR

t

3198 drw 17

(2)

"B"

OE

(3)

INR

t

"B"

INT

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE

or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

Truth Table IV  Interrupt Flag

(1,4,5)

Left Po rt Righ t Por t

W

L

CE OE

A

L

15L-A0L

INT

L

L L X FFFF X X X X X L
XXXXXXLLFFFFH
XXX X L
X L L FFFE H

(3)

(2)

W

R/

R

CE OE

A

R

15R-A0R

INT

R

(2)

(3

)

L L X FFFE X Set Left

X X X X X Rese t L e ft

NOTES:

1. Assumes BUSY

2. If BUSY

3. If BUSY

L and INTR must be initialized at power-up.

4. INT

L = BUSYR =VIH.
L = VIL, then no change.
R = VIL, then no change.

5. Refer to Chip Enable Truth Table.

3198 drw 18

Se t Ri g ht
Rese t Rig ht

INT

FunctionR/

INT

INT

INT

L

Flag

R

Flag

Flag

L

R

Flag

31 98 tb l 16

6.42

15

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table V Address BUSY
Arbitration

Inputs Outputs

L

CE

NOTES:

1. Pins BUSY

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

3. Writes to the left port are internally ignored when BUSY

4. Refer to Chip Enable Truth Table.

R

CE

XXNO MATCH H H Normal
HXMATCHHHNormal
XHMATCHHHNormal

LL MATCH (2) (2)

push-pull, not open drain outputs. On slaves the BUSY
and enable inputs of this port. If t
when BUSY

Truth Table VI  Example of Semaphore Procurement Sequence

No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Write s " 0" to S em apho re 1 0 No c hange . Left po rt has no write acc e ss to s em apho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7008.

2. There are eight semaphore flags written to via I/O

3. CE = V

IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

(4)

AOL-A

15L

AOR-A

15R

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are

R outputs are driving LOW regardless of actual logic level on the pin.

Functions D0 - D7 Left D0 - D7 Right Status

(1)

L

BUSY

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

(1)

Function

R

BUSY

Write

(3)

Inhibit

3198 tbl 17

input internally inhibits writes.

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

(1,2,3)

0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.

3198 tbl 18

Functional Description

The IDT7008 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7008 has an automatic power down feature controlled
by CE. The CE0 and CE1 control the on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag

(INT

L) is asserted when the right port writes to memory location FFFE

(HEX), where a write is defined as CER = R/WR = VIL per the Truth Table.
The left port clears the interrupt through access of address location FFFE
when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location FFFF. The message (8 bits) at FFFE or FFFF is user­defined since it is an addressable SRAM location. If the interrupt function
is not used, address locations FFFE and FFFF are not used as mail boxes,
but as part of the random access memory. Refer to Table IV for the interrupt
operation.

16

IDT7008S/L

,

High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT7008 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.

16

A

0

MASTER
Dual Port RAM

BUSY

MASTER
Dual Port RAM

BUSY

Figure 3. Busy and chip enable routing for both width and depth

CE

BUSY

(L)

CE

BUSY

(L)

expansion with IDT7008 RAMs.

(R)

1

(R)

SLAVE
Dual Port RAM

BUSY

(L)

SLAVE
Dual Port RAM

BUSY

(L)

BUSY

BUSY

CE

CE

0

(R)

1

(R)

3198 drw 19

Width Expansion Busy Logic
Master/Slave Arrays

When expanding an IDT7008 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7008 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown
in Figure 3.

If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can

result in a glitched internal write inhibit signal and corrupted data in the
slave.

Semaphores

The IDT7008 is an extremely fast Dual-Port 64K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non­semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where CE and SEM are both HIGH.

Systems which can best use the IDT7008 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a per-formance increase offered by the IDT7008s hardware sema­phores, which provide a lockout mechanism without requiring complex
programming.

Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7008 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.

An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high­speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via

6.42

17

IDT7008S/L

,

High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.

The eight semaphore flags reside within the IDT7008 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, CE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A

0 – A2. When accessing the semaphores, none of

the other address pins has any effect.

When writing to a semaphore, only data pin D

0 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.

A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
VI). As an example, assume a processor writes a zero to the left port at
a free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right

side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip

LPORT

SEMAPHORE

REQUESTFLIP FLOP

0

D

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT7008 Semaphore Logic

Q

RPORT

0

D

D

WRITE

SEMAPHORE
READ

3198 drw 20

over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta­neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.

One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.

18

IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

NOTE:

1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.

Blank

(1)

I
B

PF
G
J

20
25
35
55

S
L

7008

Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°Cto+125°C)

Compliant to MIL-PRF-38535 QML

100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
84-pin PLCC (J84-1)

Commercial Only
Commercial & Military
Commercial & Military
Commercial, Industrial

Speed in

nanoseconds

& Military

StandardPower
Low Power

512K(64Kx 8) Dual-Port RAM

,

3198 drw 21

Datasheet Document History

1/6/99: Initiated datasheet document history

Converted to new format
Cosmetic and typographical corrections

Pages 2 and 3 Added additional notes to pin configurations
6/3/99: Changed drawing format
11/10/99: Replaced IDT logo
5/8/99: Page 6 Increased storage temperature parameter

Clarified TA parameter
Page 7 DC Electrical paramters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes

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2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: [phone] [e-mail]

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

www.idt.com

19