Datasheet IDT7007L55JI, IDT7007L55PFI, IDT7007S15G, IDT7007L15G, IDT7007L15J Datasheet (Integrated Device Technology Inc)

HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous reads of the same memory location

◆

High-speed access

 Military: 25/35/55ns (max.)  Industrial: 55ns (max.)  Commercial: 15/20/25/35/55ns (max.)

◆

Low-power operation

 IDT7007S

Active: 850mW (typ.) Standby: 5mW (typ.)

 IDT7007L

Active: 850mW (typ.) Standby: 1mW (typ.)

◆

IDT7007 easily expands data bus width to 16 bits or more

Functional Block Diagram

IDT7007S/L

using the Master/Slave select when cascading more than one device

◆

M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave

◆

Interrupt Flag

◆

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling between ports

◆

Fully asynchronous operation from either port

◆

TTL-compatible, single 5V (±10%) power supply

◆

Available in 68-pin PGA and PLCC and a 80-pin TQFP

◆

Industrial temperature range (40°C to +85°C) is available for selected speeds

OE

L

CE

L

R/W

L

I/O0L- I/O

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

7L

(1,2) (1,2)

BUSY

L

A

SEM

INT

14L

0L

L

(2)

L

Addre ss Decoder

CE OE

R/W

L L L

15

I/O

Control

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/S

1

I/O

Control

OE

R

CE

R

R/W

R

I/O0R-I/O

BUSY

Address Decoder

15

CE

R

OE

R

R/W

R

A A

SEM INT

2940 drw 01

14R

0R

7R

R

(2)

R

JUNE 1999

DSC 2940/8

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter a very LOW standby power mode.

Fabricated using IDTs CMOS high-performance technology, these

devices typically operate on only 850mW of power.

The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, and an 80-pin thin quad flatpack, TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

Pin Configurations

INDEX

I/O

2L

I/O

3L

I/O

4L

I/O

5L

GND I/O

6L

I/O

7L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

(1,2,3)

L

0

1

O

/

I

98765432168676665 10 11

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28 29 30 31 32 33 34 35 36 37 38 39

L

M

W

C

E

/

/ N

E S

O

R

L

E C

C

3

4

1

C

A

V

IDT7007J

(4)

J68-1

68-Pin PLCC

Top View

(5)

L

2

1

A

L

0

L

1

A

64 63 62 61

40 41 42 43

L

9

8

7

A

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

L

6

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

BUSY

GND M/

S

BUSY INT

R

A

0R

A

1R

A

2R

A

3R

A

4R

L

R

C

7

/

E

W

/

N

O

/

I

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately .95 in x .95 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

R

M E S

R

4

E

1

C

A

R

D

2

3

1

N

A

G

2

R

9

1

A

8

0

1

A

R

6

A

2940 drw 0 2

5

A

7

A

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Pin Configurations

INDEX

N/C

2L

I/O

3L

I/O

4L

I/O

5L

I/O

GND

6L

I/O

7L

I/O

CC

V

N/C

GND

0R

I/O

1R

I/O

2R

I/O

CC

V

3R

I/O

4R

I/O

5R

I/O

6R

I/O

N/C

(1,2,3)

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

L

1

0

O

/

I

0

9

8

7

1

2

(con't.)

L

M

W

C

E

/

/ N

787

3 2

S

O

R

7

5

767

4

5

6

2

L

E C

4

7

C

/ N

737

3

4

1

A

2

1

7

L

7007P F

PN80-1

80-Pin TQ FP

Top View

7

8

9

2

0

2

3

C C

V

706

(4)

1 3

(5)

L

2

1

A

9

2 3

1

A

686

3 3

L

0

9

1

A

7

6

4

5

3

L

8

A

656

6 3

L

C

6

7

/

A

N

4

3

1

6

626

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42

7 3

41

8

9

0

3

4

N/C

5L

A

4L

A

3L

A

2L

A

1L

A

0L

A

L

INT BUSY

GND M/S

BUSY

R

INT

0R

A

1R

A

2R

A

3R

A

4R

A N/C N/C

L

R

,

R

E O

W

/ R

R

M E S

E C

C

/

7

N

O

/

I

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

R

C

/ N

D

3

4

N

1

G

A

R

2

1

0

9

1

A

8

1

A

R

7

6

5

A

C

/ N

2940drw 03

C

/ N

3

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

11

10

09

08

07

06

05

04

03

02

53

A

55

A

57

A

59

V

61

A

14L

63

SEM

65

OE

67

I/O

68

I/O

51 50 48 46 44 42 40 38 36

S

L

BUSY

M/

INT

R

A

0R

7L

52

A

5L

49 39 37

A

6L

4L

A

2L

A

0L

BUSY

47 45 43 41 34

INT

L

3L

A

1L

GND

54

9L

A

8L

56

11L

A

10L

58

CC

60

A

12L

A

13L

IDT7007G

G68-1

(4)

68-Pin PGA

62

L

CE

L

Top View

64

L

W

R/

L

66

0L

N/C

13579

1L

I/O

2L

I/O

GND GND

4L

I/O

7L

(5)

11 13 15

V

1R

CC

I/O

A

1R

2R

4R

A

3R

35

A

4R

32

A

7R

30

A

9R

28

A

11R

26

GND

24

A

14R

22

SEM

R

20

OE

R

18 1 9 I/O

7R

33

31

29

27

25

23

21

A

CE

R/

A

5R

A

6R

A

8R

10R

12R

13R

W

N/C

R

01

I/O

3L

I/O

5L

I/O

6L

ABCDEFGH J

INDEX

NOTES:

1. All Vcc pins must be connected to power supply

2. All GND pins must be connected to power supply

3. Package body is approximately 1.8 in x 1.8 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

246810121416

17

I/O

V

CC

I/O2RI/O3RI/O

0R

5R

I/O

6R

K

L

2940 drw 04

Pin Names

Left Port Right Port Names

CE

L CER

W

L

R/

L OER

OE

14L

A0L - A

I/O0L - I/O

SEM

INT

BUSY

7L

L SEMR

L INTR

L BUSYR

W

R

R/

14R

A0R - A

I/O0R - I/O

S

M/

CC

V

GND Ground

7R

Chip Enables

Read/Write Enable

Output Enable

Address

Data Input/ Output

Semaphore Enable

Inte rrup t Flag

Busy Flag

Master or Slave Select

Power

2940 tbl 01

4

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

(1)

Inputs

R/

CE

W

OE SEM

H X X H Hig h-Z Desel ected: Po wer-Down

LLXHDATA

LHLHDATAOUT Read Memory

X X H X High-Z Outputs Disabled

NOTE:

0L  A14L ≠ A0R  A14R

1. A

Outputs

I/O0-7

IN Write to Memory

Mode

2940 tbl 02

Truth Table II: Semaphore Read/Write Control

Inputs Outputs

CE

R/W

OE SEM

HHL LDATA

H

↑

XLDATAINWrite I/O0 into Semaphore Flag

LXXL

NOTE:

1. There are eight semaphore flags written to via I/O

Absolute Maximum Ratings

Symbol Rating Commercial

(2)

TE RM

V

Te rminal Vo ltage with Respect to GND

T

BIAS

Temperature

Under Bias

STG

T

Storage

Temperature

OUT

I

DC Output Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect reliability.

TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

2. V maximum, and is limited to

& Industrial

-0.5 to +7.0 -0.5 to +7.0 V

-55 to + 125 -55 to +135oC

-55 to + 120 -65 to +150oC

50 50 mA

< 20mA for the period of VTERM > Vcc + 10%.

Capacitance (TA = +25°C, f = 1.0mhz)

Symbol Parameter

IN

C

Input Capacitance VIN = 3dV 9 pF

OUT

C

Outp ut Cap acitance V

NOTES:

1. This parameter is determined by device characterization but is not production tested. TQFP package only.

2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.

(1)

Conditions

OUT

= 3dV 10 pF

0-7

I/O

OUT

Read Semaphore Flag Data Out (I/O0-I/O7)

______

0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.

Military Unit

(1)

Not Allowed

Maximum Operating Temperature and Supply Voltage

Grade

Military -55

Commercial 0OC to + 70OC0V 5.0V + 10%

Industrial -40

NOTES:

1. This is the parameter T

2. Industrial temperature: for other speeds, packages and powers contact your

2940 tbl 04

sales office.

Recommended Operating Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

V

Supply Voltag e 4.5 5.0 5.5 V

GND Ground 0 0 0 V

IH

Inp ut Hig h Voltage 2.2

V

(2)

Max. Unit

2940 tbl 07

IL

V

Inp ut Low Voltage -0.5

NOTES:

IL > -1.5V for pulse width less than 10ns.

1. V

TERM must not exceed Vcc + 10%.

2. V

5

(1)

Mode

(1,2)

Ambient

Temperature GND Vcc

O

C to+125OC0V 5.0V + 10%

O

C to + 85OC0V 5.0V + 10%

A.

(1)

____

2940 tbl 03

2940 tbl 05

(2)

6.0

0.8 V

2940 tbl 06

V

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

(VCC = 5.0V ± 10%)

7007S 7007L

Symbol Parameter Test Conditions

|ILI| Input Leakage Current

| Output Leakage Current

|I

LO

OL

V

NOTE:

1. At Vcc

Output Low Voltage IOL = 4mA

Output High Voltage IOH = -4mA 2.4

OH

< 2.0V, input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to V

CE = V

IH

, V

= 0V to V

OUT

CC

___

DC Electrical Characteristics Over the Operating

(1,6)

Temperature and Supply Voltage Range

Symbol Parameter Test Condition Versi on

CC

I

Dynamic Ope rating Current (Both Ports Active )

SB1

Standb y Current

I

(Both Ports - TTL Level Inputs)

SB2

Standb y Current

I

(One Port - TTL Leve l Inputs)

SB3

Full Standb y Current

I

(Both Ports - All CMOS Level Inputs)

IL

, Outputs Open

= V

CE

IH

SEM = V

(3)

MAX

f = f

L

R

=

CE SEMR = SEML = V

MAX

f = f

"A"

CE

Active Port Outputs Open,

MAX

f=f

SEMR = SEML = V

Both Ports

R

> VCC - 0.2V

CE

IN

> VCC - 0.2V o r

V VIN <

IH

= V

CE

(3)

= VIL and CE

(3)

L

and

CE

0.2V, f = 0

(4)

IH

"B"

= V

(5)

IH

SEMR = SEML > VCC - 0.2V

SB4

Full Standb y Current

I

(One Port - All CMOS Level Inputs)

"A"

< 0.2V and

CE CE

"B"

> VCC - 0.2V

(5)

SEMR = SEML > VCC - 0.2V

IN

> VCC - 0.2V or VIN < 0.2V

V Active Port Outputs Open

(3)

MAX

f = f

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

COM' L SL190

MIL & IND

COM' L S

MIL & IND

COM' L

MIL & IND

COM' L

MIL & IND

COM' L

MIL & IND

(VCC = 5.0V ± 10%)

7007X15

Com'l Only

(2)

190

___

S

___

L

L3535

___

S

___

L

SL125

125

___

S

___

L

SL1.0

0.2

___

S

___

L

SL120

120

___

S

___

L

10

0.4

___

Max. Typ.

325 285

220 190

190 160

180 180

___

85 60

___

115 115

___

15

5

0.2

___

110 110

___

7007X20

Com'l Only

(2)

___

30 30

___

1.0

___

2.4

Max. Typ.

315 275

___

85 60

___

210 180

___

15

5

___

185 160

___

5µA

0.4 V

___

7007X25 Com'l &

Military

(2)

Max.

170

305

170

265

170

345

170

305

25 25

105 105

1.0

0.2

1.0

02.

100 100

8560mA

100

80

200

170

230 200

15

5

30 10

175 160

200

175

UnitMin. Max. Min. Max.

V

2940 tbl 08

UnitTyp.

mA

2940 tbl 09

6

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(1,6)

Temperature and Supply Voltage Range

Symbol Parameter Test Condition Version

I

SB1

I

SB2

I

SB3

CC

Dynamic Operating Current (Both Ports Active)

Standby Current (Bo th P orts - TTL Leve l Inp uts)

Standby Current (One Port - TTL Level Inputs)

Full Standby Current (Both Ports - All CMOS Level Inp uts)

CE = V

, Outputs Open

IL

SEM = V

IH

(3)

f = f

MAX

CE

= CER = V

L

SEMR = SEML = V

f = f

MAX

CE

= VIL and CE

"A"

Active Port Outputs Open, f=f

MAX

SEMR = SEML = V

IH

(3)

IH

= V

"B"

IH

Both Ports CEL and

CE

> VCC - 0.2V

R

> VCC - 0.2V or

V

IN

VIN <

0.2 V, f = 0

(4)

SEMR = SEML > VCC - 0.2V

(5)

IH

(con't.) (VCC = 5.0V ± 10%)

COM' L SL160

MIL & IND

COM' L S

MIL & IND

COM' L S

MIL & IND

COM' L SL1.0

MIL & IND

7007X35 Com'l &

Military

(2)

Max. Typ.

295

160

____

S

____

L

20

L

20

____

S

____

L

95

L

95

____

S

____

L

255

335 295

85 60

100

80

185 155

215 185

15

0.2

____

S

____

L

5

30 10

7007X55

Com'l, Ind

& Military

(2)

150 150

20 20

13 13

85 85

1.0

0.2

1.0

0.2

Max.

270 230

310 270

85 60

100

80

165 135

195 165

15

5

30 10

UnitTyp.

mA

I

SB4

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

AC Test Conditions of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

Full Standby Current (One Port - All CMOS Level Inp uts)

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using

CE

< 0.2V and

"A"

CE

> VCC - 0.2V

"B"

(5)

SEMR = SEML > VCC - 0.2V

> VCC - 0.2V or VIN < 0.2V

V

IN

Active Port Outputs Open

(3)

f = f

MAX

COM' L S

MIL & IND

90

L

90

____

S

____

L

160 135

190 165

80

135

80

110

80

165

80

140

mA

2940 t bl 1 0

7

IDT7007S/L

.

High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Test Conditions

Inp ut Pulse Lev els

Inp ut Rise/Fall Times

Inp ut Timing Re ferenc e Le vels

Output Reference Levels

Output Load

GND to 3.0V

5ns Max.

1.5V

Figures 1 and 2

294 0 tbl 11

DATA

OUT

BUSY

INT

347

Ω

5V

893

30pF

2940 drw 05

Ω

Figure 1. AC Output Test Load

AC Electrical Characteristics Over the

7007X15

Com'l Only

____

3

____

0

____

(4,5)

____

15

10

____

10

____

15

____

15

____

Operating Temperature and Supply Voltage Range

READ CYCLE

t

RC Read Cycle Time 15

t

AA Address Access Time

tACE Chip Enable Access Time

t

AOE Output Enable Access Ti me

OH

t

LZ Output Lo w-Z Time

t

HZ Outp ut High-Z Time

Output Hold from Address Change 3

tPU Chip Ena ble to Power Up Time

t

PD Chip Disable to Po wer Down Time

t

SOP Semaphore Flag Update Pulse (

tSAA Semaphore Address Access Time

READ CYCLE

RC Read Cycle Time 35

t

tAA Address Access Time

tACE Chip Enable Access Time

tAOE Output Enable Access Time

tOH Outp ut Hol d fro m Ad dre ss Change 3

tLZ O utp ut L ow-Z Tim e

tHZ Output High-Z Time

tPU Chi p En able to Po wer Up Time

t

PD Chip Dis abl e to Po wer Do wn Time

tSOP Semaphore Flag Update Pulse (OE or

tSAA Semaphore Address Access Time

NOTES:

1. Transition is measured ±200mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. 'X' in part numbers indicates power rating (S or L).

5. Industrial temperature: for other speeds, packages and powers contact your sales office.

(3)

(1,2)

(2)

OE

or

SEM

)10

(3)

(1,2)

(2)

SEM

)15

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

8

OUT

DATA

347

Ω

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

7007X20

Com'l Only

20

3

0

10

7007X35 Com'l &

Military

3

0

____

20

12

____

12

____

20

____

20

____

35

20

____

15

____

35

____

35

7007X25 Com'l

25

____

12

____

55

____

15

____

& Military

3

0

7007X55

Com'l, Ind

& Military

3

0

5V

893

5pF*

2940 drw 06

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

____

25 ns

13 ns

____

15 ns

____

25 ns

____

25 ns

2940 tb l 12a

UnitSymbol Parameter Min.Max.Min.Max.

____

55 ns

30 ns

____

25 ns

____

50 ns

____

55 ns

2940 t bl 12 b

Ω

ns

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

CE

ACE

t

AOE

(4)

OE

R/W

(1)

t

LZ

OUT

DATA

BUSY

OUT

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

3. t

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t

5. SEM = V

IH.

AOE, tACE, tAA or tBDD.

VALID DATA

(3,4)

t

BDD

(4)

t

OH

(2)

t

HZ

2940 drw 07

Timing of Power-Up Power-Down

CE

I I

CC

SB

t

PU

t

PD

2940 drw 08

,

9

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage

Symbol Parameter

WRIT E CYCLE

WC Write Cycle Time 15

t

tEW Chip Enable to End-of-Write

t

AW

Address Valid to End-of-Write 12

tAS Address Set-up Time

tWP Write Pulse Width 12

tWR Write Recovery Time 0

DW Data Valid to End-o f-Write 10

t

tHZ Outp ut Hig h-Z Time

t

DH

Data Ho ld Time

(4)

tWZ Write Enable to Output in High-Z

tOW Output Active from End-of-Write

t

SWRD

t

SPS

SEM

Flag Write to Read Time

Flag Contention Windo w

SEM

Symbol Parameter

WRITE CYCLE

WC Write Cycle Time 35

t

tEW Chip Enable to End-of-Write

t

AW

Address Valid to End-of-Write 30

tAS Address Set-up Time

tWP Write Pulse Width 25

t

WR

Write Rec ov ery Time 0

tDW Data Valid to End-of-Write 15

tHZ Output High-Z Time

t

DH

Data Ho ld Time

(4)

tWZ Write Enable to Output in High-Z

tOW Output Acti ve from End -of-Write

t

SWRD

t

SPS

SEM

Flag Write to Read Tim e

Flag Contention Window

SEM

NOTES:

1. Transition is measured ±200mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. The specification for t

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t

5. 'X' in part numbers indicates power rating (S or L).

6. Industrial temperature: for other speeds, packages and powrs contact your sales office.

(3)

(1,2)

(1, 2 ,4 )

(3)

(1,2)

(1, 2,4 )

DH will always be smaller than the actual tOW.

(5,6)

7007X15

Com'l Only

12

0

____

0

____

0

5

____

10

____

10

____

7007X20

Com'l Only

20

15

0

15

0

15

____

0

____

0

5

7007X35

Com'l Only

30

0

____

0

____

0

5

7007X25 Com'l &

Military

Uni tMin. Max. Min. Max. Min. Max.

____

12

____

12

____

25

20

0

20

0

15

____

0

____

0

5

____

15 ns

____

15 ns

____

2940 tbl 13 a

ns

7007X55 Com'l &

Mil itary

UnitMin. Max. Min. Max.

____

12

____

12

____

55

45

0

40

0

30

____

0

____

0

5

____

25 ns

____

25 ns

____

2940 tbl 13b

ns

10

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

t

WC

(1,5,8)

ADDRESS

(7)

t

HZ

OE

t

AW

CEorSEM

(9)

(3)

t

WR

t

OW

t

DH

DATA

R/

OUT

(6)

AS

t

(2)

t

WP

W

(7)

t

WZ

(4) (4)

t

DW

IN

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

t

WC

ADDRESS

t

AW

R/

DATA

(9)

(6)

t

AS

(2)

t

EW

t

WR

(3)

W

t

DW

IN

t

DH

CEorSEM

2940 drw 09

(1,5)

2940 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

3. t

EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured

+200mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t

placed on the bus for the required t the specified t

WP.

9. To access RAM, CE = V

DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

11

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side

A0-A

SEM

DATA

W

R/

OE

NOTE:

1. CE = V

2

0

IH for the duration of the above timing (both write and read cycle).

VALID ADDRESS

t

AW

t

EW

DATAINVALID

t

AS

t

WP

Write Cycle

t

DW

WR

t

DH

t

SOP

t

SWRD

t

SAA

VALID ADDRESS

t

ACE

t

AOE

t

SOP Read Cycle

DATA

VALID

OUT

t

OH

2940 drw 11

(1)

Timing Waveform of Semaphore Write Contention

0"A"-A2"A"

(2)

SIDE "A"

A

"A"

W

R/

MATCH

(1,3,4)

SEM"A"

SPS

t

0"B"-A2"B"

SIDE

A

(2)

"B"

R/

W

"B"

MATCH

SEM"B"

NOTES:

OR = DOL = VIL, CER = CEL = VIH.

1. D

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W

SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

4. If t

A or SEMA going HIGH to R/WB or SEMB going HIGH.

2940 drw 12

12

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

____

15

18

30

25

(6,7)

7007X20

Com'l Only

____

5

____

15

0

15

____

7007X35 Com'l &

Military

____

5

____

25

0

25

____

20

17

30

45

30

____

7007X25 Com'l &

Military

____

5

____

17

0

17

____

7007X55

Com'l, Ind

& Military

____

20

____

20

____

20

____

20

5

____

35

25

0

25

____

60

____

45

Operating Temperature and Supply Voltage Range

7007X15

Com'l Only

Symbol Parameter

BUSY

TIMING (M/S=VIH)

BAA

t

BDA

t

BAC

t

BDC

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY

t

WB

t

WH

BUSY

Access Time from Address Match

BUSY

Disable Time from Address Not Matched

BUSY

Access Time from Chip Enable Low

BUSY

Access Time from Chip Enable High

BUSY

Disable to Valid Data

TIMING (M/S=VIL)

BUSY

Input to Write

Write Hold After

BUSY

(4)

BUSY

(2)

(3)

(5)

PORT-TO-PORT DELAY TIMI NG

t

WDD Write Pulse to Data Delay

tDDD Write Data Valid to Read Data Del ay

(1)

Symbol Parameter

BUSY

TIMING (M/S=VIH)

t

BAA

t

BDA

BAC

t

BDC

APS Arbitration Priority Set-up Time

t

BDD

WH Write Hold After

t

BUSY

t

WB

t

WH

BUSY

Access Time from Address Match

BUSY

Disable Time from Address Not Matched

BUSY

Access Time from Chip Enable Low

BUSY

Access Time from Chip Enable High

BUSY

Disable to Valid Data

TIMING (M/S=VIL)

BUSY

Input to Write

Write Hold After

BUSY

(2)

(3)

(5)

(4)

(5)

PORT-TO-PORT DELAY TIMI NG

t

WDD Write Pulse to Data Delay

tDDD Write Data Valid to Read Data Del ay

(1)

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of 0, tWDD  tWP (actual) or tDDD  tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

13

____

5

____

12

0

12

____

UnitMin. Max. Min. Max. Min. Max.

20 ns

17 ns

____

30 ns

____

50 ns

35 ns

2940 tb l 14a

45 ns

40 ns

35 ns

____

40 ns

____

80 ns

65 ns

2940 t bl 1 4b

IH)".

ns

UnitMin. Max. Min. Max.

ns

IDT7007S/L

,

High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)

(4)

WC

t

(2,5)

ADDR

DATA

ADDR

DATA

W

R/

IN "A"

BUSY

OUT "B"

"A"

"B"

APS

t

(1)

MATCH

t

WP

DW

t

MATCH

WDD

t

VALID

DDD

t

(3)

NOTES:

1. To ensure that the earlier of the two ports wins. t

L = CER = VIL

2. CE

APS is ignored for M/S = VIL (SLAVE).

3. OE = VIL for the reading port.

4. If M/S = V

IL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

BDA

t

DH

t

BDD

t

VALID

2940 drw 13

Timing Waveform of Write with BUSY (M/S = VIL)

WP

t

"A"

W

R/

WB

t

"B"

BUSY

"B"

R/W

NOTES:

WH must be met for both BUSY input (SLAVE) and output (MASTER).

1. t

2. BUSY is asserted on port "B" blocking R/W

"B", until BUSY"B" goes HIGH.

(2)

t

WH

(1)

2940 drw 14

14

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

(1)

Wavefor m of BUSY Arbitration Controlled by CE Timing

ADDR

and

CE

BUSY

"A" "B"

"A"

"B"

t

APS

(2)

ADDR ESSES MATCH

t

BAC

t

BDC

(M/S = VIH)

2940 drw 15

Wavefor m of BUSY Arbitration Cycle Controlled by Address Match

(1)

Timing

(M/S = VIH)

ADDR

"A"

ADDR

"B"

BUSY

"B"

ADDRESS "N"

(2)

APS

t

MATCHING ADDRESS "N"

t

BAA

t

BDA

2940 drw 16

NOTES:

1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.

APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2. If t

AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range

7007X15

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

AS Address Set-up Time 0

t

tWR Write Recovery Time 0

tINS Interrupt Set Time

tINR Inte rrupt Rese t Time

____

INTERRUPT TIMING

t

AS Address Set-up Time 0

WR Write Recovery Time 0

t

INS Interrup t Set Time

t

INR Interrupt Reset Ti me

t

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. Industrial temperature: for other speeds, packages and powers contact your sales office.

____

15

(1,2)

7007X20

Com'l Only

0

____

7007X35 Com'l &

Military

____

7007X25 Com'l &

Military

7007X55 Com'l, Ind & Military

____

20 ns

2940 tbl 15a

ns

0

20

____

UnitSymbol Parameter Min. Max. Min. Max.

0

25

____

40 ns

2940 tbl 15b

ns

15

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

ADDR

CE

R/

INT

ADDR

CE

W

"A"

"B"

INTE RRUPT SE T ADDRES S

(3)

AS

t

(3)

INS

t

INTERRUPT CLEAR ADDRESS

(3)

AS

t

(1)

t

WC

RC

t

(2)

t

WR

(4)

2940 drw 17

OE

"B"

(3)

INR

t

"B"

INT

NOTES:

1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III  Interrupt Flag

(1)

Left Port Right Port

W

L

CE

L

OE

LLX7FFFXXXX X L

XXXXXXLL7FFFH

XXX X L

X L L 7FFE H

NOTES:

1. Assumes BUSY

2. If BUSY

3. If BUSY

L = BUSYR =VIH.

L = VIL, then no change. R = VIL, then no change.

A14L-A 0L

L

INT

(3)

(2)

R/

W

L

R

CE

R

OE

A14R-A 0R

R

INT

R

(2)

(3)

L L X 7FFE X Se t Left

X X X X X Re se t Le ft

Se t Rig ht

Res et Right

INT

FunctionR/

INT

R Flag

INT

L Flag

2940 drw 18

R Flag

L

Flag

2940 tbl 16

16

IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table IV  Address BUSY Arbitration

Inputs Outputs

14L

AOL-A

14R

CE

L CER

X X NO MATCH H H Normal

H X MATCH H H Normal

X H MATCH H H Normal

L L MATCH (2) (2) Write Inhib it

NOTES:

1. Pins BUSY push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t

3. Writes to the left port are internally ignored when BUSY when BUSY

AOR-A

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are

R outputs are driving LOW regardless of actual logic level on the pin.

(1)

BUSYL

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

BUSYR

(1)

Function

(3)

29 40 tb l 17

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

Truth Table V  Example of Semaphore Procurement Sequence

Functions D0 - D7 Left D0 - D7 Ri ght Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semap hore 0 1 No change. Rig ht side has no write ac ces s to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semap hore 1 0 No change. Left port has no write access to semap hore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.

2. There are eight semaphore flags written to via I/O

3. CE = V

IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.

(1,2,3)

Functional Description

The IDT7007 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location in memory. The IDT7007 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted.

INTERRUPTS

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CE = R/W = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFE

when CE interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFF. The message (8 bits) at 7FFE or 7FFF is userdefined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Table III for the interrupt operation.

Busy Logic

have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is

17

R = OER = VIL, R/W is a "don't care". Likewise, the right port

Busy Logic provides a hardware indication that both ports of the RAM

2940 tbl 18

IDT7007S/L

,

High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT 7007 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.

Width Expansion with Busy Logic Master/Slave Arrays

R E

BUSY

2940 drw 19

D O C E D

(R)

(L)

BUSY

CE

(R)

CE

(R)

MASTER Dual Port RAM

BUSY

MASTER Dual Port RAM

BUSY

(L)

BUSY

Figure 3. Busy and chip enable routing for both width and depth

CE

(L)

expansion with IDT7007 RAMs.

BUSY

(R)

CE

(R)

SLAVE Dual Port RAM

BUSY

SLAVE Dual Port RAM

BUSY

When expanding an IDT7007 RAM array in width while using BUSY

logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7007 RAM the BUSY pin is an output if the part is used as a master (M/S pin = H), and the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.

Semaphores

The IDT7007 is an extremely fast Dual-Port 32K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designers software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH.

Systems which can best use the IDT7007 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7007 hardware semaphores, which provide a lockout mechanism without requiring complex programming.

Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7007 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphores status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing

18

IDT7007S/L

,

High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

a zero into a semaphore latch and is released when the same side writes a one to that latch.

The eight semaphore flags reside within the IDT7007 in a separate

memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0  A2. When accessing the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one sides output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change.

A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other sides semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip

over to the other side as soon as a one is written into the first sides request latch. The second sides flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or

LPORT

SEMAPHORE

REQUEST FLIP FLOP

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT7007 Semaphore Logic

Q

RPORT

0

D

WRITE

SEMAPHORE READ

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the other.

One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.

Using SemaphoresSome Examples

Perhaps the simplest application of semaphores is their application as resource markers for the IDT7007s Dual-Port RAM. Say the 32K x 8 RAM was to be divided into two 16K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory.

To take a resource, in this example the lower 16K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 16K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side.

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IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 16K blocks of Dual-Port RAM with each other.

The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area

was off-limits to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states.

Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.

Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.

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IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

IDT

XXXXX

Device

Type

NOTE:

1. Industrial temperature range is available on selected packages. For other speeds, packages and powers contact your sales office.

A

Power

999

SpeedAPackage

Process/

Temperature

Range

A

Blank

(1)

I B

PF G J

15 20 25 35 55

S L

7007

Commercial (0°Cto+70°C) Industrial (-40°Cto+85°C) Military (-55°Cto+125°C)

Compliantto MIL-PRF-38535 QML

80-pin TQFP (PN 80-1) 68-pin PGA(G68-1) 68-pin PLCC(J68-1)

Commercial Only Commercial Only Commercial & Military Commercial & Military Commercial, Industrial & Military

Standard Power Low Power

256K (32K x 8) Dual-Port RAM

Speed in nanoseconds

2940 drw 21

Datasheet Document History

1/5/99: Initiated datasheet document history

Converted to new format Cosmetic and typographical corrections Pages 2, 3, 4 Added additional notes to pin configurations

6/3/99: Changed drawing format

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613 Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

www.idt.com

21

Datasheet IDT7007L55JI, IDT7007L55PFI, IDT7007S15G, IDT7007L15G, IDT7007L15J Datasheet (Integrated Device Technology Inc)

Specifications and Main Features

Frequently Asked Questions

User Manual