Datasheet IDT7007L35PFB, IDT7007L55G, IDT7007L55GB, IDT7007L55J, IDT7007L55JB Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM

IDT7007S/L

FEATURES:

• True Dual-Ported memory cells which allow simulta­neous access of the same memory location

• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)

• Low-power operation
— IDT7007S

Active: 750mW (typ.)
Standby: 5mW (typ.)

— IDT7007L

Active: 750mW (typ.)
Standby: 1mW (typ.)

• IDT7007 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading

FUNCTIONAL BLOCK DIAGRAM

OE

L

CE

L
L

R/

W

more than one device

•M/S = H for
M/S = L for

BUSY

output flag on Master,

BUSY

input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling
between ports

• Fully asynchronous operation from either port

• Devices are capable of withstanding greater than 2001V
electrostatic discharge

• TTL-compatible, single 5V (±10%) power supply

• Available in 68-pin PGA, 68-pin PLCC, and a 80-pin
TQFP

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

OE

R

CE

R

R/

W

R

I/O0L- I/O

BUSY

(1,2)

L

A

A

14L

0L

7L

Address
Decoder

I/O

Control

MEMORY

ARRAY

15

I/O

Control

Address
Decoder

15

I/O0R-I/O

(1,2)

R

BUSY

A

14R

A

0R

7R

ARBITRATION

CE

L

OE

L

R/

W

L

SEM

L

(2)

INT

L

NOTES:

1. (MASTER):

2.

BUSY

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

and

BUSY

is output; (SLAVE):

INT

outputs are non-tri-stated push-pull.

BUSY

is input.

INTERRUPT

SEMAPHORE

LOGIC

M/

S

CE

OE

R/

R
R

W

R

SEM

R

(2)

INT

2940 drw 01

R

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2940/4

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.08

1

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION:

The IDT7007 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT7007 is designed to be used as a stand-alone
256K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 16-bit-or-more word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in
16-bit or wider memory system applications results in full­speed, error-free operation without the need for additional
discrete logic.

This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in

PIN CONFIGURATIONS

(1,2)

INDEX

1L

I/O

0L

I/O

N/C

L

OE

L

W

R/

L

SEM

memory. An automatic power down feature controlled by
permits the on-chip circuitry of each port to enter a very low
standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 750mW of power.

The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin
PLCC, and a 80-pin TQFP (thin plastic quad flatpack). Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.

L

CE

14L

A

13L

A

CC

V

12L

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

A

CE

I/O
I/O
I/O
I/O
GND
I/O
I/O

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

98765432168676665

2L

10

3L

11

4L

12

5L

13
14

6L

15

7L

16
17
18
19
20
21
22
23
24
25
26

27 28 29 30 31 32 33 34 35 36 37 38 39

R

N/C

OE

R

W

R/

7R

I/O

TOP VIEW

R

R

14R

CE

A

SEM

IDT7007

J68-1

PLCC

13R

A

(3)

12R

A

GND

11R

A

40 41 42 43

9R

10R

A

A

64 63 62 61

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

7R

8R

6R

A

A

A

2940 drw 02

5R

A

A

5L
4L

A
A

3L

A

2L

A

1L

A

0L

INT

L

BUSY

GND
M/

S

BUSY

INT

R

A

0R

A

1R

A

2R

A

3R

A

4R

L

R

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to power supply.

3. This text does not indicate orientation of the actual part marking.

6.08 2

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D.)

0L

1L

I/O

N/C

10
11
12
13
14
15
16
17
18

19

20

I/O

80

78

79

1
2
3
4
5
6
7
8
9

23

21

7R

I/O

22

N/C

R

OE

24

R

W

R/

INDEX

N/C
I/O
I/O
I/O
I/O

GND
I/O
I/O

V

N/C

GND

I/O
I/O
I/O

V
I/O
I/O
I/O
I/O

N/C

2L
3L
4L
5L

6L
7L

CC

0R
1R
2R

CC

3R
4R
5R
6R

(1,2)

L

OE

77

R

SEM

L

W

R/

76

25

L

L

SEM

CE

N/C

74

75

73

TOP VIEW

28

26

27

R

14R

N/C

CE

A

13L

14L

CC

A

A

V

71

70

72

IDT7007

PN80-1

TQFP

30

31

29

13R

12R

GND

A

A

12L

A

69

(3)

32

11R

A

11L

A

68

33

10R

A

10L

A

67

34

9R

A

9L

A

66

35

8R

A

8L

A

36

7R

A

65

7L

A

37

6R

A

64

6L

A

63

38

5R

A

N/C

62

60
59
58

57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

39

N/C

N/C

40

N/C

61

2940 drw 03

N/C
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

L

INT

BUSY

GND
M/

S

BUSY

INT

R

A

0R

A

1R

A

2R

A

3R
4R

A
N/C
N/C

L

R

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to power supply.

3. This text does not indicate orientation of the actual part marking.

6.08 3

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D.)

(1,2)

11

10

09

08

07

06

05

04

03

02

01

51 50 48 46 44 42 40 38 36

M/

A4L A2L A0L A3R

A

5L

525449 39 37

53

A6L

47 45 43 41 34

A3L A1L

INT

L

BUSY

GND

L

BUSY

S

R

55

A9L

A8L

56

57

A11L

A10L

58

59

VCC

A12L

IDT7007

G68-1

60

61

A14L

63

SEM

65

67

I/O0L

68

I/O1L

A13L

62

L

CE

L

64

OE

L

R/

W

L

66

N/C

13579

I/O4L I/O7L

I/O2L

GND GND

2 4 6 8 10 12 14 16

I/O3L

I/O5L

I/O6L

68-PIN PGA

TOP VIEW

I/O

VCC

0R

(3)

11 13 15

I/O1R I/O4R

I/O2R I/O3R I/O5R I/O6R

A

INT

1R

R

35

A4R

A2R

A0RA7L

32

A7R

30

A9R

28
A11R

26
GND

24

A14R

22

SEM

20

OE

A5R

33

A6R

31

A8R

29

A10R

27

A12R

25

A13R

23

R

CE

21

R

R/

18 19

VCC N/C

I/O7R

17

R

W

R

ABCDEFGH J

INDEX

NOTES:

CC pins must be connected to power supply.

1. All V

2. All GND pins must be connected to ground supply.

3. This text does not indicate orientation of the actual part marking.

PIN NAMES

Left Port Right Port Names

CE

L

R/

W

L R/WR Read/Write Enable

OE

L

A

0L – A14L A0R – A14R Address

I/O

0L – I/O7L I/O0R – I/O7R Data Input/Output

SEM

L

INT

L

BUSY

L

CE

R Chip Enable

OE

R Output Enable

SEM

R Semaphore Enable

INT

R Interrupt Flag

BUSY

R Busy Flag

M/

S

V

CC Power

Master or Slave Select

GND Ground

2940 tbl 01

K

L

2940 drw 04

6.08 4

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL

Inputs

CECE

CE

CECE

R/

WW

W

WW

H X X H High-Z Deselected: Power-Down

L L X H DATA
L H L H DATA

X X H X High-Z Outputs Disabled

NOTE: 2940 tbl 02

1. A0L — A14L ≠ A0R — A14R.

(1)

OEOE

OE

OEOE

SEMSEM

SEM

SEMSEM

Outputs

0-7 Mode

I/O

IN Write to Memory

OUT Read Memory

TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL

(1)

Inputs Outputs

CECE

CE

CECE

H H L L DATA
H X L DATA

R/

WW

W

WW

OEOE

OE

OEOE

SEMSEM

SEM

SEMSEM

0-7 Mode

I/O

OUT Read Semaphore Flag Data Out (I/O0-I/O7)

IN Write I/O0 into Semaphore Flag

L X X L — Not Allowed

NOTE: 2940 tbl 03

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

(2)

V

TERM

T

A Operating 0 to +70 –55 to +125 °C

T

BIAS Temperature –55 to +125 –65 to +135 °C

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

Temperature

(1)

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2940 tbl 05

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 2940 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.

2. V

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — 6.0

V
V

IL Input Low Voltage –0.5

NOTES: 2940 tbl 06

1. VIL > -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

CAPACITANCE

(1)

(1)

— 0.8 V

(2)

V

(TA = +25°C, f = 1.0MHz)TQFP ONLY

Symbol Parameter Conditions

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output VOUT = 3dV 10 pF

C

Capacitance

NOTES: 2940 tbl 07

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.

(1)

Max. Unit

6.08 5

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I

OL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = – 4mA 2.4 — 2.4 — V

V

NOTE: 2940 tbl 08

1. At Vcc < 2.0V, input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

(VCC = 5.0V ± 10%)

IDT7007S IDT7007L

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test Com'l. Only

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

SB2 Standby Current

I

(One Port — TTL Active Port Outputs Open, L — — 105 200
Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL. S — — 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 2940 tbl 09

1. "X" in part numbers indicates power rating (S or L).

2. V

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S — — 170 345 mA

SEM

= V

IH L — — 170 305

(3)

MAX

CE

R = CEL = VIH MIL. S — — 25 100 mA

SEM

R =

SEM

L = VIH L— —25 80

(3)

MAX

CE

"A" = VIL and CE"B" = VIH

(3)

MAX

SEM

R =

SEM

L = VIH L 115 180 105 170

CE

R > VCC - 0.2V L — — 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2V and MIL. S — — 100 200 mA

CE

"B" > VCC - 0.2V

R =

SEM

IN ≥ VCC - 0.2V or VIN ≤ 0.2V COM’L. S 110 185 100 275

V

(4)

SEM

L > VCC - 0.2V

SEM

L > VCC - 0.2V

(5)

COM’L. S 180 315 170 305

COM’L. S 30 85 25 85

(5)

MIL. S — — 105 230 mA

COM’L. S 115 210 105 200

Active Port Outputs Open L 110 160 100 230

(3)

MAX

f = f

(1)

(VCC = 5.0V ± 10%)

7007X20 7007X25

(2)

Max. Typ.

L 180 275 170 265

L30 6025 60

L 0.2 5 0.2 5

L — — 100 175

(2)

Max. Unit

6.08 6

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports — TTL
Level Inputs) f = f

I

SB2 Standby Current

(One Port — TTL Active Port Outputs Open, L — 185 85 165
Level Inputs) f = f

I

SB3 Full Standby Current Both Ports CEL and MIL. S — 30 1.0 30 mA

(Both Ports — All
CMOS Level Inputs) V

I

SB4 Full Standby Current

(One Port — All
CMOS Level Inputs)

NOTES:

1. "X" in part numbers indicates power rating (S or L).

CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using

“AC Test Conditions” of input levels of GND to 3V.

CE

= VIL, Outputs Open MIL. S — 335 150 310 mA

SEM

= V

IH L — 295 150 270

(3)

MAX

CE

L = CER = VIH MIL. S — 100 13 100 mA

SEM

R =

SEM

L = VIH L — 80 13 80

(3)

MAX

CE

"A" = VIL and CE"B" = VIH

(3)

MAX

SEM

R =

SEM

L = VIH L 95 155 85 135

CE

R > VCC - 0.2V L — 10 0.2 10

IN > VCC - 0.2V or COM’L. S 1.0 15 1.0 15

V

IN < 0.2V, f = 0

SEM

R =

CE

"A" < 0.2V and MIL. S — 190 80 165 mA

CE

"B" > VCC - 0.2V

R =

SEM

IN > VCC - 0.2V or COM’L. S 90 160 80 135

V

IN < 0.2V L 90 135 80 110

V

(4)

SEM

L > VCC - 0.2V

SEM

L > VCC - 0.2V

(5)

(5)

CE

R > VCC - 0.2V L — 165 80 140

Active Port Outputs Open,

(3)

f = f

MAX

(1)

(Cont'd.) (VCC = 5.0V ± 10%)

7007X35 7007X55

(2)

Max. Typ.

(2)

Max. Unit

COM’L. S 160 295 150 270

L 160 255 150 230

COM’L. S 20 85 13 85

L 20601360

MIL. S — 215 85 195 mA

COM’L. S 95 185 85 165

L 0.2 5 0.2 5

2940 tbl 10

6.08 7

IDT7007S/L

2940 drw 06

893Ω

30pF347Ω

5V

DATA

OUT

BUSY

INT

893Ω

5pF347Ω

5V

DATA

OUT

2940 drw 05

HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2

2940 tbl 11

Figure 1. AC Output Load Figure 2. Output Test Load

(for t
* Including scope and jig.

LZ, tHZ, tWZ, tOW)

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7007X20 IDT7007X25
Com'l. Only

Symbol Parameter Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 20 — 25 — ns

t

AA Address Access Time — 20 — 25 ns

t

(1, 2)

(1, 2)

(3)

(2)

OE

(2)

or

—20 —25ns

3— 3—ns

—12 —15ns

0— 0—ns

—20 —25ns

SEM

)10—12—ns

ACE Chip Enable Access Time

t

AOE Output Enable Access Time — 12 — 13 ns

t
t

OH Output Hold from Address Change 3 — 3 — ns

t

LZ Output Low-Z Time
HZ Output High-Z Time

t
t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time
SOP Semaphore Flag Update Pulse (

t
t

SAA Semaphore Address Access Time — 20 — 25 ns

(4)

IDT7007X35 IDT7007X55

Symbol Parameter Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 35 — 55 — ns

t

AA Address Access Time — 35 — 55 ns

t

ACE Chip Enable Access Time

t
t

AOE Output Enable Access Time — 20 — 30 ns

t

OH Output Hold from Address Change 3 — 3 — ns
LZ Output Low-Z Time

t
t

HZ Output High-Z Time

t

PU Chip Enable to Power Up Time
PD Chip Disable to Power Down Time

t
t

SOP Semaphore Flag Update Pulse (

t

SAA Semaphore Address Access Time — 35 — 55 ns

NOTES: 2940 tbl 12

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. "X" in part numbers indicates power rating (S or L).

IL and

SEM

(3)

(1, 2)

(1, 2)

(2)

(2)

OE

or

SEM

)15—15—ns

= VIH. To access semaphore, CE = VIH and

6.08 8

—35—55ns

3—3—ns

—15—25ns

0—0—ns

—35—50ns

SEM

= VIL.

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF READ CYCLES

(5)

t

RC

ADDR

(4)

t

AA

(4)

t

CE

ACE

t

AOE

(4)

OE

R/

W

t

(1)

t

LZ

DATA

OUT

BUSY

OUT

(3, 4)

t

BDD

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. t

BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY

4. Start of valid data depends on which timing becomes effective last t

5.

has no relation to valid output data.

= V

IH.

SEM

AOE, tACE, tAA, or tBDD.

VALID DATA

(4)

OH

(2)

t

HZ

2940 drw 07

TIMING OF POWER-UP POWER-DOWN

CE

ICC
ISB

tPU

tPD

50% 50%

2940 drw 08

6.08 9

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Symbol Parameter Min. Max Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 20 — 25 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 15 — 20 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 15 — 20 — ns

t

WR Write Recovery Time 0 — 0 — ns

t
t

DW Data Valid to End-of-Write 15 — 15 — ns
HZ Output High-Z Time

t
t

DH Data Hold Time

t

WZ Write Enable to Output in High-Z
OW Output Active from End-of-Write

t
t

SWRD

t

SPS

SEM

Flag Write to Read Time 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — ns

(1, 2)

(4)

(3)

(3)

(1, 2)

(1, 2, 4)

(5)

IDT7007X20 IDT7007X25
Com'l. Only

15 — 20 — ns

0—0—ns

—12—15ns

0—0—ns

—12—15ns

0—0—ns

IDT7007X35 IDT7007X55

Symbol Parameter Min. Max Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 35 — 55 — ns

t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 30 — 45 — ns

t

AS Address Set-up Time

t

WP Write Pulse Width 25 — 40 — ns

t

WR Write Recovery Time 0 — 0 — ns

t
t

DW Data Valid to End-of-Write 15 — 30 — ns
HZ Output High-Z Time

t
t

DH Data Hold Time

t

WZ Write Enable to Output in High-Z
OW Output Active from End-of-Write

t
t

SWRD
SPS

t

NOTES: 2940 tbl 13

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. The specification for t
over voltage and temperature, the actual t

5. "X" in part numbers indicates power rating (S or L).

SEM

Flag Write to Read Time 5 — 5 — ns

SEM

Flag Contention Window 5 — 5 — ns

IL and

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

(1, 2)

(4)

SEM

(3)

(3)

(1, 2)

(1, 2, 4)

= VIH. To access semaphore, CE = VIH and

DH will always be smaller than the actual tOW.

30 — 45 — ns

0—0—ns

—15—25ns

0—0—ns

—15—25ns

0—0—ns

SEM

= VIL. Either condition must be valid for the entire tEW time.

6.08 10

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

t

WC

ADDRESS

OE

t

AW

SEM

R/

W

OUT

(9)

(6)

t

AS

(7)

t

WZ

(4) (4)

IN

t

WP

(2)

CECE

CE

CECE

CE

or

DATA

DATA

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

WW

W

CONTROLLED TIMING

WW

(3)

t

WR

t

OW

t

DW

t

DH

CONTROLLED TIMING

(1,5,8)

(1,5)

(7)

t

HZ

2940 drw 09

t

WC

ADDRESS

t

AW

SEM

R/

W

(9)

(6)

t

AS

IN

EW or tWP) of a LOW

CE

or R/W (or

SEM

LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

DW. If

OE

IL and

WP.

SEM

= VIH. To access semaphore, CE = VIH and

CE

SEM

or R/W) going HIGH to the end of write cycle.

is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

(2)

t

EW

t

DW

and a LOW R/W for memory array writing cycle.

SEM

= VIL. tEW must be met for either condition.

(3)

t

WR

t

DH

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data

CE

or

DATA

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured

Test Load (Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t

to be placed on the bus for the required t
be as short as the specified t

9. To access RAM, CE = V

2940 drw 10

+ 200mV from steady state with the Output

6.08 11

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

t

OH

(2)

2940 drw 11

NOTES:

1.CE = V

2. "DATA

A0-A

2

VALID ADDRESS

t

AW

t

EW

t

WR

SEM

t

DW

DATA

I/O

R/

W

0

t

AS

t

WP

VALID

IN

t

DH

t

SWRD

OE

IH for the duration of the above timing (both write and read cycle).
OUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

t

SAA

VALID ADDRESS

t

ACE

t

SOP

t

AOE

Read CycleWrite Cycle

DATA

VALID

OUT

(1)

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION

A

0"A"-A2"A"

(2)

SIDE "A"

(2)

SIDE

NOTES:

1. D

OR = DOL = VIL, CER = CEL = VIH.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/

SPS is not satisfied there is no guarantee which side will be granted the semaphore flag.

4. If t

"B"

R/

SEM

A

0"B"-A2"B"

R/

SEM

"A" or

W

W

"A"

"A"

W

"B"

"B"

SEM

"A" going HIGH to R/W"B" or

MATCH

MATCH

t

SPS

SEM

"B" going HIGH.

(1,3,4)

2940 drw 12

6.08 12

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY TIMING (M/

WB

t
t

WH Write Hold After

PORT-TO-PORT DELAY TIMING

WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 20 — 20 ns

BUSY

Disable Time from Address Not Matched — 20 — 20 ns

BUSY

Access Time from Chip Enable Low — 20 — 20 ns

BUSY

Disable Time from Chip Enable High — 17 — 17 ns

BUSY

Disable to Valid Data

SS

S

= V

IL)

SS

BUSY

Input to Write

BUSY

(4)

BUSY

(2)

(3)

(5)

(5)

(1)

(1)

5—5—ns

—30—30ns

15 — 17 — ns

0—0—ns

15 — 17 — ns

—45—50ns
—30—35ns

(6)

IDT7007X20 IDT7007X25
Com'l. Only

IDT7007X35 IDT7007X55

Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WH Write Hold After

t

BUSY TIMING (M/

WB

t

WH Write Hold After

t

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 20 — 45 ns

BUSY

Disable Time from Address Not Matched — 20 — 40 ns

BUSY

Access Time from Chip Enable Low — 20 — 40 ns

BUSY

Disable Time from Chip Enable High — 20 — 35 ns

BUSY

Disable to Valid Data

SS

IL)

S

= V

SS

BUSY

Input to Write

BUSY

(4)

BUSY

(2)

(3)

(5)

(5)

5—5—ns
—35—40ns
25 — 25 — ns

0—0—ns
25 — 25 — ns

PORT-TO-PORT DELAY TIMING

t

WDD Write Pulse to Data Delay
DDD Write Data Valid to Read Data Delay

t

NOTES: 2940 tbl 14

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

(1)

(1)

—60—80ns
—45—65ns

BUSY

(M/S = VIH)".

6.08 13

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

t

WC

ADDR

"A"

R/

W

"A"

DATA

IN "A"

(1)

t

APS

ADDR

"B"

"B"

BUSY

DATA

OUT "B"

NOTES:

1. To ensure that the earlier of the two ports wins. t

2.

CE

L = CER = VIL

3.OE = VIL for the reading port.

4. If M/S = V

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

IL (slave),

BUSY

is an input. Then for this example

APS is ignored for M/

MATCH

BUSY

S

= VIL (SLAVE).

"A" = VIH and

t

WP

t

DW

MATCH

t

WDD

BUSY

"B" input is shown above.

VALID

BUSYBUSY

BUSY (M/

BUSYBUSY

(3)

t

DDD

t

BDA

t

DH

SS

S

= VIH)

SS

t

2940 drw 13

(2,4,5)

BDD

VALID

TIMING WAVEFORM OF WRITE WITH BUSY (M/

R/

W

"A"

t

WB

BUSY

"B"

R/

W

"B"

NOTES:

1. t

WH must be met for both

2.

BUSY

3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

is asserted on port "B" blocking R/

BUSY

input (SLAVE) and output (MASTER).

"B", until

W

BUSY

"B" goes High.

SS

S

= VIL)

SS

t

WP

(2)

(3)

t

WH

(1)

2940 drw 14

6.08 14

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

and

CE

CE

BUSY

"A"
"B"

"A"

"B"

"B"

t

APS

(2)

ADDRESSES MATCH

t

BAC

CECE

CE

TIMING (M/

CECE

t

BDC

SS

S

= VIH)

SS

(1)

2940 drw 15

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING

(M/

ADDR

ADDR

SS

S

= VIH)

SS

"A"

"B"

(1)

ADDRESS "N"

(2)

t

APS

MATCHING ADDRESS "N"

t

BAA

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2. If t

t

BDA

2940 drw 16

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7007X20 IDT7007X25
Com'l. Only

Symbol Parameter Min. Max. Min Max. Unit
INTERRUPT TIMING

t

AS Address Set-up Time 0 — 0 — ns
WR Write Recovery Time 0 — 0 — ns

t

INS Interrupt Set Time — 20 — 20 ns

t

INR Interrupt Reset Time — 20 — 20 ns

t

IDT7007X35 IDT7007X55

Symbol Parameter Min. Max. Min Max. Unit
INTERRUPT TIMING

AS Address Set-up Time 0 — 0 — ns

t

WR Write Recovery Time 0 — 0 — ns

t

INS Interrupt Set Time — 25 — 40 ns

t

INR Interrupt Reset Time — 25 — 40 ns

t

NOTE: 2739 tbl 15

1. "X" in part numbers indicates power rating (S or L).

(1)

6.08 15

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF INTERRUPT TIMING

ADDR"A"

CE

"A"

R/

W

INT

ADDR

CE

OE

"A"

"B"

"B"

"B"

"B"

INTERRUPT SET ADDRESS

(3)

tAS

tINS

INTERRUPT CLEAR ADDRESS

(3)

t

AS

(3)

t

INR

(3)

(1)

t

tWC

RC

(2)

(2)

tWR

(4)

2940 drw 17

INT

"B"

2940 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt truth table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG

Left Port Right Port

CECE

WW

CE

L

R/

W

CECE

WW

L L X 7FFF XXXXXL
X X X X X X L L 7FFF H
XXXXL
X L L 7FFE H

NOTES: 2739 tbl 16

1. Assumes

2. If

3. If

4.

INT

BUSY

L = VIL, then no change.

BUSY

R = VIL, then no change.

BUSY

L and

INT

R must be initiated at power-up.

OEOE

OE

L

L =

OEOE

BUSY

L A14L-A0L

R =VIH.

INTINT

INT

INTINT

L R/

(3)
(2)

(1,4)

CECE

WW

CE

W

R

CECE

WW

L L X 7FFE X Set Left

OEOE

OE

R

R A14R-A0R

OEOE

INTINT

INT

R Function

INTINT

(2)

Set Right

(3)

Reset Right

INT

XXXXXReset Left

INT

L Flag

INT

R Flag

INT

L Flag

R Flag

6.08 16

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE II —
ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A14L

A

CECE

CECE

CE

CE

L

CECE

XX
HX
XH
LL

NOTES: 2940 tbl 17

1. Pins
IDT7007 are push-pull, not open drain outputs. On slaves the

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If t
simultaneously.

3. Writes to the left port are internally ignored when
internally ignored when

R A0R-A14R

CECE

BUSY

L and

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs when the part is configured as a master. Both are inputs when configured as a slave.

BUSY

TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE

Functions D0 - D7 Left D0 - D7 Right Status

No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

(1)

BUSYBUSY

BUSY

L

BUSYBUSY

R outputs are driving LOW regardless of actual logic level on the pin.

(1)

BUSYBUSY

BUSY

R

BUSYBUSY

APS is not met, either

BUSY

Function

(3)

input internally inhibits writes.

BUSY

BUSY

L or

BUSY

R = LOW will result.

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are

BUSY

L and

BUSY

outputs on the

BUSY

R outputs can not be LOW

(1,2)

NOTES: 2940 tbl 18

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.

2. There are eight semaphore flags written to via I/O

0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

FUNCTIONAL DESCRIPTION

The IDT7007 provides two ports with separate control,

address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7007 has an
automatic power down feature controlled by CE. The
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location 7FFE (HEX), where a write is
defined as CE = R/W = VIL per the Truth Table. The left port
clears the interrupt through access of address location 7FFE
when

CE

R = OER = VIL, R/

right port interrupt flag (
writes to memory location 7FFF (HEX) and to clear the
interrupt flag (

INT

R), the right port must read the memory

INT

L) is asserted when the right port

W

is a "don't care". Likewise, the

INT

R) is asserted when the left port

location 7FFF. The message (8 bits) at 7FFE or 7FFF is user­defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 7FFE and
7FFF are not used as mail boxes, but as part of the random

CE

access memory. Refer to Truth Table for the interrupt opera­tion.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical

6.08 17

IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the

BUSY

pin operates solely as a write inhibit input pin. Normal opera­tion can be programmed by tying the

BUSY

pins HIGH. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.

The busy outputs on the IDT 7007 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an IDT7007 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a

MASTER
Dual Port
RAM

BUSY

L

MASTER
Dual Port
RAM

BUSY

BUSY

L

Figure 3. Busy and chip enable routing for both width and depth

L

CE

BUSY

R

CE

BUSY

expansion with IDT7007 RAMs.

SLAVE
Dual Port
RAM

BUSY

L

SLAVE
Dual Port
RAM

BUSY

R

L

CE

BUSY

CE

BUSY

R

R

DECODER

BUSY

2940 drw 19

R

write inhibit signal. Thus on the IDT7007 RAM the busy pin is
an output if the part is used as a master (M/S pin = H), and the
busy pin is an input if the part used as a slave (M/S pin = L) as
shown in Figure 3.

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.

SEMAPHORES

The IDT7007 is an extremely fast Dual-Port 16K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor

on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.

The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and

SEM

, the semaphore enable. The CE and

SEM

pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where
and

SEM

are both HIGH.

CE

Systems which can best use the IDT7007 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7007s hardware semaphores, which pro­vide a lockout mechanism without requiring complex pro­gramming.

Software handshaking between processors offers the maxi­mum in system flexibility by permitting shared resources to be
allocated in varying configurations. The IDT7007 does not
use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.

An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore

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IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.

The semaphore flags are active LOW. A token is re­quested by writing a zero into a semaphore latch and is
released when the same side writes a one to that latch.

The eight semaphore flags reside within the IDT7007 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the

SEM

pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica­tions. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side's
semaphore select (

SEM

) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (

SEM

or OE)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the sema­phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.

It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema­phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW
and the other side HIGH. This condition will continue until a
one is written to the same semaphore request latch. Should
the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its

L PORT

SEMAPHORE

REQUEST FLIP FLOP

D

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

REQUEST FLIP FLOP

Q

Figure 4. IDT7007 Semaphore Logic

Q

R PORT

D0

D

WRITE

SEMAPHORE
READ

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semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.

One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.

Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.

USING SEMAPHORES—SOME EXAMPLES

Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7007’s Dual-Port
RAM. Say the 32K x 8 RAM was to be divided into two 16K
x 8 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section

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HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.

To take a resource, in this example the lower 16K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower
16K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 16K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.

Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 16K blocks of Dual-Port RAM with each
other.

The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared

resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.

Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces­sors can access their assigned RAM segments at full speed.

Another application is in the area of complex data struc­tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.

ORDERING INFORMATION

IDT

XXXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank
B

PF
G
J

20
25
35
55

S
L

Commercial (0°C to +70°C)
Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)

Commercial Only

Speed in nanoseconds

Standard Power
Low Power

256K (32K x 8) Dual-Port RAM7007

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