Datasheet IDT7006S Datasheet (Integrated Device Technology)

CMOS Static RAM

I

,

256K (32K x 8-Bit)

IDT71256S

IDT71256L

Features

◆◆

◆

◆◆

High-speed address/chip select time

– Military: 25/35/45/55/70/85/100ns (max.) – Industrial: 25/35ns (max.) – Commercial: 20/25/35ns (max.) low power only

◆◆

◆

◆◆

Low-power operation

◆◆

◆

◆◆

Battery Backup operation – 2V data retention

◆◆

◆

◆◆

Produced with advanced high-performance CMOS technology

◆◆

◆

◆◆

Input and output directly TTL-compatible

◆◆

◆

◆◆

Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC

◆◆

◆

◆◆

Military product compliant to MIL-STD-883, Class B

Functional Block Diagram

Description

The IDT 71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology.

Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to and remain in, a low-power standby mode as long as CS remains HIGH. In the full standby mode, the low-power device consumes less than 15µW, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5µW when operating off a 2V battery.

The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC providing high board level packing densities.

The IDT71256 military RAM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

A

0

ADDRESS DECODER

A

14

/O

0

INPUT

DATA

/O

7

CS

OE

WE

CONTROL

CIRCUIT

262,144 BIT

MEMORY ARRAY

I/O CONTROL

V

CC

GND

2946drw 01

FEBRUARY 2001

1

DSC-2946/9

IDT71256S/L

2

G

,

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Pin Configurations

1

A

14

2

A

12

3

A

7

4

A

6

5

A

5

6 7 8

9 10 11 12 13 14

D28-3 P28-1 D28-1

SO28-5

I/O I/O I/O

ND

A

4

A

3

A

2

A

1

A

0 0 1 2

DIP/SOJ

Top View

28 27 26 25 24 23 22 21 20 19 18 17 16 15

2946 drw 0

V

CC

WE

13

A A

8

A

9

A

11

OE A

10

CS I/O I/O I/O I/O I/O

Truth Table

WE CS OE

X H X High-Z Standby (I XV

HC

H L H High-Z Output Disabled HLLD LLXD

7 6 5 4 3

NOTE:

IH, L = VIL, X = Don't care.

1. H = V

Absolute Maximum Ratings

Symbol Rating Com'l. Ind. Mil. Unit

TERM

V

Te rminal Voltage

(1)

I/O Function

X High-Z Standby (I

OUT

IN

Re ad Data Write Data

(1)

-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V

SB

SB1

)

with Re s p e ct to GN D

INDEX

A

6

A

5

A

4

A

3

A

2

A

1

A

0

NC

0

I/O

2

1

A7A

4

3

5 6

7 8 9

10 11 12 13

14

15

1

2

O

/

I

32-Pin LCC

4

1

A

1,1

A

2

L32-1

16

D N G

1

C N

32 31

C N

C

3

E

C

1

V

W

A

V

A

30

29

A

8

28

A

9

27

A

11

26

NC

25

OE

24

10

A

23

CS

22 21

20191817

3

4

5

O

/

I

7

I/O I/O

8

2946drw03

T

P

I

OUT

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

Operating

A

0 to + 70 -40 to + 85 -55 to + 125oC

Temperature

BIAS

Temperature

-55 to + 125 -55 to +125 -65 to +135oC

Unde r Bias Storage

STG

T

Temperature

Power Dissipation

-55 to + 125 -55 to +125 -65 to +150

1.0 1.0 1.0 W

DC Output Current505050mA

may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Top View

2 9 46 t b l 02

o

C

29 46 tb l 03

Capacitance (TA = +25°C, f = 1.0MHz)

Pin Descriptions

Name Description

0

- A

14

A

0

- I/O

7

I/O

CS

WE

OE

Address Inputs

Data Inp ut/ Outp ut

Chip Se le ct

Write Enable

Output Enable

Symbol Parameter

C

IN

C

I/O

NOTE:

1. This parameter is determined by device characterization, but is not production tested.

Inp ut Cap ac ita nc e VIN = 0V 11 pF I/O Capaci tance V

GND Ground

CC

V

Power

2946 tbl 01

2

(1)

Conditions Max. Unit

OUT

= 0V 11 p F

2946 tbl 04

IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Recommended Operating Temperature and Supply Voltage

Grade Temperature GND Vcc

O

Military -55 Industrial -40 Commercial 0

DC Electrical Characteristics

Symbol Parameter

I

CC

Dynamic Operating Current

VIL, Outputs Ope n

CS <

CC

= Max., f

V

SB

Stand by Po wer Supply Current

I

(TTL Le ve l), CS > Outputs Open, f = f

SB1

Full Standby Power Supply Current

I

(CMOS Le v e l), CS >

CC

= Max. , f = 0

V

C to +1 25OC 0V 5V ± 10%

O

C to +8 5OC 0V 5V ± 10%

O

C to +70OC 0V 5V ± 10%

(1,2)

(2)

MAX

VIH, VCC = Max.,

(2)

MAX

VHC,

Recommended DC Operating Conditions

Symbol Parameter Min. Typ. Max. Unit

CC

Supply Voltage 4.5 5.0 5.5 V

V

GND Ground 0 0 0 V

V

IH

Inp ut Hig h Vol tag e 2 .2

2 9 46 t b l 05

V

IL

Input Low Voltage -0.5

NOTE:

1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

71256S/L20 71256S/L25 71256S/L3 5 712 56S/L45

Power Com'l. Mil. Com'l

& In d

____ ____ ____

S L135 S L3 S L0.4

____

____ ____ ____

____

____ ____ ____

____

Mil. Com'l.

& In d

____

150

11 5 130 105 120

____

20

3333

____

20

0.4 1.5 0.4 1.5

____

(1)

____

6.0 V

0.8 V

Mil. Com'l. Mil.

____

140

20

____

135 115

20 mA

1.5

2946 tb l 06

Unit

mA

3

2946 tbl 07

71256S/L55 71256S/L70 71256S/L85 71256S/L100

Symbol Parameter Power Mil. Mil. Mil. Mil. Unit

CC

I

SB

I

SB1

I

NOTES:

Dynamic Operating Current CS <

VIL, Outputs Open

V

CC

= Max ., f

MAX

(2)

Standby Power Supp ly Current (TTL Lev e l), CS > Ou tputs Open, f = f

VIH, VCC = Max.,

(2)

MAX

Full Standby Power Supply Current (CMOS Le v el ), CS >

CC

= Max. , f = 0

V

VHC,

S 135 135 135 135 mA L 115 115 115 115 S20202020 L3 3 3 3 S20202020 L 1.5 1.5 1.5 1.5

2946 tbl 08

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.

6.42

3

mA

IDT71256S/L

D

,

D

,

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

AC Test Conditions

Inp u t Pu ls e Le v e l s Inp u t Ris e / F al l Ti me s Inp u t Tim in g Re fe re n c e Le v e ls Output Refere nce Lev e ls AC Test Load

GND to 3.0V

5ns

1.5V

See Figures 1 and 2

2 9 46 t b l 09

5V

480Ω

OUT

ATA

255Ω

30pF*

2946drw04

Figure 1. AC Test Load

*Includes scope and jig capacitances

DC Electrical Characteristics (VCC = 5.0V ± 10%)

Symbol Param eter Test Conditions

Input Leakage Current

|I

LI

|

LO

| Output Leakag e Current VCC = Max., CS = VIH,

|I

Output Low Voltage

OL

V

OH

V

Output High Voltage IOH = -4mA, VCC = Min. 2.4

VCC = Max., V

IN =

GND to V

V

OUT

= GND to V

I

OL

= 8mA, VCC = Min.

I

OL

= 10mA, VCC = Min.

MIL.

CC

COM" L & IND. MIL.

COM" L & IND.

CC

____ ____

5V

480Ω

OUT

ATA

255Ω

5pF*

2946drw05

Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

IDT71256S IDT71256L

____ ____

0.4

0.5

____ ____

10

5

10

5

____ ____

2.4

____ ____

0.4

0.5

5 2

UnitMin. Typ. Max. Min. Typ. Max.

µA

V

2946 tbl 10

Data Retention Characteristics Over All Temperature Ranges

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)

(1)

Typ.

VCC @

Symbol Parameter Test Condition Mi n. 2.0V 3.0V 2.0V 3.0V Unit

V

I

CCDR

t

CDR

R

t

DR

VCC for Data Re te ntio n Data Re te nti o n Curre n t MIL.

Chip De s e l e ct to Da ta Retentio n Time

(3)

Operatio n Recovery Time

CS >

____

COM' L. & IND.

V

HC

2.0

____ ____

0

(2)

t

RC

____ ____ ____ ____

____ ____

____ ____ ____ ____

____ ____

NOTES:

1. TA = +25°C.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but is not production tested.

4

500 120

V

Max .

CC

@

800 200

V

µA

ns

2946 tb l 11

IDT71256S/L

DAT

A

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Low VCC Data Retention Waveform

RETENTION

MODE

V

CC

t

CDR

4.5V

DR

≥ 2V

V

t

R

CS

IH

V

DR

V

IH

AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)

Symbol Parameter

Read Cycl e

t

RC

t

AA

ACS

t

CLZ

t t

CHZ

OE

t

OLZ

t t

OHZ

t

OH

Read Cyc le Time 20 Address Access Time Chip Select Acces s Time

(2)

Chip Select to Output in Low-Z 5

(2)

Chip Deselect to Output in High-Z Output Enable to Output Valid

(2)

Output Enabl e to Outp ut in Low-Z 2

(2)

Outp ut Dis ab l e to Ou tpu t in Hi g h-Z 2 8 2 1 0 2 15 Output Hold from A ddre ss Change 5

71256L20

(1)

71256S25 71256L25

Min. Max. Min. Max. Min. Max. Min. Max.

____

20 20

____

10 10

____

25

____

25 25

____

5

11 11

____

2

____

5

71256S35 71256L35

35

____

5

____

2

5

____

71256S45 71256L45

45

____

35

____

35

5

____

15

____

15

0

____

5

2946drw06

(3) (3)

____

45 ns 45 ns

____

20 ns 20 ns

____

20 ns

____

Unit

ns

Write Cycl e

t

WC

t

CW

AW

t t

AS

t

WP

WR

t t

DW

WHZ

t t

DH

OW

t

NOTES:

1. 0° to +70°C temperature range only.

2. This parameter is guaranteed by device characterization, but is not production tested.

3. –55°C to +125°C temperature range only.

Write Cycle Time 20 Chip Select to End-of-Write 15 Address Valid to End-of-Write 15 Address Set-up Time 0 Write Pulse Width 15 Write Recovery Time 0 Data to Write Time Overlap 11

(2)

Write Enab le to Output in High-Z Data Hold from Write Time 0

(2)

Output Active from End-of-Write 5

____

6.42

5

____

25

____

20

____

20

____

0

____

20

____

0

____

13

____

10

____

0

____

5

____

11

____

35

____

30

____

30

____

0

____

30

____

0

____

15

____

0

____

5

45 40 40

35

20

____

ns

____

ns

____

ns

____

0

____

ns ns ns ns

20 ns

____

0 5

____

ns ns

2946 tb l 12

IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

AC Electrical Characteristics (VCC = 5.0V ± 10%, Military Temperature Ranges)

71256S55 71256L55

Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max.

Read Cycl e

t

RC

t

AA

t

ACS

CLZ

t t

CHZ

OE

t

OLZ

t t

OHZ

t

OH

Read Cyc le Time 55 Address Access Time Chip Select Acces s Time

(2)

Chip Select to Output in Low-Z 5

(2)

Chip Deselect to Output in High-Z Output Enable to Output Valid

(2)

Output Enabl e to Outp ut in Low-Z 0

(2)

Outp ut Dis ab l e to Ou tpu t in Hi g h-Z 0 2 5 0 3 0

____

Output Hold from A ddre ss Change 5

Write Cycl e

t

WC

t

CW

t

AW

t

AS

WP

t t

WR

t

DW

WHZ

t

DH

t t

OW

NOTES:

1. -55° to +125°C temperature range only.

2. This parameter is guaranteed by device characterization, but is not production tested.

Write Cycle Time 55 Chip Select to End-of-Write 50 Address Valid to End-of-Write 50 Address Set-up Time 0 Write Pulse Width 40 Write Recovery Time 0 Data to Write Time Overlap 25

(2)

Write Enab le to Output in High-Z

____

Data Hold fro m Write Tim e ( WE)0

(2)

Output Active from End-of-Write 5

____

55 55

____

25 25

____

25

____

(1) (1)

71256S70 71256L70

70

____

70 60 60

45

30

____

(1) (1)

____

70 70

____

5

30 30

____

0

____

5

____

0

____

0

____

30

____

0

____

5

71256S85 71256L85

85

____

85 70 70

50

35

____

(1)

71256S100

(1)

71256L100

____

100

____

85

____

85

____

5

35 35

____

0

35

____

5

____

0

____

0

____

35

____

0

____

5

____

0

____

5

100

80 80

0

55

0

40

____

0 5

(1)

____

100 ns 100 ns

____

40 ns 40 ns

____

40 ns

____

40 ns

____

Unit

ns

ns ns ns ns ns ns ns

ns ns

2946 tb l 13

6

IDT71256S/L

,

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 1

t

RC

(1)

ADDRESS

t

AA

OH

OE

t

OLZ

OE

(5)

t

OHZ

(5)

CS

t

DATA

OUT

t

CLZ

ACS

(5)

t

CHZ

(5)

2946 drw 07

Timing Waveform of Read Cycle No. 2

t

RC

ADDRESS

t

AA

t

OH

OUT

DATA

Timing Waveform of Read Cycle No. 2

CS

t

ACS

(5)

t

CLZ

OUT

DATA

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

(1,2,4)

(1,3,4)

t

OH

2946 drw 08

(5)

t

CHZ

2946 drw 09

6.42

7

IDT71256S/L

t

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)

WC

(1,2,4,6)

ADDRESS

(5)

OHZ

t

OE

t

AW

CS

(6)

WP

t

AS

t

WR

WE

(5)

WZ

DATA

OUT

t

(3)

DW

t

IN

t

OW

(3)

DH

t

2946 drw 10

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)

WC

t

(1,2,4)

ADDRESS

AW

t

CS

(6)

AS

t

CW

t

WR

t

WE

DATA

t

DW

IN

t

DH2

2946 drw 11

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

3. During this period, I/O pins are in the output state so that the input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.

8

IDT71256S/L

I

ds

CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Ordering Information — Commercial & Industrial

71256

DT

Device

Type

X

PowerXXSpeed

XXX

Package

X

Process/

Temperature

Range

Ordering Information — Military

71256

DT

Device

Type

X

XXX

Power Speed

XXX

Package

Process/

Temperature

Range

Blank I

Y P

L Low Power Only

Commercial (0°C to +70°C)

Industrial (-40°C to+85°C)

300 mil SOJ (SO28-5) 600mil PlasticDIP (P28-1)

20

300 mil SOJ Only, Commercial Only

25 35

Speed in nanosecon

,

2946 drw 13

X

B

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

TD D L32

300 mil CERDIP(D28-3) 600 mil CERDIP(D28-1) Leadless Chip Carrier (32-pin) (L32-1)

25 35 45 55

Speed in nanoseconds 70 85 100

6.42

9

S L

Standard Power Low Power

2946 drw 12

IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Datasheet Document History

11/4/99 Updated to new format

Pp. 1–5, 9 Added Industrial Temperature Range offerings Pg. 1 Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings. Pg. 2 Removed P28-2 package from DIP/SOJ Top View Pg. 3 Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table

Revised notes and footnotes

Pg. 5 Removed 30ns speed grade offering from AC Electrical table

Revised notes and footnotes

Pg. 6 Expressed Military Temperature range on AC Electrical table

Revised notes and footnotes Pg. 8 Removed Note 1 and renumbered notes and footnotes Pg. 9 Revised Ordering Information and presented by temperature range offering Pg. 10 Added Datasheet Document History

08/09/00 Not recommended for new designs 02/01/01 Remove "Not recommended for new designs"

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fax: 408-284-2775 www.idt.com

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10