HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Feature s
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆
Low-power operation
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆
IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OE
L
CE
L
R/W
L
IDT7006S/L
◆
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆
Busy and Interrupt Flags
◆
On-chip port arbitration logic
◆
Full on-chip hardware support of semaphore signaling
between ports
◆
Fully asynchronous operation from either port
◆
Devices are capable of withstanding greater than 2001V
electrostatic discharge
◆
Battery backup operation—2V data retention
◆
TTL-compatible, single 5V (±10%) power supply
◆
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speed
◆
Green parts available, see ordering information
OE
R
CE
R
R/W
R
I/O0L-I/O
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2006 Integrated Device Technology, Inc.
BUSY
A
A
SEM
INT
13L
7L
(1,2)
L
Address
0L
L
(2)
L
Decoder
CE
OE
R/W
14
L
L
L
I/O
Control
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
1
I/O
Control
I/O0R-I/O
BUSY
Address
Decoder
14
CE
R
OE
R
R/W
R
A
A
SEM
INT
2739 drw 01
13R
0R
7R
(1,2)
R
R
(2)
R
JANUARY 2006
DSC 2739/15
IDT7006S/L
.
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad
flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade
product is manufactured in compliance with the latest revision of MIL-PRF38535 QML, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
Pin Configurations
L
L
C
W
E
/
/
O
N
R
68 Pin PLCC / Flatpack
R
R
R
R
E
O
E
M
W
/
C
E
R
S
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
L
L
0
1
O
O
/
/
I
I
98765432168676665
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39
R
C
7
/
N
O
/
I
(1,2,3)
L
M
E
S
IDT7006J or F
L
C
E
/
C
N
J68-1
F68-1
TopView
R
C
D
3
/
1
N
N
A
G
L
3
1
A
(4)
(4)
(5)
R
2
1
A
L
L
L
C
2
1
0
L
1
9
A
A
64 63 62 61
40 41 42 43
R
R
R
9
8
7
A
A
A
L
8
A
R
6
A
1
1
C
A
A
V
R
R
1
0
1
1
A
A
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in. x .17 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
L
7
A
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
L
6
A
R
2739 drw 02
5
A
11/06/01
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
BUSY
GND
M/S
BUSY
INT
A
0R
A
1R
A
2R
A
3R
A
4R
L
L
R
R
INDEX
I/O
I/O
I/O
I/O
GND
I/O
I/O
V
GND
I/O
I/O
I/O
V
I/O
I/O
I/O
CC
CC
L
L
1
O
/
I
4
6
1
2L
2
3L
3
4L
4
5L
5
6
6L
7
7L
8
9
10
0R
11
1R
12
2R
13
14
3R
15
4R
5R
7
16
1
R
6
O
/
I
L
L
L
0
E
O
/
O
I
3
2
6
6
L
L
M
W
/
E
S
R
1
6
C
3
E
1
C
A
C
V
0
9
8
5
6
5
7006PF
PN-64
64 Pin TQFP
Top View
0
8
9
2
1
1
R
R
R
7
E
W
/
O
O
/
I
R
3
4
2
1
2
2
2
2
R
R
R
D
3
E
M
E
S
N
1
C
G
A
L
L
L
1
2
1
1
A
A
6
7
5
5
5
5
(4)
(5)
6
5
2
2
R
R
2
1
1
1
A
A
L
L
0
8
9
1
A
A
A
4
3
5
5
9
8
7
2
2
2
R
R
R
9
8
0
1
A
A
A
L
L
L
5
6
7
A
A
A
1
2
5
5
0
3
R
7
A
11/06/01
0
9
5
4
A
A
A
A
A
INT
BUSY
GND
M/S
BUSY
INT
A
A
A
A
A
2739 drw 03
4L
3L
2L
1L
0L
L
L
R
R
0R
1R
2R
3R
4R
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
2
1
33
3
3
R
R
6
5
A
A
2
IDT7006S/L
.
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
(1,2,3)
Pin Configurations
(con't.)
11
10
09
08
07
06
05
04
03
02
53
A
55
A
57
A
59
V
61
N/C
63
SEM
65
OE
67
I/O
68
I/O
51 50 48 46 44 42 40 38 36
BUSY
L
7L
52
A
4L
A
2L
A
INT
0L
L
GND
5L
A
49 39 37
A
6L
47 45 43 41 34
A
3L
A
1L
M/SINT
BUSY
R
R
A
0R
54
9L
A
8L
56
11L
A
10L
58
CC
A
12L
60
A
13L
62
L
CE
L
IDT7006G
G68-1
(4)
68-Pin PGA
Top View
(5)
64
L
R/W
L
66
0L
N/C
13579
1L
I/O
2L
I/O
GND GND
4L
I/O
7L
11 13 15
V
1R
CC
I/O
I/O
A
A
1R
2R
4R
A
3R
35
A
4R
32
A
7R
30
A
9R
28
A
11R
26
GND
24
N/C
22
SEM
R
20
R
OE
18 19
I/O
7R
11/06/01
A
5R
33
A
6R
31
A
8R
29
A
10R
27
A
12R
25
A
13R
23
CE
21
R/W
N/C
R
R
01
I/O
3L
I/O
5L
I/O
6L
ABCDEFGH JKL
INDEX
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
2 4 6 8 10121416
17
0R
I/O
2R
I/O
V
CC
I/O3RI/O
5R
I/O
6R
2739 drw 04
Pin Names
Left Por t Right Por t Names
CE
R/W
OE
0L
A
0L
I/O
SEM
INT
BUSY
L
L
L
- A
L
- I/O
L
L
13L
CE
R
R/W
R
OE
R
A0R - A
13R
7L
I/O0R - I/O
SEM
INT
BUSY
M/S Master or Slave Select
CC
V
GND Ground
7R
R
R
R
Chip E nable
Re ad /Wri te E nab le
Outp ut Enab l e
Address
Data Inp ut/Outp ut
Semaphore Enable
Inte rrup t Flag
Busy Flag
Power
2739 tbl 01
6.42
3
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
T ruth Table I: Non-Contention R ead/Write Control
(1)
Inputs
CE
R/W
OE SEM
H X X H Hig h -Z Des ele c te d: P o wer -Do wn
LLXHDATA
LHLHDATA
X X H X High-Z Outputs Disabled
NOTE:
1. A
0L – A13L is not equal to A0R – A13R
Outputs
I/O
0-7
OUT
IN
Write to Memory
Read Memo ry
Mode
2739 tbl 02
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
R/W
OE SEM
HHLLDATA
H
↑
XLDATA
LXXL
NOTE:
1. There are eight semaphore flags written to via I/O
Absolute Maximum Ratings
Symbol Rating Commercial
(2)
V
TERM
Ter mi na l Vo l t a g e
with Re sp e c t
to GND
T
BIAS
T emperature
Und e r B ia s
T
STG
Storage
T emperature
I
OUT
DC Output
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sec-tions of this specification is not implied. Exposure
to absolute maxi-mum rating conditions for extended periods may affect
reliability.
TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
2. V
maximum, and is limited to
Capacitance
(1)
Symbol Parameter Conditions
IN
C
OUT
C
Inp u t Ca p ac i ta nc e VIN = 3dV 9 pF
Output
Capacitance
NOTES:
1. These parameters are determined by device characterization, but are not
production tested (TQFP Package Only).
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
& Industrial
-0.5 to +7.0 -0.5 to +7.0 V
-55 to +125 - 65 to +13 5oC
-65 to +150 - 65 to +15 0oC
50 50 mA
< 20mA for the period of VTERM < Vcc + 10%.
(TA = +25°C, f = 1.0mhz)
V
Outputs
I/O
0-7
OUT
Read in Semaphore Flag Data Out
IN
Write I/Oo into Semaphore Flag
____
0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
No t A ll o we d
(1)
Military Unit
Recommended DC Operating
Conditions
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supp ly Vo ltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
V
IL
Input Lo w Voltag e -0 .5
NOTES:
1. V
IL > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 10%.
2. V
2739 tbl 04
Maximum Operating Temperature
and Supply Voltage
Grade
Military -55
Commercial 0
(2)
Max. Unit
OUT
= 3dV 10 p F
2739 tbl 05
Industrial 40
NOTES:
1. This is the parameter T
(1)
Mode
(1)
Ambient
Temperature GND Vcc
O
C to +1 25OC0V 5.0V + 10%
O
C to +70OC0V 5.0V + 10%
O
C to +8 5OC0V 5.0V + 10%
A. This is the "instant on" case temperature.
2739 tbl 03
____
(1)
____
(2)
6.0
0.8 V
2739 tbl 06
V
2739 tbl 07
4
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range
Symbol Parameter Test Conditions
|I
LI
| Input Leakage Current
|I
LO
| Outp ut Le ak age Cur rent
V
OL
Output Low Voltage IOL = 4mA
V
OH
Output High Voltage IOH = -4mA 2.4
NOTE:
1. At Vcc
< 2.0V input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to V
CE = V
IH
, V
OUT
= 0V to V
(VCC = 5.0V ± 10%)
7006S 7006L
CC
CC
___
___
___
0.4
2.4
___
___
___
5µA
5µA
0.4 V
___
2739 t bl 08
10
10
___
Data Retention Characteristics Over All Temperature Ranges
(L Version Only)
Symbol Parameter Test Condition Min. Typ.
V
DR VCC
CCDR Data Rete ntio n Current
I
(3)
CDR
t
(3)
R
t
NOTES:
A = +25°C, VCC = 2V, and are not production tested.
1. T
RC = Read Cycle Time
2. t
3. This parameter is guaranteed by characterization, but is not production tested.
fo r Da ta Re tenti o n V CC = 2
Chip Dese le c t to Data Re tentio n Time SEM > VHC 0
Operation Recovery Time tRC
(VLC = 0.2V, VHC = VCC - 0.2V)
V
VHC
CE >
VIN > VHC or < VLC
Mil. & Ind.
Com'l.
2.0
(1)
Max. Unit
___ ___
___
___
(2)
100 4000
100 1500
___ ___
___ ___
2739 t bl 0 9
UnitMin. Max. Min. Max.
V
V
µA
ns
ns
Data Retention Wa veform
V
CC
CE
4.5V
t
CDR
V
IH
DATA RETENTION MODE
VDR> 2V
V
DR
6.42
5
4.5V
t
R
V
IH
2739 drw 05
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range
Symbol Parameter Test Condition Version Typ.
I
CC
Dynamic Op erating
Current
(Both Ports Active)
SB1
Standb y Current
I
(Bo th P o rts - TTL
Leve l Inputs)
I
SB2
Standb y Current
(One Po rt - TTL
Leve l Inputs)
SB3
Full S tand b y Curre nt (B oth
I
Po rts - All CMOS Le v e l
Inputs)
I
SB4
Full Standby Current
(One Po rt - Al l
CMOS Leve l Inp uts)
IL
, Outputs Disabled
CE = V
IH
SEM = V
(3)
f = f
MAX
L
= CER = V
CE
SEMR = SEML = V
f = f
MAX
"A"
CE
Active Po rt Outputs Disable d,
MAX
f=f
SEMR = SEML = V
Both Ports CEL and
R
CE
IN
> VCC - 0.2V o r
V
IN
< 0.2V, f = 0
V
SEMR = SEML > VCC - 0.2V
"A"
CE
"B"
CE
SEMR = SEML > VCC - 0.2V
IN
> VCC - 0.2V o r VIN < 0.2V
V
Active Po rt Outputs Disable d
MAX
f = f
(3)
= VIL and CE
(3)
> VCC - 0. 2V
< 0.2V and
> VCC - 0.2V
(3)
IH
IH
"B"
= V
IH
IH
(4)
(5)
(5)
Symbol Parameter Test Condition Version Typ.
CC
Dynamic Op erating
I
Current
(Both Ports Active)
I
SB1
Standb y Current
(Both Ports - TTL
Leve l Inputs)
I
SB2
Standb y Current
(One P ort - TTL
Leve l Inputs)
I
SB3
Full Standb y Current
(Both Ports - All CMOS
Leve l Inputs)
I
SB4
Full Standb y Current
(One Po rt - A ll CMOS
Leve l Inputs)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
CC = 5V, TA = +25°C, and are not production tested. ICC DC =120ma (typ)
2. V
3. At f = f
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
MAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels
of GND to 3V.
CE = V
IL
, Outputs Disabled
SEM = V
IH
(3)
f = f
MAX
CE
L
= CER = V
SEMR = SEML = V
f = f
MAX
CE
"A"
Active Port Outputs Disabled,
f=f
MAX
SEMR = SEML = V
Both Ports CE
CE
R
V
IN
> VCC - 0.2V or
V
IN
< 0.2 V, f = 0
SEMR = SEML > VCC - 0.2V
CE
"A"
CE
"B"
SEMR = SEML > VCC - 0.2V
V
IN
> VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
= VIL and CE
(3)
L
> VCC - 0.2V
< 0.2V and
> VCC - 0.2V
(3)
IH
and
IH
"B"
= V
IH
IH
(4)
(5)
(5)
COM'L SL170
MIL &
IND
COM'L SL20
MIL &
IND
COM'L SL10595190
MIL &
IND
COM'L SL1.0
MIL &
IND
COM'L SL10090170
MIL &
IND
(1)
(VCC = 5.0V ± 10%)
7006X15
Com'l Only
(2)
Max. Typ.
310
160
260
____
S
L
S
L
____
____
____
60
10
50
____
____
____
____
160
____
S
L
S
L
____
____
____
1551.0
0.2
____
____
____
____
140
____
S
L
____
____
____
COM'L SL150
MIL &
IND
SL150
COM'L SL131060
MIL &
IND
SL131080
COM'L SL8575155
MIL &
IND
S
L
COM'L SL1.0
MIL &
IND
SL1.0
COM'L SL8070135
MIL &
IND
SL8070175
7006X17
Com'l Only
(2)
Max. Typ.
170
310
160
260
____
____
201060
____
____
10595190
1609585
____
____
0.2
____
____
10090170
1409080
____
____
7006X35
Com 'l &
Military
(2)
Max. Typ.
250
140
210
300
140
250
1308575
85
190
75
1608575
0.2
0.2
1108070
1508070
160
150
____
160
____
150
50
____
____
____
____
15
5
____
____
____
____
150
140
150
140
50
65
1551.0
0.2
30101.0
0.23010
7006X20
Com'l, I nd
& Military
(2)
Max. Typ.
201060
201090
9585240
1.0
0.2
1.0
0.23010
9080225
7006X55
Com'l, Ind
& Military
(2)
Max. Typ.
13
10
13
10
290
240
370
320
50
70
180
1509080
2109080
1551.0
155
1308575
2008575
250
210
300
250
60
50
80
65
155
130
190
1608070
15
5
135
110
175
1507565
7006X25
Com' l &
Military
(2)
Max. Unit
155
265
145
220
155
340
145
280
16106050mA
161080
65
170
140
215
180
155mA
0.2
1.0
30
0.2
10
145
120
200
170
2739 t bl 1 0
7006X70
Military
Only
(2)
Max. Unit
____
____
____
____
140
300
130
250
____
____
____
____
10880
65
____
____
____
____
190
160
____
____
____
____
1.0
0.23010
____
____
____
____
175
150
2739 tb l 11
mA
mA
mA
mA
mA
mA
mA
mA
6
IDT7006S/L
,
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC T est Conditions
Inp ut Pul se Le v e ls
Inp ut Ris e/ F all Tim e s
Inp ut Timing R efe re nc e Le ve l s
Outp ut Re fere nc e Le v el s
Outp ut Lo ad
GND to 3.0V
5ns Max.
1.5V
1.5V
Fi g ure s 1 and 2
2739 tbl 12
DATA
OUT
BUSY
INT
775Ω
Figure 1. AC Output Test Load
AC Electrical Oharacteristics Over the
Operating temperature and Supply Voltage Range
7006X15
Com'l Only
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cy cl e Time 15
Address Access Time
Chip Enable Access Time
(3)
Output Enable Access Time
Output Hold from Address Change 3
Out pu t Lo w-Z Ti me
Output Hi gh-Z Time
Chip Enable to Power Up Time
Chi p Dis a ble to P owe r Down Ti m e
(1,2)
(1,2)
(2,5)
(2,5)
Semaphore Flag Update Pulse (OE or SEM)10
Semaphore Address Access Time
____
____
____
____
____
____
____
15
15
10
____
____
3
10
____
0
15
____
15
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time 35
Address Access Time
Chip Enable A cce ss Time
(3)
Output Enable Access Time
Output Hold from Address Change 3
Output Low-Z Time
Output High-Z Time
Chip Enabl e to P o wer Up Time
Chip Disab l e to Powe r Do wn Tim e
(1,2)
(1,2)
(2,5)
(2,5)
Semaphore Flag Update Pulse (OE or SEM)15
Semaphore Address Access Time
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
7006X17
Com'l Only
17
____
____
____
3
3
____
0
____
10
____
7006X35
Com ' l &
Military
____
____
____
3
____
0
____
____
5V
(4)
____
17
17
10
____
____
10
____
17
____
17
____
35
35
20
____
____
15
____
35
____
35
1250Ω
DATA
OUT
30pF
775Ω
Figure 2. Output Test Load
(5pF for t
*Including scope and jig.
7006X20
Com'l,Ind
& Military
20
____
____
____
3
3
____
0
____
10
____
7006X55
Com'l, Ind
& Mil i tary
55
____
____
____
3
3
____
0
____
15
____
Com'l & Mil itary
____
20
20
12
____
____
12
____
20
____
20
____
55
55
30
____
____
25
____
50
____
55
5V
LZ, tHZ, tWZ, tOW)
7006X 25
____
25
____
25 ns
____
25 ns
____
13 ns
____
3
____
3
____
15 ns
____
0
____
25 ns
____
10
____
25 ns
7006X70
Military
Only
____
70
____
____
____
____
3
____
3
____
____
0
____
____
15
____
1250Ω
5pF*
2739 drw 06
UnitSymbol Parameter Min. Max. Min. Max. Min. Max. Min. Max.
ns
ns
ns
ns
ns
2739 tbl 13a
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
ns
70 ns
70 ns
35 ns
ns
ns
30 ns
ns
50 ns
ns
70 ns
2739 tbl 13b
6.42
7
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Wav eform of Read Cyc les
(5)
t
RC
ADDR
(4)
t
AA
(4)
t
ACE
CE
(4)
t
AOE
OE
R/W
DATA
BUSY
OUT
OUT
(1)
t
LZ
VALID DATA
(3,4)
t
BDD
(4)
t
OH
(2)
t
HZ
2739drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
3. t
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
IH.
AOE, tACE, tAA or tBDD.
Timing of Power-Up Power-Down
CE
t
I
CC
I
SB
PU
t
PD
2739 drw 08
,
8
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
____
____
____
____
____
____
____
10
____
____
____
____
(5)
7006X17
Com'l Only
17
12
12
0
12
0
10
____
0
0
5
5
7006X35
Com'l & Military
30
0
____
0
____
0
5
5
Operating Temperature and Supply Voltage
7006X15
Com'l Only
Symbol Parameter
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
t
SWRD
t
SPS
Symbol Parameter
WRITE CYCLE
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
t
SWRD
t
SPS
t
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested but not tested.
3. To access RAM, CE = V
4. The specification for t
and temperature, the actual t
5. 'X' in part numbers indicates power rating (S or L).
Write Cycle Time 15
Chip Enable to End-of-Write
(3)
12
Address Valid to End -of-Write 12
Address Se t-up Time
(3)
0
Write Pulse Width 12
Write Reco v ery Time 0
Data Va li d to E nd - o f-Wri te 10
Output High-Z Time
Data H o ld Ti me
(1,2)
(4)
Write Enable to O utput i n Hig h-Z
Outp ut A c ti v e fro m E nd - o f-Wri te
SEM Flag Write to Read Ti m e
SEM Flag Co nte ntio n Windo w
(1,2)
(1, 2,4)
____
0
____ ____ ____ ____ ____
0
5
5
Write Cycle Time 35
Chip Enable to End-of-Write
(3)
Address Valid to End -of-Write 30
Address Se t-up Time
(3)
Write Pulse Width 25
Write Reco v ery Time 0
Data Va li d to E nd - o f-Wri te 15
Output High-Z Time
Data H o ld Ti me
Write Enable to O utput i n Hig h-Z
Outp ut A c ti v e fro m E nd - o f-Wri te
(1,2)
(4)
(1,2)
(1, 2,4)
SEM Flag Write to Read Ti m e
SEM Flag Co nte ntio n Windo w
IL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
DH will always be smaller than the actual tOW.
7006X20
Com'l, Ind
& Military
7006X25
Com 'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
____
____
____
____
____
____
____
____
____
____
____
20
____
10
15
15
0
15
0
15
0
0
5
5
7006X55
Com'l, Ind
& Military
____
____
____
____
____
____
____
____
12
____
____
12
____
____
____
____
25
____
20
____
20
____
0
____
20
____
0
____
15
ns
ns
ns
ns
ns
ns
ns
15 ns
____
0
ns
15 ns
____
0
____
5
____
5
ns
ns
ns
2739 tbl 14a
7006X70
Military
Only
UnitMin. Max. Min. Max. Min. Max.
____
____
____
____
____
____
____
____
____
____
____
55
45
45
40
30
____
15
____
15
____
____
____
____
0
____
____
0
____
____
25
____
0
____
25
____
0
____
5
____
5
____
70
____
50
____
50
____
0
____
50
____
0
____
40
ns
ns
ns
ns
ns
ns
ns
30 ns
____
0
ns
30 ns
____
0
____
5
____
5
ns
ns
ns
2739 tb l 14b
6.42
9
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Wavef orm of Write Cycle No. 1, R/W Controlled Timing
t
WC
(1,5,8)
ADDRES S
(7)
t
HZ
OE
t
AW
CEorSEM
(9)
(6)
t
AS
t
WP
(2)
(3)
t
WR
R/W
DATA
DATA
OUT
(7)
t
WZ
(4) (4)
t
DW
IN
t
OW
t
DH
Timing Wav eform of Write Cycle No. 2, CE Controlled Timing
t
WC
ADDRESS
t
AW
R/W
DATA
(9)
(6)
t
AS
IN
(2)
t
EW
t
DW
t
WR
(3)
t
DH
CEorSEM
2739 drw 09
(1,5)
2739drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
3. t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
on the bus for the required t
WP.
t
9. To access RAM, CE = V
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
IL and SEM = VIH. To access semaphore CE = VIH and SEM = VIL. tEW must be met for either condition.
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
10
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Wavef orm of Semaphore Read after Write Timing, Either Side
t
SAA
A0-A
SEM
DATA
2
0
VALID ADDRESS
t
AW
t
AS
t
EW
DATAINVALID
t
WP
t
DW
t
WR
VALID ADDRESS
t
SOP
t
DH
R/W
t
SWRD
OE
Write Cycle
t
SOP
Read Cycle
NOTE:
1. CE = V
IH for the duration of the above timing (both write and read cycle).
Timing Wav eform of Semaphore Write Contention
t
ACE
t
AOE
(1,3,4)
DATA
VALID
OUT
t
OH
2739 drw 11
(1)
A
(2)
SIDE “A ”
(2)
SIDE
“B”
0"A"-A2"A"
R/W
SEM
A
0"B"-A2"B"
R/W
SEM
"A"
"A"
"B"
"B"
MATCH
MATCH
t
SPS
2739 drw 12
NOTES:
OR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
1. D
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
4. If t
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
6.42
11
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7006X15
Com'l Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
IH
BUS Y TIMING (M/S=V
t
BAA
BDA
t
BAC
t
BDC
t
t
APS
BDD
t
t
WH
BUSY Acces s Time from Add ress Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Prio rity Set-up Time
BUSY Disable to Valid Data
Write Hold After BUSY
BUS Y TIMING (M/S=V
t
WB
t
WH
BUSY Input to Write
Write Hold After BUSY
PORT-TO-PORT DELAY TIMING
t
WDD
t
DDD
Write Pul se to Data De lay
Wri te D ata Vali d to R e ad D ata De l ay
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMI NG (M/S=V
t
t
t
t
t
t
t
BAA
BDA
BAC
BDC
APS
BDD
WH
BUSY Acces s Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Acce s s Time from Chip En able High
Arb itratio n P rio r ity S e t-up Time
BUSY Disable to Valid Data
Write Hold After BUSY
BUSY TIMI NG (M/S=V
t
WB
t
WH
BUSY Input to Wri te
Write Hold After BUSY
PORT-TO-P ORT DEL AY TIM ING
t
t
WDD
DDD
Write Pulse to Data Delay
Write Data Valid to Re ad Data Del ay
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
3. t
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. 'X' is part numbers indicates power rating (S or L).
.
)
____
15
____
15
____
15
____
15
(2)
(3)
(5)
IL
)
(4)
(5)
(1)
(1)
____
____
____
____
5
18
____
12
____
0
____
12
30
25
7006X3 5 Com' l
IH
)
(2)
(3)
(5)
IL
)
(4)
(5)
(1)
(1)
12
(6)
7006X17
Com'l Only
____
17
____
17
____
17
____
17
____
5
____
18
____
13
____
0
____
13
____
30
____
25
& Mil itary
____
20
____
20
____
20
____
20
____
5
____
35
____
25
____
0
____
25
____
60
____
45
7006X20
Com'l, Ind
& Military
____
____
____
____
5
____
15
0
15
____
____
7006X55
Com'l, Ind
& Military
____
____
____
____
5
____
25
0
25
____
____
20
20
20
____
30
____
____
____
45
35
____
____
____
____
7006X25
Com ' l &
Military
____
20 ns
____
20 ns
____
20 ns
____
17
____
____
____
17 ns
____
5
30 ns
____
17
____
0
____
17
50 ns
35 ns
2739 tb l 15a
7006X70
Military
Only
____
45
40
40
35
40
80
65
____
____
____
____
____
____
45 ns
40 ns
40 ns
35 ns
____
5
45 ns
____
25
____
0
____
25
95 ns
80 ns
2739 tbl 15b
ns
ns
ns
ns
ns
ns
ns
ns
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY
t
WC
ADDR
"A"
R/W
"A"
DATA
IN "A"
(1)
t
APS
ADDR
"B"
"B"
BUSY
DATA
OUT "B"
NOTES:
1. To ensure that the earlier of the two ports wins. t
L = CER = VIL
2. CE
APS is ignored for M/S = VIL (SLAVE).
3. OE = VIL for the reading port.
4. If M/S = V
IL(slave) then BUSY is input (BUSY"A" = VIH) and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right port. Port "A' may be either left or right port. Port "B" is the port opposite from Port "A".
MATCH
t
WP
t
DW
MATCH
t
WDD
VALID
t
DDD
(2,5)
(M/S = VIH)
t
DH
t
BDA
(3)
(4)
t
BDD
VALID
2739 drw 13
Timing Wavef orm of Write with BUSY
R/W
"A"
(3)
t
WB
BUSY
"B"
R/W
"B"
NOTES:
WH must be met for both BUSY input (slave) and output (master).
1. t
2. BUSY is asserted on Port "B", blocking R/W
WB is only for the 'Slave' Version.
3. t
"B", until BUSY"B" goes HIGH.
t
WP
(2)
t
WH
(1)
2739 drw 14
6.42
13
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
(1)
Waveform of BUSY Arbitration Controlled by CE Timing
ADDR
and
CE
CE
BUSY
"A"
"B"
"A"
(2)
t
APS
"B"
"B"
ADDRESSES MATCH
t
BAC
t
BDC
(M/S = VIH)
2739 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
(1)
Timing
(M/S = VIH)
ADDR
"A"
ADDR
"B"
BUSY
"B"
t
APS
ADDRESS"N"
(2)
MATCHINGADDRESS "N"
t
BAA
t
BDA
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
2. If t
AC Electrical Characteristics Over the
Military
____
____
15
15
____
____
25
25
(1)
7006X20
Com'l, Ind
& Mil itar y
0
0
____
____
7006X55
Com 'l, I nd
& Mil itar y
0
0
____
____
____
____
20
20
____
____
40
40
7006X25
Com 'l &
Military
____
0
____
0
____
____
20 ns
20 ns
7006X70
Mili tary Only
____
0
____
0
____
____
50 ns
50 ns
2739 tbl 16a
2739 tbl 16b
Operating Temperature and Supply Voltage Range
7006X15
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
____
____
____
____
15
15
AS
t
t
WR
INS
t
INR
t
Address Set-up Time 0
Write Re c o v ery Tim e 0
Inte rrupt Se t Ti m e
Inter rupt R e s e t Ti me
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
AS
t
t
WR
t
INS
t
INR
Address Set-up Time 0
Write Re c o v ery Tim e 0
Inte rrupt S et Ti m e
Inter rupt R e s e t Ti me
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
7006X17
Com'l Only
0
0
____
____
7006X35
Com'l &
____
____
ns
ns
ns
ns
14
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Wavef orm of Interrupt Timing
ADDR
CE
R/W
INT
ADDR
CE
OE
"A"
"A"
"A"
"B"
"B"
"B"
"B"
(3)
t
AS
t
AS
INTERRUPT SET ADDRESS
(3)
t
INS
INTERRUPT CLEAR ADDRESS
(3)
(3)
t
INR
(1)
t
WC
t
RC
(2)
(4)
t
WR
2739 drw 17
(2)
INT
"B"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Tables
Truth T able III — Interrupt Flag
Left P or t Ri gh t P ort
L
CE
L
OE
LLX3FFFXXXX X L
XXXXXXLL3FFFH
XXX X L
XLL3FFEH
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
R and INTL must be initialized at power-up.
4. INT
L = BUSYR = VIH.
L = VIL, then no change.
R = VIL, then no change.
A
L
13L-A0L
INT
L
(3)
(2)
(1,4)
R/W
R
CE
R
OE
A
R
13R-A0R
INT
R
(2)
(3)
L L X3FFEXSet Left INTL Flag
X X X X X Res e t Le ft INTL Flag
2739drw 18
FunctionR/W
Se t Ri g h t INTR Flag
Res e t Rig h t INTR Flag
2 739 t b l 17
6.42
15
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
T ruth T able IV — Address BUSY Arbitration
Inputs Outputs
AOL-A
13L
AOR-A
CE
L
CE
R
13R
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhi bi t
NOTES:
1. Pins BUSY
push pull, not open drain outputs. On slaves the BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
3. Writes to the left port are internally ignored when BUSY
when BUSY
L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7006 are
R outputs are driving LOW regardless of actual logic level on the pin.
(1)
BUSY
L
APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
(1)
BUSY
R
X input internally inhibits writes.
L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored
Function
(3)
2739 tbl 18
Truth Table V — Example of Semaphore Procurement Sequence
Functions D0 - D7 Left D0 - D
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left po rt has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Rig ht side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Rig ht Port Writes "1" to Semaphore 0 1 Left po rt obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Rig ht Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Rig ht Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left po rt has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2. There are eight semaphore flags written to via I/O
3. CE = V
IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
7
Right Status
(1,2,3)
Functional Description
The IDT7006 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7006 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) where a write is defined as CE = R/W = VIL per the Truth Table .
The left port clears the interrupt by reading address location 3FFE access
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
3FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 3FFF. The message (8 bits) at 3FFE or 3FFF is userdefined, since it is an addressable SRAM location. If the interrupt function
is not used, address locations 3FFE and 3FFF are not used as mail boxes,
but as part of the random access memory. Refer to Truth Table III for the
interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
27 39 tb l 19
16
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
MASTER
Dual Port
RAM
BUSY (L)
MASTER
Dual Port
RAM
BUSY (L)
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs.
BUSY (L) BUSY (R)
CE
BUSY (R)
CE
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 7006 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7006 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT7006 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
SLAVE
Dual Port
RAM
BUSY (L)
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
BUSY (R)
CE
BUSY (R)
2739drw 19
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
SEMAPHORES
The IDT7006 is an extremely fast Dual-Port 16K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7006 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7006s hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7006 does not use its semaphore flags to control
6.42
17
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This pro-cessor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7006 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none
of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7006’s Dual-Port RAM. Say the 16K x 8 RAM
was to be divided into two 8K x 8 blocks which were to be dedicated at any
one time to servicing either the left or right port. Semaphore 0 could be used
18
IDT7006S/L
,
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
to indicate the side which would control the lower section of memory, and
Semaphore 1 could be defined as the indicator for the upper section of
memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
LPORT
SEMAPHORE
REQUESTFLIP FLOP
D
0
D
WRITE
SEMAPHORE
READ
SEMAPHORE
REQUEST FLIP FLOP
Q
Figure 4. IDT7006 Semaphore Logic
Q
RPORT
D
D
SEMAPHORE
READ
0
WRITE
2739 drw 20
6.42
19
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
Device
Type
A
Power
999
SpeedAPackage
A
A
Process/
Temperature
Range
Blank
Commercial (0°Cto+70°C)
(1)
I
Industrial(-40°Cto+85°C)
B
Military (-55°Cto+125°C)
Compliant to MIL-PRF-38535 QML
(2)
G
Green
64-pin TQFP (PN64-1)
PF
68-pin PGA (G68-1)
G
68-pin PLCC (J68-1)
J
68-pin Flatpack (F68-1)
F
Commercial Only
15
Commercial Only
17
Commercial, Industrial & Military
20
Commercial & Military
25
Commercial & Military
35
Commercial, Industrial, & Military
55
Military Only
70
S
StandardPower
L
Low Power
Speed in nanoseconds
,
128K (16K x 8) Dual-Port RAM7006
NOTES:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
01/04/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
06/03/99: Changed drawing format
09/14/99: Page 15 Changed 3FFF to 3FFE in Truth Table III
11/10/99: Replaced IDT logo
12/22/99: Page 1 Corrected drawing error
05/08/00: Page 1 Added copywright info
Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±500mV to 0mV in notes
09/12/01: Page 2 & 3 Added date revision for pin configurations
Page 6 Added Industrial temp to the column heading for 20ns to DC Electrical Characteristics
Pages 7,9,12&14 Added Industrial temp to the column headings for 20ns to AC Electrical Characteristics
Page 7 Table 13a appeared twice, corrected and placed table 13b for 35, 55 & 70ns speeds
Pages 4,6,7,9, Removed Industrial temp note from all tables
12 & 14
Page 20 Added Industrial temp to 20ns in ordering information
01/31/06: Page 1 Added green availability to features
Page 20 Added green indicator to ordering information
2739 drw 21
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
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20
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