Datasheet ICX248AL Datasheet (Sony)

Page 1

Description

The ICX248AL is an interline CCD solid-state image sensor suitable for EIA black-and-white video cameras with a diagonal 8mm (Type 1/2) system. Sensitivity, smear, D-range, S/N and other characteristics from visible light area to near infrared light area, have been greatly improved compared with the ICX038DLA through the adoption of EXview HAD CCDTMtechnology.

This chip features a field period readout system and an electronic shutter with variable charge-storage time.

This chip is compatible with and can replace the ICX038DLA.

Features

• Sensitivity in the near infrared light area

(+12dB compared with the ICX038DLA, λ = 945nm)

• High sensitivity

(+9dB compared with the ICX038DLA, without IR cut filter)

• Low smear (–15dB compared with the ICX038DLA)

• High D range (+2dB compared with the ICX038DLA)

• High S/N

• High resolution and low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)

• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)

• Horizontal register: 5V drive

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 8mm (Type 1/2)

• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels

• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels

• Chip size: 7.95mm (H) × 6.45mm (V)

• Unit cell size: 8.4µm (H) × 9.8µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even fields only)

• Substrate material: Silicon

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ICX248AL

E98728A99

Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA Black-and-White Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

20 pin DIP (Cer-DIP)

Pin 1

Pin 11

Optical black position

(Top View)

∗

EXview HAD CCD is a trademark of Sony Corporation EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of HAD (Hole-Accnmulation Diode) sensor.

AAA AAA AAA

Page 2

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ICX248AL

Pin No. Symbol Description Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

Vφ4 Vφ3 Vφ2

φSUB

GND Vφ1 VL GND VDD VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock GND Vertical register transfer clock Protective transistor bias GND Output circuit supply voltage Signal output

11 12 13 14 15 16 17 18 19 20

VGG VDSUB VSS GND GND RD

φRG

NC Hφ1 Hφ2

Output circuit gate bias Substrate bias circuit supply voltage Output circuit source GND GND Reset drain bias Reset gate clock

Horizontal register transfer clock Horizontal register transfer clock

14 15

Note)

Note) : Photo sensor

GND

Vφ

GND

SUB

Vφ

DSUB

GND

Horizontal Register

Vertical Register

OUT

Hφ

Block Diagram and Pin Configuration

(Top View)

Pin Description

Page 3

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ICX248AL

Item

–0.3 to +50 –0.3 to +18

–55 to +10 –15 to +20

to +10 to +15

to +17 –17 to +17 –10 to +15 –55 to +10

–65 to +0.3 –0.3 to +30

–30 to +80 –10 to +60

V V V V V V V V V V V

V °C °C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Substrate clock φSUB – GND

VDD, VRD, VDSUB, VOUT, VSS – GND

Supply voltage

VDD, VRD, VDSUB, VOUT, VSS – φSUB Vφ1, Vφ2, Vφ3, Vφ4 – GND

Clock input voltage

Vφ1, Vφ2, Vφ3, Vφ4 – φSUB Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Hφ1, Hφ2 – Vφ4

φRG, VGG – GND φRG, VGG – φSUB

VL – φSUB Pins other than GND and φSUB – VL Storage temperature Operating temperature

Page 4

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ICX248AL

Item

VDD VRD VGG VSS VL VDSUB VSUB ∆VSUB

14.55

1.75

6.0 –3

15.0

2.0

∗3 ∗4

15.45

2.25

14.0 +3

V V V

VRD = VDD

∗5 ∗5

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions 2 [when used in substrate bias external adjustment mode]

Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision

∗3

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.)

∗4

Connect to GND or leave open.

∗5

The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode.

VSUB code — one character indication Code and optimal setting correspond to each other as follows.

DC Characteristics

Item

Output circuit supply current IDD 5.0 10.0 mA

Symbol Min. Typ. Max. Unit Remarks

VSUB code Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5

10.0 10.5 11.011.5 12.0 12.5 13.0 13.5 14.0

E f G h J K L m N P Q R S T U V W

<Example> "L" → VSUB = 9.0V

Item

VDD VRD VGG VSS VL VDSUB

φSUB

14.55

1.75

14.55

15.0

2.0

∗1

15.0

∗2

15.45

2.25

15.45

V V V

VRD = VDD

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions 1 [when used in substrate bias internal generation mode]

Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate clock

Grounded with 390Ω resistor

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.)

∗2

Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

Grounded with 390Ω resistor

Page 5

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ICX248AL

Item

Readout clock voltage

VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,

VVL3, VVL4 VφV | VVH1 – VVH2 | VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL VRGL VφRG VRGLH – VRGLL VφSUB

14.55 –0.05

–0.2 –9.6

8.3

–0.25 –0.25

4.75

–0.05

4.5

23.0

15.0 0 0

–9.0

9.0

5.0 0

∗1

5.0

24.0

15.45

0.05

0.05 –8.5

9.65

0.1

0.5

5.25

0.05

5.5

0.8

25.0

V V V

Vp-p

V V V V V V V

Vp-p

V V

Vp-p

1 2 2

2 2

2 2 2 2 2 2 2 3 3 4 4 4 5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling High-level coupling Low-level coupling Low-level coupling

Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage

∗1

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Item Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

∗1

Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications.

Reset gate clock voltage

VRGL VφRG

–0.2

8.509.0

0.2

9.5VVp-p

4 4

Clock Voltage Conditions

Page 6

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ICX248AL

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer clock and GND

CφV1, CφV3 CφV2, CφV4 CφV12, CφV34 CφV23, CφV41 CφH1 CφH2 CφHH CφRG CφSUB R1, R2, R3, R4 RGND

1800 2200

450 270

64 62 47

400

68 15

pF pF pF pF pF pF pF pF pF

Ω Ω

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND

Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor

Symbol Min. Typ. Max. Unit Remarks

Hφ2Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23CφV41

CφV1 CφV2

CφV4 CφV3

RGND

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

Page 7

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ICX248AL

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

VVT

tr twh tf

φM

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

Page 8

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ICX248AL

(3) Horizontal transfer clock waveform

tr twh tf

90%

10%

twl

Vφ

VHL

(4) Reset gate clock waveform

Point A

twl

Vφ

VRGH

VRGL + 0.5V V

RGL

+2.5V

RGLH

RG waveform

RGLL

Hφ1 waveform

twhtr tf

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Page 9

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ICX248AL

(5) Substrate clock waveform

90%

100%

10%

SUB

tr twh tf

φM

VφSUB

Clock Switching Characteristics

Item

Readout clock Vertical transfer

clock

During imaging

During parallelserial conversion

Reset gate clock

Substrate clock

VT V

1, Vφ2,

3, V

Hφ Hφ1

Hφ2

φRG

φSUB

2.3

1.5

2.5

5.38

1.8

5.38

0.5

0.01

0.01 3

0.5

0.01

0.01 3

250

0.5

µs

During readout

∗1

∗2

During drain charge

Symbol

twh

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

twl tr tf

Unit Remarks

∗1

When vertical transfer clock driver CXD1267AN is used.

∗2

tf ≥ tr – 2ns.

Item

Horizontal transfer clock

Hφ1, Hφ2 16 20 ns

∗3

Symbol

two

Min. Typ. Max.

Unit Remarks

∗3

The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

Horizontal

transfer clock

Page 10

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ICX248AL

Image Sensor Characteristics (Ta = 25°C)

Item Sensitivity Saturation signal Smear

Video signal shading

Dark signal Dark signal shading Flicker Lag

S Vsat Sm

Vdt ∆Vdt F Lag

4500 1000

5500

0.00005 0.00018 20 25

2 1 2

0.5

mV mV

% %

% mV mV

1 2 3 4 4 5 6 7 8

∗1

Ta = 60°C

Zone 0 and I

Zone 0 to II' Ta = 60°C Ta = 60°C

Symbol Min. Typ. Max. Unit Measurement method Remarks

Zone Definition of Video Signal Shading

494 (V)

1414

768 (H)

H 8

Effective pixel region

Zone 0, I

Zone II, II'

Ignored region

∗1

Sensitivity data is the conversion value by Measurement method 1.

Page 11

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ICX248AL

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device and connect VDSUB pin to GND or leare it open.)

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the drive circuit example is used.

Definition of standard imaging conditions

1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (IR cut filter is not applicable.)

2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens and the luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (IR cut filter is not applicable.)

1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/500s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula.

2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output.

3. Smear Set to standard imaging condition II. Adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula.

4. Video signal shading Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.

SH = (Vmax – Vmin)/200 × 100 [%]

Sm =

× 100 [%] (1/10V method conversion value)

× ×

200

VSm

500

S = Vs ×

[mV]

500

Page 12

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ICX248AL

5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula.

∆Vdt = Vdmax – Vdmin [mV]

7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula.

F = (∆Vf/200) × 100 [%]

8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula.

Lag = (Vlag/200) × 100 [%]

Vlag (lag)Signal output 200mV

Light

FLD

Strobe light

timing

Output

Page 13

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ICX248AL

15V

XSUB

XV2

XV1

XSG1

XV3

XSG2

XV4

Hφ

Hφ1

0.01

–9V

3.3/16V

100k

1/35V

22/16V

22/20V

CXD1267AN

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

390

47/

6.3V

3.3/20V

0.01

0.01 180k

6.3V

27k

3.9k

CCD OUT

[

∗

100

Hφ

GND

Vss

DSUB

Vφ

SUB

GND

Vφ

GND

OUT

ICX248AL

(BOTTOM VIEW)

Drive Circuit 1 (substrate bias internal generation mode)

Page 14

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ICX248AL

15V

XSUB

XV2

XV1

XSG1

XV3

XSG2

XV4

Hφ

Hφ1

0.01

–9V

3.3/16V

15k

47k

15k

0.1

39k

0.1

270k

27k

56k

0.1

100k

1/35V

22/16V

22/20V

CXD1267AN

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

390

47/

6.3V

3.3/20V 0.01

0.01 180k

6.3V

27k

3.9k

CCD OUT

[

∗

100

Hφ

GND

Vss

DSUB

Vφ

SUB

GND

Vφ

GND

OUT

ICX248AL

(BOTTOM VIEW)

Drive Circuit 2 (substrate bias external adjustment mode)

Page 15

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ICX248AL

Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics)

1000

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

500 600 700 800 900400

Wave Length [nm]

Relative Response

Sensor Readout Clock Timing Chart

unit: µs

Odd Field

Even Field

V1 V2

V3 V4

V1 V2

V3 V4

2.5

2.5 2.5 2.5

1.6

33.5

0.2

Page 16

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ICX248AL

Drive Timing Chart (Vertical Sync)

FLD

BLK

CCD

OUT

520

525

260

265

270

275

280

493

494

1 3 5

2 4 6

1 3 5

2 4 6

494

493

Page 17

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ICX248AL

Drive Timing Chart (Horizontal Sync)

760

768

BLK

SUB

Page 18

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ICX248AL

Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized

air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more

than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.)

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.

Compressive strength

39N

0.9Nm

Upper ceramic

Lower ceramic

29N

Low melting point glass

29N

Shearing strength

Tensile strength Torsional strength

Page 19

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ICX248AL

c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated

voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution.

d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not

to perform the following actions as this may cause cracks.

• Applying repeated bending stress to the outer leads.

• Heating the outer leads for an extended period with a soldering iron.

• Rapidly cooling or heating the package.

• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other

sharp tools.

• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards.

e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-

acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)

5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition

exceeding the normal using condition, consult our company.

b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or

usage in such conditions.

c) This CCD image sensor has sensitivity in the near infrared area. Its focus may not match in the same

condition under visible light /near infrared light because of aberration.

Page 20

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ICX248AL

PACKAGE STRUCTURE

20pin DIP (600mil)

0.7

11.55 3

0.55

9.0

7.55

18.0 ± 0.4

15.1 ± 0.3

15.24

0° to 9°

1.4

0.25

(R0.7)

(1.0)

17.6

φ1.4

(4.0)

(1.7)

3.4 ± 0.3

0.7

14.6

4.0 ± 0.3

1.27

0.46

0.8

0.83

0.4

1.778

0.3

1. “A” is the center of the effective image area.

2. The two points “B” of the package are the horizontal reference.

The point “B'” of the package is the vertical reference.

3. The bottom “C” of the package is the height reference.

4. The center of the effective image area, relative to “B” and “B'” is

(H, V) = (9.0, 7.55) ± 0.15mm.

5. The rotation angle of the effective image area relative to H and V is ± 1°.

6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.

7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.

8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.

9. The notch and the hole on the bottom must not be used for reference of fixing.

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

Cer-DIP

TIN PLATING

42 ALLOY

2.6g

Package Outline Unit: mm