Datasheet ICX205AK Datasheet (Sony)

Page 1

Description

The ICX205AK is a diagonal 8mm (Type 1/2) interline CCD solid-state image sensor with a square pixel array and 1.45M effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of HAD (HoleAccumulation Diode) sensors.

This chip is suitable for applications such as electronic still cameras, PC input cameras, etc.

Features

• Progressive scan allows individual readout of the

image signals from all pixels.

• High horizontal and vertical resolution (both approx.

800TV-lines) still image without a mechanical shutter.

• Supports high frame rate readout mode

(effective 256 lines output, 30 frame/s)

• Square pixel

• Horizontal drive frequency: 14.318MHz

• No voltage adjustments

(reset gate and substrate bias are not adjusted.)

• R, G, B primary color mosaic filters on chip

• High resolution, high color reproductivity,

high sensitivity, low dark current

• Low smear, excellent antiblooming characteristics

• Continuous variable-speed shutter Device Structure

• Interline CCD image sensor

• Image size: Diagonal 8mm (Type 1/2)

• Total number of pixels: 1434 (H) × 1050 (V) approx. 1.50M pixels

• Number of effective pixels: 1392 (H) × 1040 (V) approx. 1.45M pixels

• Number of active pixels: 1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)

• Chip size: 7.60mm (H) × 6.20mm (V)

• Unit cell size: 4.65µm (H) × 4.65µm (V)

• Optical black: Horizontal (H) direction: Front 2 pixels, rear 40 pixels

Vertical (V) direction: Front 8 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 20

Vertical 3

• Substrate material: Silicon

Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

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E98118B99

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

ICX205AK

20 pin DIP (Cer-DIP)

∗

Wfine CCD is a registered trademark of Sony Corporation. Represents a CCD adopting progressive scan, primary color filter and square pixel.

Pin 1

Pin 11

Optical black position

(Top View)

AAA AAA AAA

Page 2

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ICX205AK

Pin No. Symbol Description Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

Vφ1 Vφ2A Vφ2B Vφ3 NC NC GND NC GND VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock

GND

GND Signal output

11 12 13 14 15 16 17 18 19 20

VDD GND φSUB NC CSUB NC VL φRG Hφ1 Hφ2

Supply voltage GND Substrate clock

Substrate bias

∗1

Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock

Pin Description

Note) : Photo sensor

G R

B G

Note)

B G

G R

G R G

Horizontal register

R GG

14 15

Vertical register

OUT

GND

Vφ

GND

φSUB

SUB

φRG

Hφ

...

Block Diagram and Pin Configuration

(Top View)

∗1

DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF.

Page 3

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ICX205AK

Against φSUB

Against GND

Against VL

Between input clock pins

Storage temperature Operating temperature

Absolute Maximum Ratings

–40 to +10

–50 to +15 –50 to +0.3 –40 to +0.3

–25 to

–0.3 to +18

–10 to +18

–10 to +15 –0.3 to +28 –0.3 to +15

to +15 –16 to +16 –16 to +16 –30 to +80 –10 to +60

V V V V V V V V V V V V

V °C °C

VDD, VOUT, φRG – φSUB Vφ2A, Vφ2B – φSUB Vφ1, Vφ3, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Vφ1, Vφ2A, Vφ2B, Vφ3 – GND Hφ1, Hφ2 – GND Vφ2A, Vφ2B – VL Vφ1, Vφ3, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ3

Item Ratings Unit Remarks

∗1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply.

∗1

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ICX205AK

Clock Voltage Conditions

Item

Readout clock voltage

VVT VVH02A VVH1, VVH2A,

VVH2B, VVH3 VVL1, VVL2A,

VVL2B, VVL3 Vφ1, Vφ2A,

Vφ2B, Vφ3 | VVL1 – VVL3 | VVHH VVHL VVLH VVLL VφH VHL VφRG VRGLH – VRGLL VRGL – VRGLm VφSUB

14.55 –0.05

–0.2

–8.4

7.6

4.75

–0.05

3.0

22.15

15.0 0

–8.0

8.0

5.0 0

3.3

23.0

15.45

0.05

–7.6

8.4

0.1

0.9

1.3

1.0

0.9

5.25

0.05

5.5

0.4

0.5

23.85

V V

V V V V V V V V V V

1 2

2 2

2 2 2 2 3 3 4 4 4 5

VVH = VVH02A

VVL = (VVL1 + VVL3)/2

High-level coupling High-level coupling Low-level coupling Low-level coupling

Low-level coupling Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Bias Conditions

Item Supply voltage Protective transistor bias Substrate clock Reset gate clock

VDD VL

φSUB φRG

14.55

15.0

∗1 ∗2 ∗2

15.45 V

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item

Supply current

IDD

5.5

Symbol Min. Typ. Max. Unit Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.

Page 5

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ICX205AK

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer clock and GND

CφV1 CφV2A CφV2B CφV3 CφV12A, CφV2B1 CφV2A3, CφV32B CφV13

CφH1, CφH2 CφHH

CφRG CφSUB R1 R2A, R3 R2B RGND RφH RφRG

2200 1800 6800 3300 1200 1200 2200

100

680

36 56 43 30 15 20

pF pF pF pF pF pF pF

pF pF

Ω Ω Ω Ω Ω Ω

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND

Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND

Vertical transfer clock series resistor

Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor

Symbol Min.

Typ.

Max. Unit Remarks

RφH RφH

Hφ2

Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12A

Vφ2A

Vφ2B Vφ3

CφV32B

CφV2A3CφV2B1

CφV13

CφV1 CφV2A

CφV2B

CφV3

RGND

R2B

R2A

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

Reset gate clock equivalent circuit

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ICX205AK

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

VVT

tr twh tf

φM

Vφ1

Vφ3

Vφ2A, Vφ2B

VVH1

VVHH VVH

VVHL

VVLH

VVL1

VVL01

VVL

VVLL

VVH3

VVHH VVH

VVHL

VVLH

VVL03

VVL

VVLL

VφV1 = VVH1 – VVL01 VφV2A = VVH02A – VVL2A VφV2B = VVH02B – VVL2B VφV3 = VVH3 – VVL03

VVH = VVH02A VVL = (VVL01 + VVL03) / 2 VVL3 = VVL03

VVLH

VVL2A, VVL2B

VVLL

VVL

VVH

VVHH

VVH02A, VVH02B

VVH2A, VVH2B

VVHL

Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.

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ICX205AK

twh tftr

90%

10%

twl

Hφ1

two

Hφ2

VRGL

VRGLL

VRGLH

twl

RGH

RG waveform

VRGLm

VφH

twh tf

Point A

(3) Horizontal transfer clock waveform

(4) Reset gate clock waveform

VφH

VφRG

Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL.

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

90%

100%

10%

SUB

(A bias generated within the CCD)

tr twh tf

φM

VφSUB

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ICX205AK

Readout clock Vertical transfer

clock

During imaging

During parallel-serial conversion

Reset gate clock

Substrate clock

VT Vφ1, Vφ2A,

Vφ2B, Vφ3 Hφ1 Hφ2 Hφ1 Hφ2

φRG

φSUB

2.3

20 20

2.5

25 25

2.2

202025

0.5

10 10

0.01

0.01 3

15 15

0.5

10 10

0.01

0.01 3

450

15 15

0.5

µs ns

µs

During readout

∗1

∗2

During drain charge

Horizontal

transfer clock

Item Symbol

twh twl tr tf

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

Unit Remarks

Horizontal transfer clock

Hφ1, Hφ2

20 ns

Item

Symbol

two

Min. Typ.

Max.

Unit

Remarks

∗1

When vertical transfer clock driver CXD1267AN × 2 is used.

∗2

tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V].

Clock Switching Characteristics

Relative Response

0.2

0.4

0.6

0.8

Wave Length [nm]

400 500 600 700

Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)

Page 9

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ICX205AK

Image Sensor Characteristics (Ta = 25°C)

Item

G sensitivity Sensitivity

comparison Saturation signal

Smear

Video signal shading

Uniformity between video signal channels

Dark signal Dark signal shading Line crawl G Line crawl R Line crawl B Lag

Sg Rr Rb Vsat Sm

SHg

∆Srg ∆Sbg

Vdt ∆Vdt Lcg Lcr Lcb Lag

320

0.4

0.3

450

400

0.55

0.45

0.001

0.7

0.6

0.0025 20 25

8 8

3.8

0.5

% % % %

% mV mV

1 1 1 2 3 4 4 5 5 6 7 8 8 8 9

1/30s accumulation

Ta = 60°C No electronic shutter Zone 0 and I

Zone 0 to II'

Ta = 60°C Ta = 60°C

Symbol

Min. Typ. Max. Unit

Measurement

method

Remarks

Zone Definition of Video Signal Shading

1040 (V)

1616

1392 (H)

H 8

Effective pixel region

Ignored region

Zone 0, I

Zone II, II'

R B

Measurement System

CCD

C.D.S

S/H

AMP

CCD signal output [∗A]

Gr/Gb channel signal output [∗B]

Gr/Gb

S/H

R/B

R/B channel signal output [∗C]

Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.

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ICX205AK

Image Sensor Characteristics Measurement Method

Color coding and readout of this image sensor

The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively.

All pixel signals are output successively in a 1/7.5s period. The R signal and Gr signal lines and the Gb signal and B signal lines are output successively.

Horizontal register

Color Coding Diagram

Page 11

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ICX205AK

Readout modes

The diagram below shows the output methods for the following two readout modes.

OUT

R G

G B

R G

G B

R G

G B

R G

G B

Progressive scan mode

High frame rate readout mode

Note) Blacked out portions in the diagram indicate pixels which are not read out.

Output starts from the line 1 in high frame rate readout mode.

1. Progressive scan mode In this mode, all pixel signals are output in non-interlace format in 1/7.5s. The vertical resolution is approximately 800TV-lines and all pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing.

2. High frame rate readout mode All effective areas are scanned in approximately 1/30s by reading out two out of eight lines (1st and 4th lines, 9th and 12th lines). The vertical resolution is approximately 200TV-lines. This readout mode emphasizes processing speed over vertical resolution.

Page 12

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ICX205AK

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the progressive scan mode, bias and clock voltage conditions.

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb signal output or the R/B signal output of the measurement system.

Definition of standard imaging conditions

1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity.

2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.

1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas.

VG = (VGr + VGb)/2 Sg = VG × 100/30 [mV] Rr = VR/VG Rb = VB/VG

2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs.

3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula.

Sm = Vsm ÷ × × × 100 [%] (1/10V method conversion value)

4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.

SHg = (Grmax – Grmin)/150 × 100 [%]

500

Gra + Gba + Ra + Ba

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ICX205AK

5. Uniformity between video signal channels After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values into the following formulas.

∆Srg = (Rmax – Rmin)/150 × 100 [%] ∆Sbg = (Bmax – Bmin)/150 × 100 [%]

6. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

7. Dark signal shading After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula.

∆Vdt = Vdmax – Vdmin [mV]

8. Line crawl Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula.

Lci = ∆Gli/Gai × 100 [%] (i = r, g, b)

9. Lag Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula.

Lag = (Vlag/150) × 100 [%]

Vlag (lag)Gr signal output 150mV

Light

V2A

Strobe light

Timing

Output

Page 14

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ICX205AK

Drive Circuit

15V

XV1

XV2A

XSG1

XSUB

123456789

18171615141312

CXD1267AN

3456789

18171615141312

22/20V

1/35V

100k

Hφ

φRG

GND

Vφ

GND

OUT

ICX205

(Bottom View)

0.1

22/16V

0.1

2200P

22/20V

0.01

3.9k

CCD OUT

2SK523

100

φSUB C

SUB

–8.0V

XV3

XV2B

XSG2

GND

CXD1267AN

0.1

Page 15

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ICX205AK

XV1

XV2A/XV2B

XV3

V2A/V2B

55.8µs (800 bits)

3.49µs (50 bits)

139ns (2 bits)

XSG1/XSG2

Sensor readout clocks XSG1 and XSG2 are used by composing XV2A and XV2B.

Sensor Readout Clock Timing Chart Progressive Scan Mode

Page 16

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ICX205AK

V2A

55.8µs (800 bits)

139ns (2 bits)

V2B

3.49µs (50 bits)

5.0µs (72 bits)

XV1

XV2A/XV2B

XV3

XSG1

XSG2

Sensor readout clock XSG1 is used by composing XV2A.

5.87µs (84 bits)

14 bits

Sensor Readout Clock Timing Chart High Frame Rate Readout Mode

Page 17

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ICX205AK

1068

1063

1052

1044

1068

1063

V2A

V2B

CCD

OUT

1 2 3 4 5 61 2 3 4 5 6 7 8 10

1 2 3 4 51 2 3 4 5 6 7 8

1040

1040 1039 1038

7 8 9

Drive Timing Chart (Vertical Sync) Progressive Scan Mode

Page 18

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ICX205AK

V2A

V2B

CCD

OUT

1/30s 1/30s

266

267

266

267

265 264 263

262 261 260

1 4 1 4 9 12172025 1 4 1 4 9 1217 20 25 1 4 1 4 9 1217 20 25

1020

1025

1028

1033

1036

1020

1025

1028

1033

1036

Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode

Page 19

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ICX205AK

CLK

Hφ1

Hφ2

RGφ

Vφ1

Vφ2A

Vφ2B

Vφ3

SUB

1790

392

412

430

1 32

240

208

176

Drive Timing Chart (Horizontal Sync) Progressive Scan Mode

Page 20

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ICX205AK

CLK

Hφ1

Hφ2

RGφ

Vφ1

Vφ2A

Vφ2B

Vφ3

SUB

1790

392

412

430

112

1 14

168

Drive Timing Chart (Horizontal Sync) High Frame Rate Readout Mode

Page 21

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ICX205AK

Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized

air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more

than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.)

Compressive strength

39N

0.9Nm

Upper ceramic

Lower ceramic

29N

Low melting point glass

29N

Shearing strength

Tensile strength Torsional strength

Page 22

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ICX205AK

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.

c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated

voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution.

d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not

to perform the following actions as this may cause cracks.

• Applying repeated bending stress to the outer leads.

• Heating the outer leads for an extended period with a soldering iron.

• Rapidly cooling or heating the package.

• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other

sharp tools.

• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards.

e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-

acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)

5) Others

a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high

luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company.

b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or

usage in such conditions.

Page 23

PACKAGE STRUCTURE

20pin DIP (600mil)

0.7

11.55 3

0.55

9.0

7.55

18.0 ± 0.4

15.1 ± 0.3

15.24

0° to 9°

1.4

0.25

(R0.7)

(1.0)

17.6

φ1.4

(4.0)

(1.7)

3.4 ± 0.3

0.7

14.6

4.0 ± 0.3

1.27

0.46

0.8

0.83

0.4

1.778

0.3

1. “A” is the center of the effective image area.

2. The two points “B” of the package are the horizontal reference.

The point “B'” of the package is the vertical reference.

3. The bottom “C” of the package is the height reference.

4. The center of the effective image area, relative to “B” and “B'” is

(H, V) = (9.0, 7.55) ± 0.15mm.

5. The rotation angle of the effective image area relative to H and V is ± 1°.

6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.

7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.

8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.

9. The notch and the hole on the bottom must not be used for reference of fixing.

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

Cer-DIP

TIN PLATING

42 ALLOY

2.6g

– 23 –

ICX205AK

Package Outline Unit: mm