Datasheet ICX082AL Datasheet (Sony)

Description

The ICX082AL is an interline CCD solid-state
image sensor suitable for EIA black-and-white video
cameras with a diagonal 11mm (Type 2/3) system.

High sensitivity and low dark current are achieved
through the adoption of HAD (Hole-Accumulation
Diode) sensors.

This chip features a field period readout system
and an electronic shutter with variable charge­storage time.

Features

• High sensitivity (+6dB compared with the ICX022BL)

• Low smear (–20dB compared with the ICX022BL)

• High resolution, Low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 11mm (Type 2/3)

• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels

• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels

• Chip size: 10.25mm (H) × 8.5mm (V)

• Unit cell size: 11.6µm (H) × 13.5µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

ICX082AL

E95935C99

Diagonal 1 1mm (Type 2/3) CCD Image Sensor for EIA Black-and-White Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

20 pin DIP (Ceramic)

A

A

Pin 1

V

3

40

2

12

Pin 11

H

Optical black position

(Top View)

AAAA
AAAA

– 2 –

ICX082AL

Pin No.

Symbol Description

Description

Pin No.

Symbol

Pin Description

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate (overflow drain)
GND
Vertical register transfer clock
Protective transistor bias

GND
Output amplifier drain power

1
2
3
4
5
6
7
8
9

10

Vφ4
Vφ3
Vφ2
SUB
GND
Vφ1
VL
NC
GND
VDD

11
12
13
14
15
16
17
18
19
20

VOUT
VGG
VSS
GND
RD
RG
VL
Hφ1
Hφ2
HIS

Signal output
Output amplifier gate bias
Output amplifier source
GND
Reset drain
Reset gate clock
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock

Horizontal register input source bias

Block Diagram and Pin Configuration

(Top View)

1

2

3

4

5

6

9

7

10
11
12
13
14

Note)

GND

V

DD

SUB

RG Hφ1

15

16

17

18

19

20

HIS

V

OUT

Vφ4

Vφ3

Vφ2

Vφ1

VL

GND

VGG

VSS

GND

RD Hφ2VL

Vertical Register

Horizontal Register

Note) : Photo sensor

Output Unit

– 3 –

ICX082AL

Item

–0.3 to +55
–0.3 to +20

–55 to +10
–15 to +20

to +10
to +15

to +17
–17 to +17
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Substrate voltage SUB – GND

HIS, VDD, RD, VOUT, VSS – GND
HIS, VDD, RD, VOUT, VSS – SUB
Vertical clock input pins – GND

Vertical clock input pins – SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2, RG, VGG – GND
Hφ1, Hφ2, RG, VGG – SUB
VL – SUB
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL
RG – VL
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL
Storage temperature
Operating temperature

Item

VDD
VRD
VGG

VSS
VSUB

∆VSUB
VRGL
∆VRGL
VL
VHIS

Grounded with

750Ω resistor

V
V
V

V

%

V

%

V
V

VRD = VDD

±5%

∗2

∗2

∗3

VHIS = VDD

Symbol Min.

Unit

Remarks

Bias Conditions

Output amplifier drain voltage
Reset drain voltage
Output amplifier gate voltage

Output amplifier source
Substrate voltage adjustment range

Substrate voltage adjustment precision
Reset gate clock voltage adjustment range
Reset gate clock voltage adjustment precision
Protective transistor bias
Horizontal register input source bias

14.7

14.7

3.8

Typ.

Max.

15.0

15.0

4.2

15.3

15.3

4.6

9

–3

0

–3

–11

14.7

–10.5

15.0

19
+3

3.0
+3

–10

15.3

Supply voltage

Vertical clock input voltage

– 4 –

ICX082AL

∗2

Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to
the indicated voltage. The adjustment precision is ±3%.

VSUB code — one character indication
VRGL code — one character indication ↑ ↑

VRGL code VSUB code

"Code" and optimal setting correspond to each other as follows.

DC Characteristics

<Example> "5K" → VRGL = 2.0V

VSUB = 12.0V

∗3

This must no exceed the VVL voltage of the vertical clock waveform.

∗4

1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are
not tested are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.
However, GND and SUB pins are left open.

∗5

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

Item
Output amplifier drain current
Input current
Input current

IDD
IIN1
IIN2

6

1

10

mA

µA
µA

∗4
∗5

Symbol Min.

Typ. Max.

Unit

Remarks

VRGL code
Optimal setting 0 0.5 1.0 1.5 2.0

2.5

3.0

1 2

3 4 5 6

7

VSUB code
Optimal setting

9.0 9.5

10.0

10.511.0

11.5

12.0

D E

f G h J

K

L m

N P Q R

S T U

V W X Y

Z

12.5

13.013.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

– 5 –

ICX082AL

Item

VVT
VVH1, VVH2,

VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
| VVH1– VVH2 |
VVH3– VVH
VVH4– VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
VRGL
VφSUB

14.5
–0.6

8.9

–0.5
–0.5

6.0

–3.5

6.0
0

27.0

15.0

–9.6

15.5
0

0.2
0
0

0.8

1.0

0.8

0.8

8.0

–3.0

13.0

3.0

32.0

V
V

V
V

V
V
V
V
V
V
V
V
V
V
V
V

1
2

2
2

2
2
2
2
2
2
2
3
3
3
3
4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
V

φ

V = VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

∗1

Readout clock voltage

Vertical transfer clock
voltage

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

∗1

The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the
specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of
the image sensor has not significance.

Reset gate clock
voltage

Item

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

VRGL
VφRG

–0.2

8.5

0

9.0

0.2

9.5

V
V

3
3

– 6 –

ICX082AL

Clock Equivalent Circuit Constant

Item

CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13
CφV24

CφH1, CφH2

CφHH

CφRG

CφSUB
R1, R2, R3, R4

RGND
RφH

2700
2700
2100

900

1000

500

47

58

7

800

22

3

10

pF
pF
pF
pF
pF
pF

pF

pF

pF

pF

Ω
Ω
Ω

Capacitance between horizontal transfer
clock and GND

Capacitance between horizontal transfer
clocks

Capacitance between reset gate clock and
GND

Capacitance between substrate clock and
GND

Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor

Symbol Min. Typ. Max. Unit

Remarks

RφH RφH

Hφ2Hφ1

CφH1

CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23CφV41

CφV13

CφV24

CφV1 CφV2

CφV4 CφV3

RGND

R4

R1

R3

R2

Vertical transfer clock equivalent circuit

Horizontal transfer clock equivalent circuit

Capacitance between vertical transfer
clock and GND

Capacitance between vertical transfer
clocks

– 7 –

ICX082AL

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

Drive Clock Waveform Conditions
(1) Readout clock waveform

(2) Vertical transfer clock waveform

– 8 –

ICX082AL

(3) Horizontal transfer clock waveform · Reset gate clock waveform

tr twh tf

90%

10%

twl

Vφ

H, VφRG

VHL, VRGL

(4) Substrate clock waveform

90%

100%

10%

0%

V

SUB

tr twh tf

φM

φM

2

VφSUB

Clock Switching Characteristics

Item

Readout clock VT

µs

During
readout

During
imaging

During
imaging

During
parallel-serial
conversion

During drain
charge

Symbol

Min.

Typ.

Max.

Unit

Remarks

Vφ3, Vφ4

Vφ1, Vφ2

Vertical transfer
clock

Horizontal
transfer clock

Reset gate
clock

Substrate clock

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

twh

twl tr tf

Hφ

Hφ1
Hφ2

φRG

φSUB

µs

µs

ns

µs
µs

ns

µs

2.3

2.5

62.6

1.3

20

5.38

11

13

1.5 1.8

0.74

62.1

20

5.38

51

0.5

0.1

0.1

15 19

0.01

0.01

2.0

0.5

0.5

0.1

0.1

15 19

0.01

0.01

2.0

0.5

– 9 –

ICX082AL

Image Sensor Characteristics (Ta = 25°C)

Item

Sensitivity
Saturation signal
Smear
Video signal shading
Dark signal
Dark signal shading
Flicker
Lag

S
Vsat
Sm
SH
Vdt
∆Vdt
F
Lag

500
800

700

0.0001 0.0003
25

2
1
5

0.5

mV
mV

%

%
mV
mV

%

%

1
2
3
4
5
6
7
8

Ta = 60°C

Ta = 60°C
Ta = 60°C

Symbol Min.

Typ. Max. Unit

Measurement

method

Remarks

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the substrate voltage and the reget gate clock voltage are set to the values
indicated on the device, and the device drive conditions are at the typical values of the bias and clock
voltage conditions.

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, and the value measured at point [*A] in the

drive circuit example is used.

Definition of standard imaging conditions

1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter
and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity luminous intensity.

2) Standard imaging condition II :
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity

Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following
formula.

S = Vs × [mV]

2. Saturation signal

Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of signal output, 350mV, measure the minimum value of the signal output.

60

250

– 10 –

ICX082AL

Vlag (lag)Signal output 350mV

Light

FLD

V1

Strobe light

timing

Output

3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped
and the charge drain is executed by the electronic shutter at the respective H blankings, measure the
maximum value VSm [mV] of the signal output and substitute the value into the following formula.

4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.

SH = (Vmax – Vmin)/350 × 100 [%]

5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the
device in the light-obstructed state, using the horizontal idle transfer level as a reference.

6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.

∆Vdt = Vdmax – Vdmin [mV]

7. Flicker
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal
output is 350mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then
substitute the value into the following formula.

F = (∆Vf/350) × 100 [%]

8. Lag
Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.

Lag = (Vlag/350) × 100 [%]

Sm =

× 100 [%] (1/10V method conversion value)

× ×

350

VSm

500

1

10

1

– 11 –

ICX082AL

30V

15V

XSUB

–9V

5V

XV1

XSG1

XV2

XV4

XSG2

XV3

–11V

H2

H1

RG

6V

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

1

0.1

0.01

22/20V

3.3/25V

56k

27k

3.3/

16V

270k

15k

15k

47k

3.3/

35V

0.01

1000P

10k

15

15

22k

3.3/35V

2200P

1M

2

3

4

5

6

7

8

9

10

1

11

12

13

1415

16

17

18

19

20

Vφ

4

Vφ

3

Vφ

2

SUB

GND

Vφ

1

V

L

NC

GND

V

DD

HIS

Hφ

2

Hφ

1

V

L

RG

RD

GND

V

SS

V

GG

V

OUT

3.3/16V

39k

3.3/16V

100k

100

CCD OUT

100k

10k

47k

10/10V

0.1

10

10

100k

100k

1/16V

33k

91k

0.1

0.1

0.1

0.1

2.2/16V

CXD1268M

33k

0.01

3.3/25V

3.3/

16V

750

3.3k

ICX082AL (BOTTOM VIEW)

39k

74AC04

[

∗

A]

Drive Circuit

– 12 –

ICX082AL

Spectral Sensitivity Characteristics

(includes lens characteristics, excludes light source characteristics)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0
500 600 700 800 900 1000400

Wave Length [nm]

Relative Response

Sensor Readout Clock Timing Chart

Odd Field

Even Field

V1
V2

V3
V4

V1
V2

V3
V4

2.5

2.5 2.5 2.5

1.6

33.5

0.2

Unit : µs

– 13 –

ICX082AL

FLD

VD

BLK

HD

V1

V2

V3

V4

CCD

OUT

520

525

1

2

3

4

5

10

15

20

260

265

270

275

280

493

494

1 3 5

2 4 6

1 3 5

2 4 6 494

493

2

1

4

3

6

5

2

1

4

3

6

5

Drive Timing Chart (Vertical Sync)

– 14 –

ICX082AL

760

768

1

2

3

5

10

20

30

40

1

2

3

5

10

20

22

1

2

3

1

2

3

10

20

HD

BLK

H1

H2

RG

V1

V2

V3

V4

SUB

Drive Timing Chart (Horizontal Sync)

– 15 –

ICX082AL

Notes on Handling

1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Operate in clean environments (around class 1000 is appropriate).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.

Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity

ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.

5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage
in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical
shocks.

– 16 –

ICX082AL

Package Outline Unit: mm

PACKAGE STRUCTURE

31.0 ± 0.4

27.0 ± 0.3

20

11

1

10

2-φ2.50

+ 0.25

0

1Pin Index

2.54

0.46

1.27

0.3

φ2.00

+ 0.15

0

20.2 ± 0.3

2.00

+ 0.15

0

× 2.5

0° to 9°

20.32

(AT STAND OFF)

0.25

2-

6.0

2-

R3.0

3.2 ± 0.3

1.0

5.5 ± 0.2

13.15

26.00 ± 0.25

0.5

5.0

20pin DIP (800mil)

(Reference Hole)

(Elongated Hole)

V

H

0.35

1. “A” is the center of the effective image sensor area.

2. A straight line “B” which passes through the centers of the reference hole and

the elongated hole is the reference axis of vertical direction.

3. A straight line “C” which passes through the center of the reference hole

at right angles to vertical reference line “B” is the reference axis of horizontal direction.

4. The bottom “D” is the height reference. (Two points are specified.)

5. The center of the effective image area, specified relative to the reference hole

is (H, V) = (13.15, 5.0) ± 0.15mm.

6. The angle of rotation relative to the reference line “B” is less than ± 1°.

7. The height from the bottom “D” to the effective image area is 1.46 ± 0.15mm.

8. Planar orientation of the effective image area relative to the bottom “D” is less than 60µm.

9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5.

D

~

~

C

B

A

M

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

Ceramic

GOLD PLATING

42 ALLOY

5.9g