Page 1
Description
The ICX059CK is an interline CCD solid-state image
sensor suitable for PAL color video cameras.
Compared with the current product ICX059AK,
sensitivity is improved drastically through the adoption
of Super HAD CCD technology. High resolution is
achieved through the use of Ye, Cy, Mg, and G
complementary color mosaic filters.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
Features
• High sensitivity (+3dB at F5.6, +4dB at F1.2 compared with ICX059AK)
• High resolution, low smear and low dark current
• Excellent antiblooming characteristics
• Continuous variable-speed shutter
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Horizontal register: 5V drive
• Reset gate: 5V drive
Device Structure
• Interline CCD image sensor
• Image size: Diagonal 6mm (Type 1/3)
• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
• Number of total pixels: 795 (H) × 596 (V) approx. 470K pixels
• Chip size: 6.00mm (H) × 4.96mm (V)
• Unit cell size: 6.50µm (H) × 6.25µm (V)
• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even field only)
• Substrate material: Silicon
– 1 –
ICX059CK
E95213A99
Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Camera
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
A
A
A
Pin 1
V
3
40
2
12
Pin 9
H
Optical black position
(Top View)
16 pin DIP (Plastic)
∗
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
AAA
AAA
AAA
Page 2
– 2 –
ICX059CK
Substrate voltage SUB – GND
Supply voltage
Vertical clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2, LHφ1, RG, VGG – GND
Hφ1, Hφ2, LHφ1, RG, VGG – SUB
VL – SUB
Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL
RG – VL
VGG, VSS, Hφ1, Hφ2, LHφ1 – VL
Storage temperature
Operating temperature
Block Diagram and Pin Configuration
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
Note)
Note) : Photo sensor
V
OUT
V
SS
V
GG
GND
Vφ
1
Vφ
2
Vφ
3
Vφ
4
V
DD
GND
SUB
V
L
RG
LHφ
1
Hφ
1
Hφ
2
Horizontal register
Cy
Ye
Cy
Ye
Mg
G
Mg G
Cy
Ye
Cy Ye
G Mg G Mg
Cy
Ye Cy Ye
Mg G Mg G
Vertical register
Pin No.
1
2
3
4
5
6
7
8
Vφ4
Vφ3
Vφ2
Vφ1
GND
VGG
VSS
VOUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source
Signal output
9
10
11
12
13
14
15
16
VDD
GND
SUB
VL
RG
LHφ1
Hφ1
Hφ2
Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock
Horizontal register final stage transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
Description
Pin No.
Description
Pin Description
Absolute Maximum Ratings
–0.3 to +55
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
VDD, VOUT, VSS – GND
VDD, VOUT, VSS – SUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND
Vφ1, Vφ2, Vφ3, Vφ4 – SUB
Item Ratings Unit Remarks
∗1
+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Symbol
Page 3
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ICX059CK
Bias Conditions
Item
Output amplifier drain voltage
Output amplifier gate voltage
Output amplifier source
Substrate voltage adjustment range
Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate clock voltage
adjustment
Protective transistor bias
VDD
VGG
VSS
VSUB
∆VSUB
VRGL
∆VRGL
VL
14.55
3.8
9.0
–3
1.0
–3
15.0
4.2
15.45
4.65
18.5
+3
4.0
+3
V
V
V
%
V
%
±5%
∗1
∗1, ∗6
Symbol Min. Typ. Max. Unit Remarks
DC Characteristics
Item
Output amplifier drain current
Input current
Input current
IDD
IIN1
IIN2
5
1
10
mA
µA
µA
∗3
∗4
Symbol Min. Typ. Max. Unit Remarks
Grounded with
820Ω resistor
∗2
∗1
Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value.
The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image
sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the
indicated voltage. Fluctuation range after adjustment is ±3%.
VSUB code one character indication
VRGL code one character indication ↑ ↑
VRGL code VSUB code
Code and optimal setting correspond to each other as follows.
1
VRGL code
Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2
3
4 5
6
7
VSUB code
Optimal setting
9.0 9.5
10.0 10.5 11.0 11.5 12.012.5 13.0 13.5 14.0 14.5 15.0 15.516.0 16.5 17.0 17.5 18.0 18.5
E f G
h J K L
m
N P
Q
R
S
T
U V W X
Y
Z
<Example> “5L” → VRGL = 3.0V
VSUB = 12.0V
∗2
VL setting is the VVL voltage of the vertical transfer clock waveform.
∗3
1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested
are grounded.
2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to RG, LHφ1, Hφ1, Hφ2 and VGG pins, while pins
that are not tested are grounded. However, 15V is applied to SUB pin.
4) Current to VL pin when 30V is applied to Vφ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to VGG, Vss, Hφ1, Hφ2 and LHφ1 pins, while VL pin is grounded.
However, GND and SUB pins are left open.
∗4
Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
Page 4
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ICX059CK
Clock Voltage Conditions
Item
Readout clock voltage
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
| VVH1 – VVH2 |
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH,VφLH
VHL,VLHL
VφRG
VRGLH – VRGLL
VφSUB
14.55
–0.05
–0.2
–9.0
7.8
–0.25
–0.25
4.75
–0.05
4.5
22.5
15.0
0
0
–8.5
8.5
5.0
0
5.0
23.5
15.45
0.05
0.05
–8.0
9.05
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
24.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
5
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
∗5
∗5
∗6
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol Min.
Typ. Max.
Unit
Waveform
diagram
Remarks
∗5
The horizontal final stage transfer clock input pin LHφ1 is connected to the horizontal transfer clock input
pin Hφ1.
∗6
The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.
Item
Symbol
VRGL
VφRG
Min.
Typ.
Max.
Unit
Waveform
diagram
–0.2
8.5
0
9.0
0.2
9.5
V
V
4
4
Remarks
Reset gate clock
voltage
Page 5
– 5 –
ICX059CK
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13
CφV24
CφH1, CφH2
CφHH
CφLH
CφRG
CφSUB
R1, R2, R3, R4
RGND
RφH
1000
560
470
390
180
100
47
51
8
8
270
80
15
15
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between horizontal final
stage transfer clock and GND
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Symbol Min. Typ. Max. Unit Remarks
RφH RφH
Hφ2
Hφ1
CφH1
CφH2
CφHH
Vφ1
CφV12
Vφ2
Vφ4 Vφ3
CφV34
CφV23
CφV41
CφV13
CφV24
CφV1 CφV2
CφV4 CφV3
RGND
R4
R1
R3
R2
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
Page 6
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ICX059CK
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
Vφ1 Vφ3
Vφ2 Vφ4
VVHH
VVH
VVHL
VVHH
VVHL
VVH1
VVL1
VVLH
VVLL
VVL
VVHH
VVH3
VVHL
VVH
VVHH
VVHL
VVL3
VVL
VVLL
VVLH
VVHH VVHH
VVH
VVHL
VVHL
VVH2
VVLH
VVL2
VVLL
VVL
VVHH VVHH
VVHL
VVH4
VVHL
VVH
VVL
VVLH
VVLL
VVL4
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II II
100%
90%
10%
0%
VVT
tr twh tf
φM
0V
φM
2
Page 7
– 7 –
ICX059CK
tr twh tf
90%
10%
twl
Vφ
H
VHL
(3) Horizontal transfer clock waveform
Point A
twl
VφRG
VRGH
VRGL + 0.5V
V
RGL
2.5V
V
RGLH
RG waveform
V
RGLL
LHφ1 waveform
twhtr tf
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Page 8
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ICX059CK
Clock Switching Characteristics
Note) Because the horizontal final stage transfer clock LHφ1 is connected to the horizontal transfer clock Hφ1,
specifications will be the same as Hφ1.
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
VT
Vφ1, Vφ2,
Vφ3, Vφ4
H
φ1, LHφ1
H
φ
2
H
φ1, LHφ1
H
φ
2
φ
RG
φ
SUB
2.3
18
21
11
1.5
2.5
24
26
6.41
13
1.8
19.51926
24
6.41
51
0.5
10
10
0.01
0.01
3
17.5
15
0.5
15
0.5
10
10
0.01
0.01
3
250
17.5
15
0.5
µs
ns
ns
µs
ns
µs
During
readout
∗1
∗2
During
drain charge
Symbol
twh
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min. Typ.
Max.
twl tr tf
Unit Remarks
∗1
When vertical transfer clock driver CXD1267AN is used.
∗2
tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 · LHφ1 rising side of the Hφ1 · LHφ1 and Hφ2
waveforms must be at least 2.5V.
Horizontal
transfer clock
During
imaging
During
parallel-serial
conversion
Item
Horizontal transfer clock
Hφ1 · LHφ1, Hφ2
16 20 ns
∗3
Symbol
two
Min. Typ. Max.
Unit Remarks
∗3
The overlap period for twh and twl of horizontal transfer clocks Hφ1 · LHφ1 and Hφ2 is two.
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr twh tf
φM
φM
2
VφSUB
Page 9
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ICX059CK
Image Sensor Characteristics (Ta = 25°C)
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Uniformity between video
signal channels
Dark signal
Dark signal shading
Flicker Y
Flicker R-Y
Flicker B-Y
Line crawl R
Line crawl G
Line crawl B
Line crawl W
Lag
S
Ysat
Sm
SHy
∆Sr
∆Sb
Ydt
∆Ydt
Fy
Fcr
Fcb
Lcr
Lcg
Lcb
Lcw
Lag
360
540
460
0.002 0.007
20
25
10
10
2
1
2
5
5
3
3
3
3
0.5
mV
mV
%
%
%
%
%
mV
mV
%
%
%
%
%
%
%
%
1
2
3
4
4
5
5
6
7
8
8
8
9
9
9
9
10
Ta = 60°C
Zone 0, I
Zone 0 to II'
Ta = 60°C
Ta = 60°C
Symbol Min. Typ. Max. Unit Measurement method Remarks
Zone Definition of Video Signal Shading
6
8
582 (V)
12
12
752 (H)
V
10
H
8
H
8
V
10
Effective pixel region
Ignored region
Zone 0, I
Zone II, II'
Measurement System
CCD C.D.S
LPF1
LPF2
AMP
CCD signal output
Y signal output
Chroma signal output
(3dB down 6.3MHz)
(3dB down 1MHz)
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y] and between [∗A] and [∗C] equal 1.
[∗A]
[∗Y]
[∗C]
S/H
S/H
Page 10
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ICX059CK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values
indicated on the device, and the device drive conditions are at the typical values of the bias and clock
voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
Cy Ye
G
Mg
Cy Ye
G
Mg
Cy Ye
G
Mg
Cy Ye
G
Mg
A1
A2
B
Hreg
Color Coding Diagram
Page 11
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ICX059CK
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys × [mV]
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 × 100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.
∆Sr = | (Crmax – Crmin)/200 | × 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
Sm =
× 100 [%] (1/10V method conversion value)
× ×
200
YSm
500
1
10
1
50
250
Page 12
– 12 –
ICX059CK
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal
output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.
Fy = (∆Yf/200) × 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.
Fci = (∆Ci/CAi) × 100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200) × 100 [%]
Ylag (lag)Y signal output 200mV
Light
FLD
SG1
Strobe light
timing
Output
Page 13
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ICX059CK
7
15V
5V
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
Hφ2Hφ1
RG
10k
100k
10/16V
0.1
47k
2SA1175
0.01
CCD OUT
–8.5V
3.3/16V
47/6.3V
820
100
3.9k
2SK523
39k 100k
1/6.3V
1M2200p
0.01
3.3/20V
100k
1/35V
22/16V
22/20V
CXD1267AN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1 2 3 4 5 6 8
16 15 14 13 12 11 10 9
Hφ
2
Hφ
1
LHφ
1
RG
V
L
SUB
GND
V
DD
Vφ
4
Vφ
3
Vφ
2
Vφ
1
GND
V
GG
V
SS
V
OUT
[
∗
A]
VSUB
0.1
0.1
0.1
0.1
ICX059
(BOTTOM VIEW)
Drive Circuit
Page 14
– 14 –
ICX059CK
Spectral Sensitivity Characteristics
(Includes lens characteristics, excludes light source characteristics)
Wave Length [nm]
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Relative Response
400
600
450
650
500
700550
Cy
G
Mg
Ye
Sensor Readout Clock Timing Chart
Unit : µs
Odd Field
Even Field
HD
V1
V2
V3
V4
V1
V2
V3
V4
2.5 2.5 2.5
1.6
0.2
41.6
2.5
Page 15
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ICX059CK
FLD
VD
BLK
HD
SG1
SG2
V1
V2
V3
V4
CCD
OUT
CLP1
620
625
1
2
3
4
5
15
20
25
310
320
335
330
340
581
582
1 3 5
2 4 6
1 3 5
2 4 6
582
581
2
1
4
3
6
5
10
315
325
2
1
4
3
6
5
Drive Timing Chart (Vertical Sync)
Page 16
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ICX059CK
745
750
1
3
5
10
20
30
40
1
2
3
5
10
20
22
1
2
3
1
2
3
10
20
HD
BLK
H1/LH1
H2
RG
SHP
SHD
V1
V2
V3
V4
CLP1
SUB
752
Drive Timing Chart (Horizontal Sync)
Page 17
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ICX059CK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
Compressive strength
50N
Cover glass
Plastic package
50N
1.2Nm
Torsional strength
Page 18
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ICX059CK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
Page 19
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ICX059CK
Package Outline Unit: mm
PACKAGE STRUCTURE
0.3
16pin DIP (450mil)
H
V
2.5
2.5
8.4
0.5
1.2
5.7
6.1
10.3
12.2 ± 0.1
9.5
11.4 ± 0.1
11.43
0.25
0° to 9°
8
1
16
9
2-R0.5
2.5
11.6
9.2
2.5
1.2
3.35 ± 0.15
3.1
1.27
3.5 ± 0.3
0.46
0.3
1.27
0.69
(For the first pin only)
1. “A” is the center of the effective image area.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (6.1, 5.7) ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
C
B
A
D
M
B'
~
~
~
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
Plastic
GOLD PLATING
42 ALLOY
0.9g
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