Datasheet ICX039DNB Datasheet (Sony)

Page 1

Description

The ICX039DNB is an interline CCD solid-state image sensor suitable for PAL color video cameras with a diagonal 8mm (Type 1/2) system. Smear, sensitivity, D-range, S/N and other characteristics have been greatly improved compared with the ICX039BNB. High sensitivity and low dark current are achieved through the adoption of Ye, Cy, Mg and G complementary color mosaic filters and HAD (Hole-Accumulation Diode) sensors.

This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package.

This chip is compatible with and can replace the ICX039BNB.

Features

• Low smear (–20dB compared with the ICX039BNB)

• High sensitivity (+3.0dB compared with the ICX039BNB)

• High D range (+2.5dB compared with the ICX039BNB)

• High S/N

• High resolution and low dark current

• Excellent antiblooming characteristics

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

• Continuous variable-speed shutter

• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)

• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)

• Horizontal register: 5V drive

• Maximum package dimensions: φ13.2mm

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 8mm (Type 1/2)

• Number of effective pixels: 752 (H) x 582 (V) approx. 440K pixels

• Total number of pixels: 795 (H) x 596 (V) approx. 470K pixels

• Chip size: 7.95mm (H) x 6.45mm (V)

• Unit cell size: 8.6µm (H) x 8.3µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction : Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

ICX039DNB

E96128C99

Diagonal 8mm (T ype 1/2) CCD Image Sensor for PAL Color Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

16 pin DIP (Ceramic)

Pin 1

Pin 9

Optical black position

(Top View)

AAA AAA AAA

Page 2

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ICX039DNB

Pin No. Symbol Description Pin No. Symbol Description

1 2 3 4 5 6 7 8

Vφ4 Vφ3 Vφ2

φSUB

Vφ1 VL VDD VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock Vertical register transfer clock Protective transistor bias Output circuit supply voltage Signal output

9 10 11 12 13 14 15 16

VGG VSS GND RD

φRG

VDSUB Hφ1 Hφ2

Output circuit gate bias Output circuit source GND Reset drain bias Reset gate clock Substrate bias circuit supply voltage Horizontal register transfer clock Horizontal register transfer clock

Note)

Note) : Photo sensor

Horizontal Register

Vertical Register

Vφ

SUB

Vφ

OUT

DSUB

GND

Hφ

14 15

Cy Mg Cy

G Cy Mg

Ye Mg Ye

Cy Mg Cy

G Cy Mg

Ye Mg Ye

Block Diagram and Pin Configuration

(Top View)

Pin Description

Page 3

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ICX039DNB

Item

–0.3 to +50 –0.3 to +18

–55 to +10 –15 to +20

to +10 to +15

to +17 –17 to +17 –10 to +15 –55 to +10

–65 to +0.3 –0.3 to +30

–30 to +80 –10 to +60

V V V V V V V V V V V

V °C °C

∗

Ratings Unit Remarks

Absolute Maximum Ratings

∗

1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Substrate clock φSUB – GND

VDD, VRD, VDSUB, VOUT, VSS – GND

Supply voltage

VDD, VRD, VDSUB, VOUT, VSS – φSUB Vφ1, Vφ2, Vφ3, Vφ4 – GND

Clock input voltage

Vφ1, Vφ2, Vφ3, Vφ4 – φSUB Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Hφ1, Hφ2 – Vφ4

φRG, VGG – GND φRG, VGG – φSUB

VL – φSUB Pins other than GND and φSUB – VL Storage temperature Operating temperature

Page 4

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ICX039DNB

Item

VDD VRD VGG VSS VL VDSUB VSUB ∆VSUB

14.55

1.75

6.0 –3

15.0

2.0

∗

15.45

2.25

14.0 +3

V V V

VRD = VDD

∗

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions 2 [when used in substrate bias external adjustment mode]

Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision

∗

3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL

power supply for the V driver should be used. (When CXD1267AN is used.)

∗

4 Connect to GND or leave open.

∗

5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special

code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode.

VSUB code — one character indication Code and optimal setting correspond to each other as follows.

DC Characteristics

Item

Output circuit supply current IDD 5.0 10.0 mA

Symbol Min. Typ. Max. Unit Remarks

VSUB code Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5

10.0 10.5 11.0 11.512.0 12.5 13.0 13.5 14.0

E f G h J K L m N P Q R S T U V W

<Example> "L" → VSUB = 9.0V

Item

VDD VRD VGG VSS VL VDSUB

φSUB

14.55

1.75

14.55

15.0

2.0

∗

15.0

∗

15.45

2.25

15.45

V V V

VRD = VDD

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions 1 [when used in substrate bias internal generation mode]

Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate clock

Grounded with 390Ω resistor

∗

1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL

power supply for the V driver should be used. (When CXD1267AN is used.)

∗

2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

Grounded with 390Ω resistor

Page 5

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ICX039DNB

Item

Readout clock voltage

VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,

VVL3, VVL4 VφV I VVH1 – VVH2 I VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL VRGL VφRG VRGLH – VRGLL VφSUB

14.55 –0.05

–0.2 –9.6

8.3

–0.25 –0.25

4.75

–0.05

4.5

23.0

15.0 0 0

–9.0

9.0

5.0 0

∗

5.0

24.0

15.45

0.05

0.05 –8.5

9.65

0.1

0.5

5.25

0.05

5.5

0.8

25.0

V V V

Vp-p

V V V V V V V

Vp-p

V V

Vp-p

1 2 2

2 2

2 2 2 2 2 2 2 3 3 4 4 4 5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2 VφV= VVHn – VVLn (n = 1 to 4)

High-level coupling High-level coupling Low-level coupling Low-level coupling

Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage∗1

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Item Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

∗

1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven

with the following specifications.

Reset gate clock voltage

VRGL VφRG

–0.2

8.509.0

0.2

9.5VVp-p

4 4

Clock Voltage Conditions

Page 6

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ICX039DNB

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer clock and GND

CφV1, CφV3 CφV2, CφV4 CφV12, CφV34 CφV23, CφV41 CφH1 CφH2 CφHH CφRG CφSUB R1, R2, R3, R4 RGND

1800 2200

450 270

64 62 47

400

68 15

pF pF pF pF pF pF pF pF pF

Ω Ω

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND

Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor

Symbol Min. Typ. Max. Unit Remarks

Hφ2Hφ1

CφH1

CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23CφV41

CφV1 CφV2

CφV4 CφV3

RGND

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

Page 7

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ICX039DNB

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

VVT

tr twh tf

φM

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

Page 8

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ICX039DNB

(3) Horizontal transfer clock waveform

tr twh tf

90%

10%

twl

Vφ

VHL

(4) Reset gate clock waveform

Point A

twl

Vφ

VRGH

VRGL + 0.5V V

RGL

+2.5V

RGLH

RG waveform

RGLL

Hφ1 waveform

twhtr tf

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the period twh, then:

VφRG = VRGH – VRGL

Page 9

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ICX039DNB

(5) Substrate clock waveform

90%

100%

10%

SUB

tr twh tf

φM

V SUB

Clock Switching Characteristics

Item

Readout clock Vertical transfer

clock

During imaging

During parallelserial conversion

Reset gate clock

Substrate clock

VT Vφ1, Vφ2,

Vφ3, Vφ4 Hφ Hφ1

Hφ2

φRG

φSUB

2.3

1.5

2.5

5.38

1.8

5.38 51

0.5

0.01

0.01 3

0.5

0.01

0.01 3

250

0.5

µs

During readout

∗

During drain charge

Symbol

twh

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

twl tr tf

Unit Remarks

∗

1 When vertical transfer clock driver CXD1267AN is used.

∗

2 tf ≥ tr – 2ns.

Item

Horizontal transfer clock

Hφ1, Hφ2 16 20 ns

∗

Symbol

two

Min. Typ. Max.

Unit Remarks

∗

3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

Horizontal

transfer clock

Page 10

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ICX039DNB

Image Sensor Characteristics (Ta = 25°C)

Item Sensitivity Saturation signal Smear

Video signal shading

Uniformity between video signal channels

Dark signal Dark signal shading Flicker Y Flicker R-Y Flicker B-Y Line crawl R Line crawl G Line crawl B Line crawl W Lag

S Ysat Sm

SHy

∆Sr ∆Sb

Ydt ∆Ydt Fy Fcr Fcb Lcr Lcg Lcb Lcw Lag

550 720

660

0.00032

0.00056

20 25 10 10

2 1 2 5 5 3 3 3 3

0.5

mV mV

% % % %

% mV mV

1 2 3 4 4 5 5 6 7 8 8 8 9 9 9 9

Ta = 60°C

Zone 0 and I

Zone 0 to II'

Ta = 60°C Ta = 60°C

Symbol Min. Typ. Max. Unit Measurement method Remarks

Zone Definition of Video Signal Shading

582 (V)

1212

752 (H)

H 8

Effective pixel region

Zone 0, I

Zone II, II'

Ignored region

Measurement System

CCD C.D.S

LPF1

LPF2

AMP

CCD signal output

Y signal output

Chroma signal output

(3dB down 6.3MHz)

(3dB down 1MHz)

Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.

[∗A]

[∗Y]

[∗C]

Page 11

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ICX039DNB

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.)

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system.

Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals

As shown in the left figure, fields are read out. The charge is mixed by pairs such as A1 and A2 in the A field. (pairs such as B in the B field) As a result, the sequence of charges output as signals from the horizontal shift register (Hreg) is, for line A1, (G + Cy), (Mg + Ye), (G + Cy), and (Mg + Ye).

These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words, the approximation:

Y = {(G + Cy) + (Mg + Ye)} × 1/2

= 1/2 {2B + 3G + 2R}

is used for the Y signal, and the approximation:

R – Y = {(Mg + Ye) – (G + Cy)}

= {2R – G}

is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are

(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).

The Y signal is formed from these signals as follows:

Y = {(G + Ye) + (Mg + Cy)} × 1/2

= 1/2 {2B + 3G + 2R} This is balanced since it is formed in the same way as for line A1. In a like manner, the chroma (color difference) signal is approximated as follows:

– (B – Y) = {(G + Ye) – (Mg + Cy)}

= – {2B – G} In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y) in alternation. This is also true for the B field.

Cy Ye

Hreg

Color Coding Diagram

Page 12

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ICX039DNB

Definition of standard imaging conditions

1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity.

2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following formula.

S = Ys × [mV]

2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the Y signal output, 200mV, measure the minimum value of the Y signal.

3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.

4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.

SHy = (Ymax – Ymin)/200 × 100 [%]

5. Uniformity between video signal channels Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin [mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the following formula.

∆Sr = | (Crmax – Crmin)/200 | × 100 [%] ∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]

6. Dark signal Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

Sm =

× 100 [%] (1/10V method conversion value)

× ×

200

YSm

500

250

Page 13

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ICX039DNB

7. Dark signal shading After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark signal output and substitute the values into the following formula.

∆Ydt = Ydmax – Ydmin [mV]

8. Flicker

1) Fy Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then substitute the value into the following formula.

Fy = (∆Yf/200) × 100 [%]

2) Fcr, Fcb Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb). Substitute the values into the following formula.

Fci = (∆Ci/CAi) × 100 [%] (i = r, b)

9. Line crawls Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the following formula.

Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)

10. Lag Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following formula.

Lag = (Ylag/200) × 100 [%]

Ylag (lag)Y signal output 200mV

Light

FLD

Strobe light

timing

Output

Page 14

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ICX039DNB

15V

XSUB

XV2

XV1

XSG1

XV3

XSG2

XV4

Hφ

Hφ1

0.01

–9V

3.3/16V

100k

1/35V

22/16V

22/20V

CXD1267AN

1 2 3 4 5 6 7 8

16 15 14 13 12 11

390

47/6.3V

3.3/20V

0.01

0.01 180k

6.3V

27k

3.9k

CCD OUT

[

∗

100

Hφ

GND

Vss

DSUB

Vφ

SUB

Vφ

OUT

ICX039DNB

10 9

Drive Circuit 1 (substrate bias internal generation mode)

Page 15

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ICX039DNB

15V

XSUB

XV2

XV1

XSG1

XV3

XSG2

XV4

Hφ

Hφ1

0.01

–9V

3.3/16V

15k

47k

15k

0.1

39k

0.1

270k

27k

56k

0.1

100k

1/35V

22/16V

22/20V

CXD1267AN

1 2 3 4 5 6 7 8

9 10

16 15 14 13 12 11

390

47/6.3V

3.3/20V 0.01

0.01 180k

6.3V

27k

3.9k

CCD OUT

[

∗

100

Hφ

GND

Vss

DSUB

Vφ

SUB

Vφ

OUT

ICX039DNB

Drive Circuit 2 (substrate bias external adjustment mode)

Page 16

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ICX039DNB

Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)

700650600550500450400

Wave Length [nm]

Relative Response

1.0

0.8

0.6

0.4

0.2

0.0

Sensor Readout Clock Timing Chart

unit : µs

Odd Field

Even Field

2.5

2.6 2.5 2.5

1.5

33.6

0.2

Page 17

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ICX039DNB

Drive Timing Chart (Vertical Sync)

FLD

BLK

CCD

OUT

620

625

310

320

335

330

340

581

582

1 3 5

2 4 6

1 3 5

2 4 6

582

581

315

325

Page 18

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ICX039DNB

Drive Timing Chart (Horizontal Sync)

745

750

BLK

SUB

752

Page 19

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ICX039DNB

Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive

shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded

30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized

air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences. e) When protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Do not expose to strong light (sun rays) for long periods; color filters will be discolored. When high luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the imageplane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company.

5) Exposure to high temperature or high humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks.

Page 20

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ICX039DNB

Package Outline Unit: mm

PACKAGE STRUCTURE

16pin DIP (300mil)

1st. pin Index

6.175

12.0 ± 0.15

12.35 ± 0.3

φ13.2 ± 0.3

1.84

1.5

0.71.5

3.29 ± 0.3

2.54

7.62

0.25

4.0

4.0 ± 0.2

1.0

0.3

1.27

0.6

1.84

6.175

12.0 ± 0.15

12.35 ± 0.3

1. “A” is the center of the effective image area.

2. The point “B” of the package is the horizontal reference.

The point “B'” of the package is the vertical reference.

3. The bottom “C” of the package is the height reference.

4. The center of the effective image area relative to the center of the package (∗)

is (H, V) = (0, 0) ± 0.15mm.

5. The rotation angle of the effective image area relative to H and V is ± 1°.

6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.

7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.

8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.

∗ Center of the package : The center is halfway between two pairs of opposite sides,

as measured from “B”, “B'”.

0.3

~ ~

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

Ceramic

GOLD PLATING

42 ALLOY

0.9g