Datasheet ICS952011 CA431644 Datasheet

Integrated

ICS952011

Circuit Systems, Inc.

Programmable Timing Control Hub™ for P4™ processor

Recommended Application:

SIS 645/645DX/648/650 style chipsets.

Output Features:

• 2 - Pairs of differential CPUCLKs (diff erential current mode)

• 1 - SDRAM @ 3.3V

• 9 - PCI @3.3V (including 2 free-running)

• 2 - AGP @ 3.3V

• 2 - ZCLKs @ 3.3V

• 1- 12/48MHZ @ 3.3V

• 1- 24/48MHz, @3.3V selectable by I2C

• 3- REF @3.3V, 14.318MHz.

Key Specifications:

• PCI - PCI output skew: < 500ps

• CPU - SDRAM output skew: < 1ns

• AGP - AGP output skew: <150ps

Functionality

Bit2 Bit7 Bit6 Bit5 Bit4 CPU SDR AGP PCI ZCLK FS4 FS3 FS2 FS1 FS0

0 0 0 0 0 100.20 100.20 66.80 33.40 66.80 0 0 0 0 1 100.20 133.60 66.80 33.40 66.80 0 0 0 1 0 100.20 200.40 66.80 33.40 66.80 0 0 0 1 1 100.20 167.00 66.80 33.40 66.80 0 0 1 0 0 133.60 100.20 66.80 33.40 66.80 0 0 1 0 1 133.60 133.60 66.80 33.40 66.80 0 0 1 1 0 133.60 200.40 66.80 33.40 66.80 0 0 1 1 1 133.60 167.00 66.80 33.40 66.80 0 1 0 0 0 200.05 100.03 66.68 33.34 66.68 0 1 0 0 1 200.05 133.37 66.68 33.34 66.68 0 1 0 1 0 200.05 200.05 66.68 33.34 66.68 0 1 0 1 1 200.05 160.04 66.68 33.34 66.68 0 1 1 0 0 166.70 100.20 66.68 33.40 66.68 0 1 1 0 1 166.70 133.36 66.80 33.40 66.80 0 1 1 1 0 160.04 200.05 66.68 33.34 66.68 0 1 1 1 1 166.70 166.70 66.68 33.34 66.68 1 0 0 0 0 100.20 100.20 66.80 33.40 133.60 1 0 0 0 1 100.20 133.60 66.80 33.40 133.60 1 0 0 1 0 100.20 200.40 66.80 33.40 133.60 1 0 0 1 1 100.20 167.00 66.80 33.40 133.60 1 0 1 0 0 133.60 100.20 66.80 33.40 133.60 1 0 1 0 1 133.60 133.60 66.80 33.40 133.60 1 0 1 1 0 133.60 200.40 66.80 33.40 133.60 1 0 1 1 1 133.60 167.00 66.80 33.40 133.60 1 1 0 0 0 200.05 100.03 66.68 33.34 133.37 1 1 0 0 1 200.05 133.37 66.68 33.34 133.37 1 1 0 1 0 200.05 200.05 66.68 33.34 133.37 1 1 0 1 1 200.05 160.04 66.68 33.34 133.37 1 1 1 0 0 166.70 100.20 66.68 33.40 133.60 1 1 1 0 1 166.70 133.36 66.80 33.40 133.60 1 1 1 1 0 160.04 200.05 66.68 33.34 133.37 1 1 1 1 1 166.70 166.70 66.68 33.34 133.37

MHz MHz MHz MHz MHz

Features/Benefits:

• Selectable asynchronous/synchronous AGP, ZCLK and PCI outputs

• Supports DDR333 OEM frequencies

• Programmable output frequency , divider ratios, output rise/falltime, output skew .

• Programmable spread percentage for EMI control.

• Watchdog timer technology to reset system if system malfunctions.

• Programmable watch dog saf e frequency .

• Support I

2

C Index read/write and block read/write

operations.

• For PC133 SDRAM system use the ICS9179-16 as the memory buffer.

• For DDR SDRAM system use the ICS93735 or ICS93732 as the memory buffer .

• Uses external 14.318MHz crystal.

Pin Configuration

VDDREF 1 48 VDDSDR **FS0/REF0 2 47 SDRAM_OUT **FS1/REF1 3 46 GND **FS2/REF2 4 45 CPU_STOP#(PD#)*

GNDREF 5 44 CPUCLKT1

X1 6 43 CPUCLKC1 X2 7 42 VDDCPU

GNDZ 8 41 GNDCPU ZCLK0 9 40 CPUCLKT0 ZCLK1 10 39 CPUCLKC0

*(PCI_STOP#)PCICLK6 12 37 GND

**FS3/PCICLK_F0 14 35 SCLK **FS4/PCICLK_F1 15 34 SDATA

*MODE0/PCICLK0 16 33 Vtt_PwrGd/PD#(CPUSTOP#)*

VDDZ 11 38 IREF

VDDPCI 13 36 VDDA

ICS952011

PCICLK1 17 32 GNDAGP

GNDPCI 18 31 AGPCLK0

VDDPCI 19 30 AGPCLK1 PCICLK2 20 29 VDDAGP PCICLK3 21 28 VDD48 PCICLK4 22 27 12_48MHz/SEL12_48#** PCICLK5 23 26 24_48MHz/SEL24_48#*~

GNDPCI 24 25 GND48

48-SSOP

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

~ This output has 1.5X drive strength

0721A—07/29/03

Integrated

ICS952011

Circuit Systems, Inc.

General Description

The ICS952011 is a two chip clock solution for desktop designs using SIS 645/645DX/648/650 style chipsets. When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system.

The ICS952011 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

Block Diagram

X1 X2

FS (4:0)

VTTPWR_GND/PD#

CPU_STOP#

PCI_STOP#

MODE 0 SEL12_48# SEL24_48#

XTAL

Programmable

Control

Logic

Power Gr oups

Pin Number

VDD GND

1 5 REF Output, Crystal 11 8 Hyper ZCLK outputs 28 25 12/24/48MHz, Fix Analog, Fix Digital 29 32 AGP outputs 36 37 CPU PLL, CPU Analog, MCLK 42 41 CPU_T/C outputs 48 46 SDRAM_Out

Description

PLL2

Spread

PLL1

Frequency

Dividers

Programmable

Frequency

Dividers

STOP

Logic

12_48MHz 24_48MHz REF (2:0) CPUCLKT (1:0)

CPUCLKC (1:0) SDRAM_OUT AGPCLK (1:0) PCICLK (6:0) PCICLKF (1:0) ZCLK (1:0)

I REF

0721A—07/29/03

2

Integrated

q

p

y

p

yp

pply

p

pply

q

p

pply

p

pply

p

pprop

p

q

p

pply

p

q

p

Circuit Systems, Inc.

Pin Description

PIN PIN PIN

# NAME TYPE

1

VDDREF **FS0/REF0

2 3 **FS1/REF1 I/O Fre

**FS2/REF2

4

GNDREF

5

X1

6

X2

7

GNDZ

8

ZCLK0

9

ZCLK1

10

VDDZ

11 12 *(PCI_STOP#)PCICLK6 I/O

VDDPCI

13 14 **FS3/PCICLK_F0 I/O Fre

**FS4/PCICLK_F1

15 16

*MODE0/PCICLK0 PCICLK1

17

GNDPCI

18

VDDPCI

19

PCICLK2

20

PCICLK3

21

PCICLK4

22

PCICLK5

23

GNDPCI

24 25 GND48 PWR Ground

26 24_48MHz/SEL24_48#*~ I/O

27 12_48MHz/SEL12_48#** I/O 28 VDD48 PWR Power

29 VDDAGP PWR Power su 30 AGPCLK1 OUT AGP clock out 31 AGPCLK0 OUT AGP clock out 32 GNDAGP PWR Ground

Vtt_PwrGd/PD#(CPUSTOP

33

#)*

34 SDATA I/O Data 35 SCLK IN Clock 36 VDDA PWR 3.3V 37 GND PWR Ground

38 IREF OUT

39 CPUCLKC0 OUT

40 CPUCLKT0 OUT 41 GNDCPU PWR Ground

42 VDDCPU PWR Su 43 CPUCLKC1 OUT

44 CPUCLKT1 OUT

45 CPU_STOP#(PD#)* IN 46 GND PWR Ground

47 SDRAM_OUT OUT SDRAM seed clock out 48 VDDSDR PWR Supply for SDRAM clocks, nominal 3.3V.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor

0721A—07/29/03

PWR Ref, XTAL power supply, nominal 3.3V

I/O Fre

PWR Ground

IN Cr

OUT Cr

PWR Ground

OUT 3.3V H OUT 3.3V H

PWR Power su

I/O Fre I/O Function select l atch input pin, 1=Desktop Mode, 0=Mobile Mode / PCI clock output.

OUT PCI clock out PWR Ground PWR Power su

OUT PCI clock out

OUT PCI clock out PWR Ground

I/O

uency select latch input pin / 14.318 MHz reference clock. uency select latch input pin / 14.318 MHz reference clock. uency select latch input pin / 14.318 MHz reference clock.

in for the REF outputs. stal input, Nominally 14.318MHz. stal output, Nominally 14.318MHz

in for the ZCLK outputs

erzip clock output.

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This

ut is activated by the MODE selection pin / PCI clock output.

in

24MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.

12MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 12MHz.

This 3.3V LVTTL input is a level sensitive s trobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. Active low Power Down input or active low CPU_STOP depend on B24b3 IIC selection. Default is PD#.

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the a

"Complimentary" clocks of differential pair CPU outputs. These are current mode out

"True" clocks of differential pair CPU output s. These are current mode outputs. External resistors are re

"Complimentary" clocks of differential pair CPU outputs. These are current mode out

"True" clocks of differential pair CPU output s. These are current mode outputs. External resistors are re

Active low CPU_STOP or Active low Power Down input depend on B24b3 IIC selection. Default is CPU_STOP#.

for ZCLK clocks, nominal 3.3V

for PCI clocks, nominal 3.3V uency select latch input pin / 3.3V PCI free running clock output. uency select latch input pin / 3.3V PCI free running clock output.

ut.

in for the PCI outputs

for PCI clocks, nominal 3.3V

ut. ut. ut.

ut. in for the PCI outputs in for the 48MHz outputs

in for the 48MHz output.3.3V

for AGP clocks, nominal 3.3V

ut ut

in for the AGP outputs

in for I2C circuitry 5V tolerant

in of I2C circuitry 5V tolerant

ower for the PLL core.

in.

riate current. 475 ohms is the standard value.

uts. External resistors are required for voltage bias.

uired for voltage bias.

in for the CPU outputs

for CPU clocks, 3.3V nominal

uts. External resistors are required for voltage bias.

uired for voltage bias.

in.

ut for external buffer

ICS952011

DESCRIPTION

3

Integrated Circuit Systems, Inc.

Table 6: CPUCLK Swing Select Functions

ICS952011

0tiB42etyB

0LESTLUM

00 smho06

00 smho05

01 smho06

01 smho05

10 smho06

10 smho05

11 smho06

11 smho05

00 )viuqeCD(03

00 )viuqeCD(52

01 )viuqeCD(03

01 )viuqeCD(52

10 )viuqeCD(03

10 )viuqeCD(52

11 )viuqeCD(03

11 )viuqeCD(52

7tiB32etyB

1LESTLUM

tegraTdraoB

ZmreT/ecarT

,RecnerefeR

)rR*3(/ddV=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1574=rR

Am23.2=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

%1122=rR

Am5=ferI

tuptuO

tnerruC

ferI*5=hoI06@V17.0

ferI*5=hoI05@V95.0

ferI*4=hoI06@V65.0

ferI*4=hoI05@V74.0

ferI*6=hoI062/V58.0

ferI*6=hoI05@V17.0

ferI*7=hoI06@V99.0

ferI*7=hoI05@V28.0

ferI*5=hoI03@V57.0

ferI*5=hoI02@V26.0

ferI*4=hoI02@06.0

ferI*4=hoI02@V5.0

ferI*6=hoI03@V09.0

ferI*6=hoI02@V57.0

ferI*7=hoI03@V50.1

ferI*7=hoI02@V48.0

,Z@hoV

Am23.2=ferI

0721A—07/29/03

4

Integrated Circuit Systems, Inc.

General I2C serial interface information for the ICS952011

ICS952011

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

• Controller (host) starts sending

acknowledge

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

• Controller (host) sends a Stop bit

Index Block Write Operation

Controller (Host)

T

Slave Address D2

WR

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

starT bit

WRite

(H)

ICS (Slave/Receiver)

ACK

(H)

one at a time

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

was written to byte 8)

Byte N + X -1 Byte 0 through byte X (if X

.

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Controller (Host)

T starT bit

Slave Address D2

WR WRite

Beginning Byte = N

RT Repeat starT

Slave Address D3

RD ReaD

(H)

ICS (Slave/Receiver)

ACK

(H)

Byte N + X - 1

P

0721A—07/29/03

stoP bit

X Byte

ACK

N Not acknowledge PstoP bit

ACK

Data Byte Count = X

Beginning Byte N

X Byte

Byte N + X - 1

5

Integrated Circuit Systems, Inc.

Table1: QuadRom Frequency Selection Table

B24 B24 Bit2 Bit7 Bit6 Bit5 Bit4 Bit6 Bit5 FS4 FS3 FS2 FS1 FS0

0 0 0 0 0 0 0 100.20 100.20 66.80 33.40 66.80 0 0 0 0 0 0 1 100.20 133.60 66.80 33.40 66.80 0 0 0 0 0 1 0 100.20 200.40 66.80 33.40 66.80 0 0 0 0 0 1 1 100.20 167.00 66.80 33.40 66.80

0 0 0 0 1 0 0 133.60 100.20 66.80 33.40 0 0 0 0 1 0 1 133.60 133.60 66.80 33.40 66.80 0 0 0 0 1 1 0 133.60 200.40 66.80 33.40 66.80 0 0 0 0 1 1 1 133.60 167.00 66.80 33.40 66.80 0 0 0 1 0 0 0 200.05 100.03 66.68 33.34 66.68 0 0 0 1 0 0 1 200.05 133.37 66.68 33.34 66.68 0 0 0 1 0 1 0 200.05 200.05 66.68 33.34 66.68 0 0 0 1 0 1 1 200.05 160.04 66.68 33.34 66.68 0 0 0 1 1 0 0 166.70 100.20 66.68 33.40 66.68 0 0 0 1 1 0 1 166.70 133.36 66.80 33.40 66.80 0 0 0 1 1 1 0 160.04 200.05 66.68 33.34 66.68 0 0 0 1 1 1 1 166.70 166.70 66.68 33.34 66.68 0 0 1 0 0 0 0 100.20 100.20 66.80 33.40 133.60 0 0 1 0 0 0 1 100.20 133.60 66.80 33.40 133.60

0 0 1 0 0 1 0 100.20 200.40 66.80 33.40 133.60 0 0 1 0 0 1 1 100.20 167.00 66.80 33.40 133.60

0 0 1 0 1 0 0 133.60 100.20 66.80 33.40 133.60 0 0 1 0 1 0 1 133.60 133.60 66.80 33.40 133.60 0 0 1 0 1 1 0 133.60 200.40 66.80 33.40 133.60 0 0 1 0 1 1 1 133.60 167.00 66.80 33.40 133.60 0 0 1 1 0 0 0 200.05 100.03 66.68 33.34 133.37 0 0 1 1 0 0 1 200.05 133.37 66.68 33.34 133.37 0 0 1 1 0 1 0 200.05 200.05 66.68 33.34 133.37 0 0 1 1 0 1 1 200.05 160.04 66.68 33.34 133.37 0 0 1 1 1 0 0 166.70 100.20 66.68 33.40 133.60 0 0 1 1 1 0 1 166.70 133.36 66.80 33.40 133.60 0 0 1 1 1 1 0 160.04 200.05 66.68 33.34 133.37

0 0 1 1 1 1 1 166.70 166.70 66.68 33.34 133.37

CPU SDR AGP PCI ZCLK MHz MHz MHz MHz MHz

ICS952011

66.80

0721A—07/29/03

6

Integrated Circuit Systems, Inc.

Table1: QuadRom Frequency Selection Table (Continued)

B24 B24 Bit4 Bit3 Bit2 Bit1 Bit0 CPU SDR AGP PCI ZCLK Bit6 Bit5 FS4 FS3 FS2 FS1 FS0 MHz MHz MHz MHz MHz

0 1 0 0 0 0 0 100.00 100.00 66.66 33.33 0 1 0 0 0 0 1 100.00 133.33 66.66 33.33 0 1 0 0 0 1 0 100.00 200.00 66.66 33.33 0 1 0 0 0 1 1 100.00 166.67 66.66 33.33 0 1 0 0 1 0 0 133.33 100.00 66.66 33.33 0 1 0 0 1 0 1 133.33 133.33 66.66 33.33 0 1 0 0 1 1 0 133.33 200.00 66.66 33.33 0 1 0 0 1 1 1 133.33 166.67 66.66 33.33 0 1 0 1 0 0 0 200.00 100.00 66.66 33.33 0 1 0 1 0 0 1 200.00 133.33 66.66 33.33 0 1 0 1 0 1 0 200.00 200.00 66.66 33.33 0 1 0 1 0 1 1 200.00 160.00 66.66 33.33 0 1 0 1 1 0 0 166.66 100.00 66.66 33.33 0 1 0 1 1 0 1 166.67 133.33 66.66 33.33 0 1 0 1 1 1 0 160.00 200.00 66.66 33.33 0 1 0 1 1 1 1 166.67 166.67 66.66 33.33 0 1 1 0 0 0 0 100.00 100.00 66.66 33.33 133.33 0 1 1 0 0 0 1 100.00 133.33 66.66 33.33 133.33 0 1 1 0 0 1 0 100.00 200.00 66.66 33.33 133.33 0 1 1 0 0 1 1 100.00 166.67 66.66 33.33 133.33 0 1 1 0 1 0 0 133.33 100.00 66.66 33.33 133.33 0 1 1 0 1 0 1 133.33 133.33 66.66 33.33 133.33 0 1 1 0 1 1 0 133.33 200.00 66.66 33.33 133.33 0 1 1 0 1 1 1 133.33 166.67 66.66 33.33 133.33 0 1 1 0 0 0 0 200.00 100.00 66.66 33.33 133.33 0 1 1 0 0 0 1 200.00 133.33 66.66 33.33 133.33 0 1 1 0 0 1 0 200.00 200.00 66.66 33.33 133.33 0 1 1 0 0 1 1 200.00 160.00 66.66 33.33 133.33 0 1 1 1 1 0 0 166.66 100.00 66.66 33.33 133.33 0 1 1 1 1 0 1 166.67 133.33 66.66 33.33 133.33 0 1 1 1 1 1 0 160.00 200.00 66.66 33.33 133.33 0 1 1 1 1 1 1 166.67 166.67 66.66 33.33 133.33

66.66

ICS952011

0721A—07/29/03

7

Integrated Circuit Systems, Inc.

Table1: QuadRom Frequency Selection Table (Continued)

B24 B24 Bit4 Bit3 Bit2 Bit1 Bit0 Bit6 Bit5 FS4 FS3 FS2 FS1 FS0

0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0110000 0110001 0110010 0110011 0111100 0111101 0111110 0111111

CPU SDR AGP MHz MHz MHz

100.20 100.20 66.80 33.40 80.16

100.20 133.60 66.80 33.40 80.16

100.20 200.40 66.80 33.40 80.16

100.20 167.00 66.80 33.40 80.16

133.60 100.20 66.80 33.40

133.60 133.60 66.80 33.40 80.16

133.60 200.40 66.80 33.40 80.16

133.60 167.00 66.80 33.40 80.16

200.05 100.03 66.68 33.34 80.02

200.05 133.37 66.68 33.34 80.02

200.05 200.05 66.68 33.34 80.02

200.05 160.04 66.68 33.34 80.02

166.70 100.20 66.68 33.40 80.16

166.70 133.36 66.80 33.40 80.16

160.04 200.05 66.68 33.34 80.02

166.70 166.70 66.68 33.34 80.02

100.20 100.20 66.80 33.40 100.20

100.20 133.60 66.80 33.40 100.20

100.20 200.40 66.80 33.40 100.20

100.20 167.00 66.80 33.40 100.20

133.60 100.20 66.80 33.40 100.20

133.60 133.60 66.80 33.40 100.20

133.60 200.40 66.80 33.40 100.20

133.60 167.00 66.80 33.40 100.20

200.05 100.03 66.68 33.34 100.03

200.05 133.37 66.68 33.34 100.03

200.05 200.05 66.68 33.34 100.03

200.05 160.04 66.68 33.34 100.03

166.70 100.20 66.68 33.40 100.20

166.70 133.36 66.80 33.40 100.20

160.04 200.05 66.68 33.34 100.03

166.70 166.70 66.68 33.34 100.03

PCI

MHz

ICS952011

ZCLK

MHz

80.16

0721A—07/29/03

8

Integrated Circuit Systems, Inc.

Table1: QuadRom Frequency Selection Table (Continued)

B24 B24 Bit4 Bit3 Bit2 Bit1 Bit0 Bit6 Bit5 FS4 FS3 FS2 FS1 FS0

0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0110000 0110001 0110010 0110011 0111100 0111101 0111110 0111111

CPU SDR AGP MHz MHz MHz

100.00 100.00 66.66 33.33

100.00 133.33 66.66 33.33

100.00 200.00 66.66 33.33

100.00 166.67 66.66 33.33

133.33 100.00 66.66 33.33

133.33 133.33 66.66 33.33

133.33 200.00 66.66 33.33

133.33 166.67 66.66 33.33

200.00 100.00 66.66 33.33

200.00 133.33 66.66 33.33

200.00 200.00 66.66 33.33

200.00 160.00 66.66 33.33

166.66 100.00 66.66 33.33

166.67 133.33 66.66 33.33

160.00 200.00 66.66 33.33

166.67 166.67 66.66 33.33

100.00 100.00 66.66 33.33 100.00

100.00 133.33 66.66 33.33 100.00

100.00 200.00 66.66 33.33 100.00

100.00 166.67 66.66 33.33 100.00

133.33 100.00 66.66 33.33 100.00

133.33 133.33 66.66 33.33 100.00

133.33 200.00 66.66 33.33 100.00

133.33 166.67 66.66 33.33 100.00

200.00 100.00 66.66 33.33 100.00

200.00 133.33 66.66 33.33 100.00

200.00 200.00 66.66 33.33 100.00

200.00 160.00 66.66 33.33 100.00

166.66 100.00 66.66 33.33 100.00

166.67 133.33 66.66 33.33 100.00

160.00 200.00 66.66 33.33 100.00

166.67 166.67 66.66 33.33 100.00

PCI

MHz

ICS952011

ZCLK

MHz

80.00

0721A—07/29/03

9

Integrated

)

Table 3: ZCLK F

ICS952011

Circuit Systems, Inc.

I2C Table: Function Control Register

NamePin #Byte 0 Type 0

Bit 7 PDEN PD# Enable RW Disable Enable 1

Bit 6

Bit 5 Bit 4

Bit 3 AZCLKFS

Bit 2 Bit 1

Bit 0

-

AZCLKFS

WDS_EN WD Soft Enable RW Disable Enable 1 PCICLK6 Output Control RW Disable Enable 1

Reserved Reserved RW - 1

AEN1 RW 0

AEN0 RW 0

Async Zclk Freq Select in

(Mode 10 & 11, s e e t a bl e

Control

Function

N-programming (Mode

01, see table 3)

Async Zclk Freq Select

3

Zclk/Agp/Pci Freq

Source Select Control

RW 66.6MHz 133.3MHz 1

RW 66MHz 132MHz 1

See Table 3 : ZCLK, AGP &

PCI Frequency Source

Decode Table

1PWD

requency Source Decode Table

Byte0 Bit1 Byte0 Bit0 ZCLK & AGP & PCI

0 0 See Table 1, QuadRom Frequency Table 0 1 N-Programming for ZCLK/AGP/PCI 1 0 See Table 1 f or AGP/PCI, B0b3 for ZCLK freq 1 1 N-Prog for AGP/PCI, B 0b3 for ZCLK freq

I2C Table: Async N-Programming Frequency Se lect Register

Control

Function

The decimal

representation of N PLL2

Div (7:0) + 8 is equal to

VCO divider value for

PLL2. Default at power

up = 66.67MHz

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 1

Pin #

-

Name Type

N PLL3 Div7 RW - - 0 N PLL3 Div6 RW - - 1 N PLL3 Div5 RW - - 0 N PLL3 Div4 RW - - 0 N PLL3 Div3 RW - - 0 N PLL3 Div2 RW - - 1 N PLL3 Div1 RW - - 1 N PLL3 Div0 RW - - 1

I2C Table: Reserved Register

Control

Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 2

Pin #

-

Name

Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1

Type 1 PWD0

1

PWD0

0721A—07/29/03

10

Integrated Circuit Systems, Inc.

ICS952011

Byte1 (7:0)

Hex

26 27 28

29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B

VCO Freq AGP Freq PCI Freq

360.34

361.53

362.73

363.92

365.11

366.31

367.50

368.69

369.89

371.08

372.27

373.47

374.66

375.85

377.05

378.24

379.43

380.62

381.82

383.01

384.20

385.40

386.59

387.78

388.98

390.17

391.36

392.56

393.75

394.94

396.14

397.33

398.52

399.72

400.91

402.10

403.30

404.49

60.06 30.03

60.26 30.13

60.45 30.23

60.65 30.33

60.85 30.43

61.05 30.53

61.25 30.62

61.45 30.72

61.65 30.82

61.85 30.92

62.05 31.02

62.24 31.12

62.44 31.22

62.64 31.32

62.84 31.42

63.04 31.52

63.24 31.62

63.44 31.72

63.64 31.82

63.84 31.92

64.03 32.02

64.23 32.12

64.43 32.22

64.63 32.32

64.83 32.41

65.03 32.51

65.23 32.61

65.43 32.71

65.62 32.81

65.82 32.91

66.02 33.01

66.22 33.11

66.42 33.21

66.62 33.31

66.82 33.41

67.02 33.51

67.22 33.61

67.41 33.71

Byte1 (7:0)

Hex

4C 4D

4E 4F

50 51 52 53 54 55 56 57 58

59 5A 5B

5C 5D

5E 5F

60

61

62

63

64

65

66

67

68

69 6A 6B

6C 6D

6E 6F

70

71

VCO Freq AGP Freq PCI Freq

405.68

406.87

408.07

409.26

410.45

411.65

412.84

414.03

415.23

416.42

417.61

418.81

420.00

421.19

422.39

423.58

424.77

425.97

427.16

428.35

429.55

430.74

431.93

433.12

434.32

435.51

436.70

437.90

439.09

440.28

441.48

442.67

443.86

445.06

446.25

447.44

448.64

449.83

67.61 33.81

67.81 33.91

68.01 34.01

68.21 34.11

68.41 34.20

68.61 34.30

68.81 34.40

69.01 34.50

69.20 34.60

69.40 34.70

69.60 34.80

69.80 34.90

70.00 35.00

70.20 35.10

70.40 35.20

70.60 35.30

70.80 35.40

70.99 35.50

71.19 35.60

71.39 35.70

71.59 35.80

71.79 35.89

71.99 35.99

72.19 36.09

72.39 36.19

72.59 36.29

72.78 36.39

72.98 36.49

73.18 36.59

73.38 36.69

73.58 36.79

73.78 36.89

73.98 36.99

74.18 37.09

74.37 37.19

74.57 37.29

74.77 37.39

74.97 37.49

0721A—07/29/03

11

Integrated Circuit Systems, Inc.

ICS952011

Byte1 (7:0)

Hex

72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97

VCO Freq AGP Freq PCI Freq

451.02

452.22

453.41

454.60

455.80

456.99

458.18

459.37

460.57

461.76

462.95

464.15

465.34

466.53

467.73

468.92

470.11

471.31

472.50

473.69

474.89

476.08

477.27

478.47

479.66

480.85

482.05

483.24

484.43

485.62

486.82

488.01

489.20

490.40

491.59

492.78

493.98

495.17

75.17 37.59

75.37 37.68

75.57 37.78

75.77 37.88

75.97 37.98

76.16 38.08

76.36 38.18

76.56 38.28

76.76 38.38

76.96 38.48

77.16 38.58

77.36 38.68

77.56 38.78

77.76 38.88

77.95 38.98

78.15 39.08

78.35 39.18

78.55 39.28

78.75 39.37

78.95 39.47

79.15 39.57

79.35 39.67

79.55 39.77

79.74 39.87

79.94 39.97

80.14 40.07

80.34 40.17

80.54 40.27

80.74 40.37

80.94 40.47

81.14 40.57

81.34 40.67

81.53 40.77

81.73 40.87

81.93 40.97

82.13 41.07

82.33 41.16

82.53 41.26

Byte1 (7:0)

Hex

98

99 9A 9B

9C 9D

9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

AA AB AC AD AE AF

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9

BA BB BC BD

VCO Freq AGP Freq PCI Freq

496.36

497.56

498.75

499.94

501.14

502.33

503.52

504.72

505.91

507.10

508.30

509.49

510.68

511.87

513.07

514.26

515.45

516.65

517.84

519.03

520.23

521.42

522.61

523.81

525.00

526.19

527.39

528.58

529.77

530.97

532.16

533.35

534.55

535.74

536.93

538.12

539.32

540.51

82.73 41.36

82.93 41.46

83.12 41.56

83.32 41.66

83.52 41.76

83.72 41.86

83.92 41.96

84.12 42.06

84.32 42.16

84.52 42.26

84.72 42.36

84.91 42.46

85.11 42.56

85.31 42.66

85.51 42.76

85.71 42.86

85.91 42.95

86.11 43.05

86.31 43.15

86.51 43.25

86.70 43.35

86.90 43.45

87.10 43.55

87.30 43.65

87.50 43.75

87.70 43.85

87.90 43.95

88.10 44.05

88.30 44.15

88.49 44.25

88.69 44.35

88.89 44.45

89.09 44.55

89.29 44.64

89.49 44.74

89.69 44.84

89.89 44.94

90.09 45.04

0721A—07/29/03

12

Integrated Circuit Systems, Inc.

I2C Table: Reserved Register

Byte 3 Pin #

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1 Reserved Reserved RW - - 1

I2C Table: Frequency Select Register

Name TypeByte 4 Pin #

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3 Bit 2

Bit 1 Bit 0

-

FS3 Freq Select Bit 7 RW 0 FS2 Freq Select Bit 6 RW 0 FS1 Freq Select Bit 5 RW 0 FS0 Freq Select Bit 4 RW 0

FS Source Frequency HW/IIC Select RW Latch Input IIC 0

FS4 Freq Select Bit 2 RW 0

SS_EN Spread Ena ble RW OFF ON 1

Outputs Output Control RW Running Tri-state 0

Control

Function

Control

Function

ICS952011

01

See Table1 : Quad Rom

Frequency Selection Table

See Table1

PWDName Type

PWD

I2C Table: Read Back Register

Byte 5 Pin # Name

Bit 7

Bit 6 Bit 5

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

MULTISEL Multisel Read back R - - X

I2C Table: Output Control Register

Byte 6 Pin #

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Bit 2 Bit 1 Bit 0

10

9 14 15

40, 39 44, 43 40, 39

44, 43

CPUT0/C0 CPU_STOP# Control RW Stop Disable Stop Enable 1 CPUT1/C1 CPU_STOP# Control RW Stop Disable Stop Enable 1 CPUT0/C0 Output Control RW Disable Enable 1 CPUT1/C1 Output Control RW Disable Enable 1

Control

Function

WDHRB

WDSRB

FS4RB FS4 Read back R - - X FS3RB FS3 Read back R - - X FS2RB FS2 Read back R - - X FS1RB FS1 Read back R - - X FS0RB FS0 Read back R - - X

Name

ZCLK_1 Output Control RW Disable Enable 1 ZCLK_0 Output Control RW Disable Enable 1

PCI_F0 PCI_STOP# Control RW Stop Disable Stop Enable 0 PCI_F1 PCI_STOP# Control RW Stop Disable Stop Enable 0

WD Hard Alarm Status

Read back

WD Soft Alarm Status

Read back

Control

Function

Type

RNormalAlarmX

Type

0

1

PWD

0721A—07/29/03

13

Integrated

ICS952011

Circuit Systems, Inc.

I2C Table: Output Control Register

Byte 7 Pin #

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PCICLK2 Output Control RW Disable Enable 1 Bit 1 Bit 0

15 14 23 22 21 20 17 16

PCICLK_F1 Output Control RW D isable Enable 1 PCICLK_F0 Output Control RW D isable Enable 1

PCICLK5 Output Control RW Disable Enable 1 PCICLK4 Output Control RW Disable Enable 1 PCICLK3 Output Control RW Disable Enable 1

PCICLK1 Output Control RW Disable Enable 1 PCICLK0 Output Control RW Disable Enable 1

Control

Function

TypeName 0 1

I2C Table: Byte Count Register

Byte 8 Pin # Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BC3 RW - - 1 Bit 2 Bit 1 Bit 0

-

BC7 RW - - 0 BC6 RW - - 0 BC5 RW - - 0 BC4 RW - - 0

BC2 RW - - 1 BC1 RW - - 1 BC0 RW - - 1

Writing to this register will

Control

Function

configure how many bytes will be read back, default is 0F

= 15 bytes.

Type

1

PWD

I2C Table: Watchdog Timer Register

Control

Function

Bit 7 WD7 RW - - 0 Bit 6 Bit 5 Bit 4 WD4 RW - - 1 Bit 3 Bit 2 Bit 1 WD1 RW - - 0 Bit 0

-

WD6 RW - - 0 WD5 RW - - 0

WD3 RW - - 0 WD2 RW - - 0

WD0 RW - - 0

These bits represent

X*290ms the watchdog

timer will wait before it

goes to alarm mode.

Default is 16 X 290ms

=4.64 sec onds

Type 0Byte 9 Pin # Name

I2C Table: VCO Control Select Bit & WD Timer Control Register

Byte 10 Pin #

Bit 7 Bit 6 WDEN Watchdog Enable R Disable Enable 0

Bit 5 Bit 4 Bit 3 WD SF3 RW - - 0 Bit 2 Bit 1 Bit 0

-

Name Type

Reserved Reserved RW - - 0

WD SF4 RW - - 0

WD SF2 RW - - 0 WD SF1 RW - - 0 WD SF0 RW - - 1

Control

Function

M/N Programming

Enable

Writing to these bit will

configure the safe

frequency as Byte4bit 2,

(7:4)

RW

010PWD

EnableDisable

PWD1

0M/NEN

0721A—07/29/03

14

Integrated Circuit Systems, Inc.

I2C Table: VCO Frequency Control Register

Bit 7

-

N Div8 N Divider Bit 8 RW - - X

Control

Function

ICS952011

TypeByte 11 Pin # N am e

011PWD

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

M Div6 RW - - X

M Div5 RW - - X M Div4 RW - - X M Div3 RW - - X M Div2 RW - - X M Div1 RW - - X M Div0 RW - - X

The decimal

representation of M Div

(6:0) + 2 is equal to

reference divider value.

Default at power up =

latch-in or Byte 0 Rom

table.

I2C Table: VCO Frequency Control Register

Byte 12 Pin # N am e

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

N Div7 RW - - X N Div6 RW - - X N Div5 RW - - X N Div4 RW - - X N Div3 RW - - X N Div2 RW - - X N Div1 RW - - X N Div0 RW - - X

(8:0) + 8 is equal to VCO

Control

Function

The decimal

representation of N Div

divider value. Default at

power up = latch-in or

Byte 0 Rom table.

I2C Table: Spread Spectrum Control Register

Byte 13 Pin # N am e Ty pe

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

SSP7 RW - - X SSP6 RW - - X SSP5 RW - - X SSP4 RW - - X SSP3 RW - - X SSP2 RW - - X SSP1 RW - - X SSP0 RW - - X

recommended to use ICS

Control

Function

These Spread Spectrum

bits will pr og r am t h e spread pecentage. It is

Spread % table for

spread programming.

Type

01

0

PWD

I2C Table: Spread Spectrum Control Register

Byte 14 Pin # N am e Ty pe

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0721A—07/29/03

-

Reserved Reserved R - - 0 Reserved Reserved R - - 0

SSP13 RW - - X SSP12 RW - - X SSP11 RW - - X SSP10 RW - - X

SSP9 RW - - X SSP8 RW - - X

It is recommended to use

Control

Function

ICS Spread % table for

spread programming.

15

01

PWD

Integrated

ICS952011

Circuit Systems, Inc.

I2C Table: Output Divider Control Register

Byte 15 Pin # N am e

Bit 7 Bit 6 Bit 5 SDDiv1 RW X Bit 4 Bit 3 Bit 2

Bit 1 CPU Div 1 RW X Bit 0

-

SDDiv3 RW X SDDiv2 RW X

SDDiv0 RW X CPU Div3 RW X CPU Div2 RW X

CPU Div0 RW X

Control

Function

SD divider ratio can be

configured via these 4

bits individually.

CPU divider ratio can be

configured via these 4

bits individually.

01Type PWD

See Table 4: Divider Ratio

Combination Table

See Table 4: Divider Ratio

Combination Table

Table 4: CPU, SDR Divider Ratio Combination Table

Divider (3:2)

Bit00011011MSB

1248

00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24

Divider (1:0)

10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56

LSB Address Div Address Div Address Div Address Div

I2C Table: Output Divider Control Register

Byte 16 Pin # N am e

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X

Control

Function

I2C Table: Output Divider Control Register

Byte 17 Pin # N am e Ty pe

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

Reserved Reserved RW - - X Reserved Reserved RW - - X

SDINV SD Phase Invert RW Default Inverse X

CPUINV CPU Phase Invert RW Default Inverse X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X Reserved Reserved RW - - X

Control

Function

Type 0 1

0 1 PWD

PWD

0721A—07/29/03

16

Integrated

Table 5: 4-St

MSB

ICS952011

Circuit Systems, Inc.

I2C Table: Group Skew Control Register

Control

Function

CPU-CPU Skew Cont rol

CPU-SD Skew Cont rol

See Table 5: 4- St e p s Skew

Programming Table

See Table 5: 4- St e p s Skew

Programming Table

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 18

Pin # PWD

-

Name Type 0 1

CPUSkw1 RW 1 CPUSkw0 RW 1

SDSkw1 RW 0

SDSkw0 RW 0 Reserved Reserved RW - - 1 Reserved Reserved RW - - 0 Reserved Reserved RW - - 0 Reserved Reserved RW - - 0

I2C Table: Group Skew Control Register

Byte 19 Pin # N am e PWD

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

ZCLKSkw1 RW 0 ZCLKSkw0 RW 0

Reserved Reserved RW - - 0 Reserved Reserved RW - - 0

AGPSkw1 RW 0 AGPSkw0 RW 0

Reserved Reserved RW - - 0 Reserved Reserved RW - - 0

CPU-ZCLK Skew Control

Control

Function

CPU-AGP Skew Control

Type

01

See Table 5: 4- St e p s Skew

Programming Table

See Table 5: 4- St e p s Skew

Programming Table

I2C Table: Group Skew Control Register

Byte 20 Pin # N am e Ty pe

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

PCI_FSkw1 RW 0 PCI_FSkw0 RW 0

Reserved Reserved RW - - 0 Reserved Reserved RW - - 0 PCISkw1 RW 0 PCISkw0 RW 0 Reserved Reserved RW - - 0 Reserved Reserved RW - - 0

Control

Function

CPU-PCI_F Skew

Control

CPU-PCI Skew Control

eps Skew Programming Table

4 Step 0 1 LSB

0 0ps 250ps 1 500ps 750ps

---

-

01

See Table 5: 4- St e p s Skew

Programming Table

See Table 5: 4- St e p s Skew

Programming Table

PWD

0721A—07/29/03

17

Integrated

ICS952011

Circuit Systems, Inc.

I2C Table: Slew Rate Control Register

Byte 21

Bit 7 Bit 6 Bit 5 AGPSlw1 RW - - 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Pin # Name

-

24/48Slw1 RW - - 0 24/48Slw0 RW - - 0

AGPSlw0 RW - - 0

ZCLKSlw1 RW - - 0 ZCLKSlw0 RW - - 0

REFSlw1 RW - - 0 REFSlw0 RW - - 0

Control

Function

24/48 Slew Rate Control

AGP Slew Rate Control

ZCLK Slew Rate Control

REF Slew Rate Control

Type 0 1 PWD

I2C Table: Slew Rate Control Register

Byte 22 Pin # N am e Ty pe 10

30 31

-

SDSlw1 RW - - 0

SDSlw0 RW - - 0 AGPCLK1 Output Control RW Disable Enable 1 AGPCLK0

PCI_FSlw0 RW - - 0

PCISlw1 RW - - 0 PCISlw0 RW - - 0

PCI_F Slew Rate Control

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PCI_FSlw1 RW - - 0 Bit 2 Bit 1 Bit 0

Control

Function

SD Slew Rate Control

Output Control

PCI Slew Rate Control

RW Disable Enable 1

PWD

I2C Table: Output Control Register

Byte 23 Pin # N am e Ty pe

26 47 27 26

-

4 3 2

MultSel1 IREF X plier Control RW 0

SEL24_48 24MHz or 48MHz RW 48MHz 24MHz 1

SDRAM_OUT Output Control RW Disable Enable 1

12_48MHz Output Control RW Disable Enable 1

REF2 Output Control RW Disable Enable 1 REF1 Output Control RW Disable Enable 1 REF0 Output Control RW Disable Enable 1

Bit 7 Bit 6

Bit 5 Bit 4 Bit 3 24_48MHz Output Control RW Disable Enable 1 Bit 2 Bit 1 Bit 0

Control

Function

See Table 6

10PWD

I2C Table: Output Control Register

Byte 24 Pin # N am e Ty pe

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3 Bit 2

Bit 1 Bit 0

27

-

45,33

-

SEL12_48 12MHz or 48MHz RW 48MHz 12MHz 0

FS6 Freq Select bit 6 RW 0 FS5 Freq Select bit 5 RW 0

Reserved Reserved RW - - 0

STOP_PD Swap

SS_SEL SS Scheme Select1 RW 0 SS_SEL SS Scheme Select1 RW 0

MultSel0 IREF X plier Control RW 1

Control

Function

Swap CPU_STOP# and

PD# location

RW

01

See Table 1

Stop-Pin33 PD#-Pin45

See Table 2: Spread

Spectr um S e le c t i o n Ta ble

See Table 6: MultSel

Selection Table

Stop-Pin45 PD#-Pin33

PWD

1

0721A—07/29/03

18

Integrated

(By

)

(By

)

Circuit Systems, Inc.

Table2: Spread Spectrum Select Table

SS1 SS0

te 24 bit 2

0 0 OFF 0.35% 0.40% 0 1 OFF 0.50% 0.55% 1 0 0.22% 0.75% 0.80% 1 1 0.48% 1.00% 1.00%

te 24 bit 1

QuadRom Sec1&3 b(6:5 ,FS3

Byte4:bit7) = 000, 100

QuadRom Sec1&3 b(6:5,FS3

Byte4:bit7) = 001, 101

ICS952011

QuadRom Sec2&4

b(6:3) = 0011

0721A—07/29/03

19

Integrated

1

ICS952011

Circuit Systems, Inc.

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

1

V

I

IL1

I

IL2

I

DD(op)

I

DDPD

F

C

T

trans

T

STAB

T

CPU-PCIVT

Input High Voltage

Input Low Voltage

Input High Cu rre n t

Input Low Current Input Low Current

Operating Supply

Current

Power Down Supply

Current

Input frequency

Input Capacitance

Transition Time

Clk Stabilization

Skew

1

Guaranteed by design, not 100% tested in production.

1

= 3.3 V +/-5% (unless otherwise stated)

DD

IH IL

VIN = V

IH

DD

VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors

CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to VDD or

GND VDD = 3.3 V

i

Logic Inputs 5 pF

IN

X1 & X2 pins 27 45 pF

INX

To 1st crossing of target Freq. 1.8 3 ms From VDD = 3.3 V to 1% target Freq.

= 1.5 V

+0.5 V

DD

+ 0.3

2

V

- 0.3

SS

V

DD

0.8 V 5 µ

-5 µ

-200 µ 213 280 mA

15 40 mA

11 16 MHz

13ms

1.5 2.19 4 ns

V

A A A

Electrical Characteristics - PCICLK

TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V Output Low Voltage V Output High Current I

Output Low Current I

Rise Time

Fall Time

Duty Cycle

Skew

1

Jitter

1

Guaranteed by design, not 100% tested in production.

0721A—07/29/03

OH1

OL1 OH1 OL1

t

r1

t

f1

d

t

sk1

t

jcyc-cyc

t1

IOH = -18 mA 2.1 V IOL = 9.4 mA 0.4 V VOH = 2.0 V -22 mA VOL = 0.8 V 16 57 mA VOL = 0.4 V, VOH = 2.4 V 1.96 2 ns VOH = 2.4 V, VOL = 0.4 V 1.95 2 ns VT = 1.5 V 45 51.6 55 % VT = 1.5 V 70 500 ps VT = 1.5 V

100 500 ps

20

Integrated

1

p

g

(

)

(

)

r

ICS952011

Circuit Systems, Inc.

Electrical Characteristics - CPUCLKT/C

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current Source

Out

ut Impedance

Volta

e HighVHi

e Low VLow -150 9 150

Volta Max Volta

Min Volta

e Vovs 775 1150

e Vuds -450 -3

Crossing Voltage

abs

Crossing Voltage

var

Rise Time

Fall Time

Rise Time Variation

Fall Time Variation

Duty Cycle

Skew

Jitter, Cycle to cycle

Vcross(abs) 250 386 550 mV

1

Zo

Statistical measurement on single ended

h 660 757 850

VO = V

x

3000

signal using oscilloscope math function.

Measurement on single ended signal using

absolute value.

d-Vcross Variation of crossing over all edges 42 140 mV

t

d-t d-t

d

t

sk3

t

jcyc-cyc

f

t3

1

VOL = 0.175V, VOH = 0.525V

VOH = 0.525V VOL = 0.175V

175 300 700 ps 175 280 700 ps

125 ps 125 ps

Measurement from differential wavefrom 45 50 55 %

VT = 50% VT = 50%

32 100 ps 43 150 ps

Electrical Characteristics - ZCLK

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency F

Output Impedance R Output High Voltage V Output Low Voltage V Output High Current

Output Low Current

Rise Time t

Fall Time t

Duty Cycle

Skew t

Jitter

O1

DSP1

OH

OL

I

OH

I

OL

r1 f1

d

t1

sk1

t

jcyc-cyc

1

VO = VDD*(0.5) 12 55 Ω

1

IOH = -1 mA 2.4 V

1

IOL = 1 mA 0.55 V

1

V

1

V

1 1

1

OL @MIN

VOL = 0.4 V, VOH = 2.4 V 0.5 1.36 2 ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.37 2 ns VT = 1.5 V 45 52.3 55 VT = 1.5 V 15 250 ps VT = 1.5 V 3V66

OH@MIN

= 1.0 V, V

= 1.95 V, V

OH@MAX

OL @MAX

= 3.135 V -33 -33

= 0.4 V 30 38

201 250 ps

Ω

mV

MHz

mA mA

%

0721A—07/29/03

21

Integrated

1

jcy

ICS952011

Circuit Systems, Inc.

Electrical Characteristics - AGPCLK

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency F

Output Impedance R Output High Voltage V Output Low Voltage V Output High Current

Output Low Current

Rise Time t

Fall Time t

Duty Cycle

Skew t

Jitter

O1

DSP1

OH

OL

I

OH

I

OL

r1 f1

d

t1

sk1

t

jcyc-cyc

1

VO = VDD*(0.5) 12 55 Ω

1

IOH = -1 mA 2.4 V

1

IOL = 1 mA 0.55 V

1

V

1

V

1 1

1

OL @MIN

VOL = 0.4 V, VOH = 2.4 V 0.5 1.83 2 ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.69 2 ns VT = 1.5 V 45 52.7 55 VT = 1.5 V 32 250 ps VT = 1.5 V 3V66

OH@MIN

= 1.0 V, V

= 1.95 V, V

OH@MAX

OL @MAX

= 3.135 V -33 -33

= 0.4 V 30 38

240 250 ps

Electrical Characteristics - 12_48MHz, 24_48MHz

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

Fall Time

Duty Cycle

Jitter

1

Guaranteed by design, not 100% tested in production.

R

t

DSP1

V

I

OH

I

OL

t t

d

OH

OL

1

r1

1

f1

t1

c-cyc

1

VO = VDD*(0.5)

1

IOH = -1 mA

1

IOL = 1 mA V

1

V V

1

OL @MIN

V

OL @MAX

OH@MIN

OH@MAX

= 1.0 V

= 3.135 V

= 1.95 V

= 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V

1

VT = 1.5 V VT = 1.5 V

20 60

2.4 V

0.4 V

-29

-23 mA

29

27 mA

0.5 1.27 1 ns

0.5 1.4 1 ns 45 52.7 55 %

268 350 ps

MHz

mA mA

%

Ω

Electrical Characteristics - REF

TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V Output Low Voltage V Output High Current I

Output Low Current I

Rise Time

Fall Time

Duty Cycle

Jitter

0721A—07/29/03

1

OH5

OL5 OH5 OL5

t

r5

t

f5

d

t5

t

jcyc-cyc5

IOH = -12 mA 2.6 V IOL = 9 mA 0.4 V VOH = 2.0 V -22 mA VOL = 0.8 V 16 mA VOL = 0.4 V, VOH = 2.4 V 1.98 4 ns VOH = 2.4 V, VOL = 0.4 V 1.87 4 ns VT = 1.5 V 45 54.2 55 % VT = 1.5 V

213 1000 ps

22

Integrated Circuit Systems, Inc.

Shared Pin Operation Input/Output Pins

ICS952011

The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads.

T o progr am (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) powe r supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period.

Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.

0721A—07/29/03

Programming Header

Via to Gnd

Device Pad

Via to VDD

2K 

8.2K  Clock trace to load

Series Term. Res.

Fig. 1

23

Integrated

ICS952011

Circuit Systems, Inc.

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_ST OP# setup time tsu is 10 ns, for tr ansitions to be recognized by the ne xt rising edge.

Assertion of PCI_STOP# Wavef orms

PCI_STOP#

PCI_F 33MHz

PCI 33MHz

tsu

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I of CPU_STOP# are to be stopped after their next tr ansition follo wing the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values . The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.

Assertion of CPU_STOP# Wavef orms

2

C configuration to be stoppable via assertion

CPU_STOP#

CPUT

CPUC

CPU_STOP# Functionality

#POTS_UPCTUPCCUPC

1lamroNlamroN

0tluM*feritaolF

0721A—07/29/03

24

Integrated

INDEX AREA

SEATING PLANE

.10 (.004) C

Circuit Systems, Inc.

ICS952011

INDEX AREA

N

c

SYMBOL

L

In Millimeters In Inches

COM M O N DIM ENS IONS CO MMO N DIM ENSI O NS

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

E1

E

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010

1 2

D E 10.03 10.68 .395 .420

D

h x 45°

α

E1 7.40 7.60 .291 .299

e

SEE VARIATIONS SEE VARIATIONS

0.635 BASIC 0.025 BASIC h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040

A

A1

- C -

e

b

SEATING PLANE

.10 (.004) C

N

SEE VARIATIONS SEE VARIATIONS

α 0° 8° 0° 8°

VARIATIONS

N

D mm. D (inc h)

MIN MAX MIN MAX

48 15.75 16.00 .620 .630

Ref erence Doc.: JEDEC Publication 95, M O-118 10-0034

Ordering Information

ICS952011yFT

Example:

ICS XXXXXX y F - T

0721A—07/29/03

Designation for tape and reel packaging Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision) Device Type Prefix

ICS = Standard Device

25