Datasheet AV9250F-25-T, ICS9250F-25-T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS9250-25

Third party brands and names are the property of their respective owners.

Block Diagram

9250-25 Rev A 10/03/00

Pin Configuration

Recommended Application:

810/810E and Solano type chipset

Output Features:

• 2 - CPUs @ 2.5V, up to 153.33MHz.

• 13 - SDRAM @ 3.3V, up to 153.33MHz.

• 3 - 3V66 @ 3.3V, 2x PCI MHz.

• 8 - PCI @3.3V.

• 1 - 48MHz, @3.3V fixed.

• 1 - 24MHz @ 3.3V

• 1 - REF @3.3V, 14.318MHz.

Features:

• Up to 153.33MHz frequency support

• Support power management through PD#.

• Spread spectrum for EMI control (± 0.25%)
center spread.

• Uses external 14.318MHz crystal

• FS pins for frequency select

Key Specifications:

• CPU Output Jitter: <250ps

• IOAPIC Output Jitter: <500ps

• 48MHz, 3V66, PCI Output Jitter: <500ps

• Ref Output Jitter. <1000ps

• CPU Output Skew: <175ps

• PCI Output Skew: <500ps

• 3V66 Output Skew <175ps

• For group skew timing, please refer to the
Group Timing Relationship Table.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

56-Pin 300 mil SSOP

1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.

SDATA

SCLK

PLL2

PLL1

Spread

Spectrum

48MHz
24MHz

CPUCLK [1:0]

2

12

8

3

SDRAM [11:0]

IOAPIC

PCICLK [7:0]

SDRAM_F

3V66 [2:0]

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM
DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

FS[4:0]

PD#

Control

Logic

Config.

Reg.

/ 2

REF0

VDDREF

X1
X2

GNDREF

GND3V66

3V66-1
3V66-2

VDD3V66

VDDPCI
*FS0/PCICLK0
*FS1/PCICLK1

PCICLK2

GNDPCI
PCICLK3
PCICLK4
PCICLK5

VDDPCI
PCICLK6
PCICLK7

GNDPCI

PD#

SCLK

SDATA

VDDSDR

SDRAM11
SDRAM10

GNDSDR

3V66-0

1
1

REF0/FS4*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24MHz/FS2*
48MHz/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR

1

1

ICS9250-25

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

Preliminary Product Preview

PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.

2

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

NIP

REBMUN

EMANNIPEPYTNOITPIRCSED

,52,81,01,9,1

54,73,33,23

DDVRWPylppusrewopV3.3

21XNI

kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

32XTUO

daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

)Fp33(pac

,12,41,5,4

,63,92,82

94,14

DNGRWPylppusV3.3rofsnipdnuorG

6,7,8]0:2[66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3

11

0KLCICP

1

TUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

0SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

21

1KLCICP

1

NISKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

1SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

,61,71,91,02

31,51

]2:7[KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

22#DPNI

otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola

ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht

.sm3nahtretaerg

32KLCSNIIfotupnikcolC

2

tupniC

42ATADSNIIroftupniataD

2

.tupnilairesC

43

zHM84TUOBSUroftuptuokcolczHM84dexiFV3.3

3SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

53

2SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

zHM42TUOtuptuozHM42dexifV3.3

83F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3

2

C

,34,44,74,84
,13,93,04,24

62,72,03,03

]0:11[MARDSTUO

ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3

Ihguorht

2

C

05LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG

25,15]0:1[KLCUPCTUO.snipSFmorfdeviredycneuqerftuptuO.tuptuokcolcsubtsoHV5.2
55,35LDDVRWPCIPAOI,UPCrofylppyusrewopV5.2

45CIPAOITUO.zHM76.61tagninnurstuptuokcolcV5.2
65

4SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

0FER

1

TUO.tuptuokcolcecnereferzHM813.41,V3.3

The ICS9250-25 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system.

Spread spectrum may be enabled through I

2

C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-25 employs a proprietary
closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I

2

C interface allows changing functions, stop clock programming and frequency selection.

3

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Frequency Selection

Clock Enable Configuration

4SF3SF2SF1SF0SF

UPC

zHM

MARDS

zHM

zHM66V3

ICP

zHM

zHMCIPAOI

00000 00.5505.2800.555.7257.31
00001 00.0600.0900.060351
00010 08.6602.00108.664.337.61
00011 33.8605.20133.86561.435280.71
00100 00.0700.50100.07535.71
00101 00.2700.80100.276381
00110 00.5705.21100.575.7357.81
00111 00.7705.51100.775.8352.91
01000 03.3803.3835.558.729.31
01001 00.0900.0900.060.030.51
01010 03.00103.00178.664.337.61
01011 00.30100.30176.863.432.71
01100 05.21105.21100.575.738.81
01101 00.51100.51176.673.832.91
01110 00.02100.02100.080.040.02
01111 00.52100.52133.387.148.02

10000 00.82100.82100.460.230.61
1000 1 00.03100.03100.565.233.61
100 10 07.33107.33158.664.337.61
100 11 00.73100.73105.863.431.71
10 100 00.04100.04100.070.535.71
10 10 1 00.54100.54105.273.631.81
10 110 00.05100.05100.575.738.81
10111 33.35133.35176.673.832.91
11000 00.52157.3905.263.136.51
11001 00.03105.7900.565.233.61
11010 07.33182.00158.664.337.61
11011 00.73157.20105.863.431.71
11100 00.04100.50100.070.535.71
11101 00.54157.80105.273.631.81
11110 00.05105.21100.575.738.81
11111 33.35100.51176.673.832.91

#DPKLCUPCMARDSCIPAOIzHM66KLCICP

,FER

zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONO

4

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)

Notes:

1.

Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

2. The I

2

C readback for Bit 2, 7:4 indicate the revision code.

tiB

noitpircseD

DWP

tiB

)4:7,2(

)4:7,2(tiB

KLCUPC

zHM

MARDS

zHM

66V3
zHM

KLCICP

CIPAOI

zHM

10000

1etoN

00000 00.5505.2800.555.7257.31
00001 00.0600.0900.060351
00010 08.6602.00108.664.337.61
00011 33.8605.20133.86561.435280.71
00100 00.0700.50100.07535.71
00101 00.2700.80100.276381
00110 00.5705.21100.575.7357.81
00111 00.7705.51100.775.8352.91
01000 03.3803.3835.558.729.31
01001 00.0900.0900.060.030.51
01010 03.00103.00178.664.337.61
01011 00.30100.30176.863.432.71
01100 05.21105.21100.575.738.81
01101 00.51100.51176.673.832.91
01110 00.02100.02100.080.040.02
01111 00.52100.52133.387.148.02
10000 00.82100.82100.460.230.61
1000 1 00.03100.03100.565.233.61
10010 07.33107.33158.664.337.61
10011 00.73100.73105.863.431.71
10100 00.04100.04100.070.535.71
1010 1 00.54100.54105.273.631.81
10110 00.05100.05100.575.738.81
10111 33.35133.35176.673.832.91
11000 00.52157.3905.263.136.51
11001 00.03105.7900.565.233.61
11010 07.33182.00158.664.337.61
11011 00.73157.20105.863.431.71
11100 00.04100.50100.070.535.71
11101 00.54157.80105.273.631.81
11110 00.05105.21100.575.738.81
11111 33.35100.51176.673.832.91

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

4:6,2tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

daerpSretneC%52.0±elbanemurtcepsdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

5

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte 1: Control Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

tiB#niPDWPnoitpircseD

7tiB-X #3SF
6tiB-X #0SF
5tiB-X #2SF
4tiB531 zHM42
3tiB-1 )devreseR(
2tiB431 zHM84
1tiB-1 )devreseR(
0tiB831 F_MARDS

tiB#niPDWPnoitpircseD

7tiB021 7KLCICP
6tiB911 6KLCICP
5tiB711 5KLCICP
4tiB611 4KLCICP
3tiB511 3KLCICP

2tiB31

1

2KLCICP

1tiB211 1KLCICP
0tiB111 0KLCICP

Byte 3: Control Register
(1 = enable, 0 = disable)

Byte 2: Control Register
(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB931 7MARDS
6tiB041 6MARDS
5tiB241 5MARDS
4tiB341 4MARDS
3tiB441 3MARDS

2tiB64

1

2MARDS

1tiB741 1MARDS
0tiB841 0MARDS

tiB#niPDWPnoitpircseD

7tiB81 2_66V3
6tiB61 0_66V3
5tiB71 1_66V3
4tiB-X #4SF
3tiB451 CIPAOI
2tiB-X #1SF
1tiB151 1KLCUPC
0tiB251 0KLCUPC

Byte 4: Control Register
(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB621 11MARDS
2tiB721 01MARDS

1tiB031 9MARDS

0tiB131 8MARDS

Byte 5: Control Register
(1 = enable, 0 = disable)

Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)

Note: Dont write into this register, writing into this register

can cause malfunction

tiB#niPDWPnoitpircseD

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

6

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Cha ra cteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unles s othe rwis e s ta ted)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage V

IH

2V

DD

+0.3 V

Input L ow Voltage V

IL

VSS-0.3 0.8 V

Input High Curr ent I

IH

VIN = V

DD

-5 5

µ

A

Input L ow Curr e nt I

IL1

VIN = 0 V; Inputs with no pull-up resistors -5

µ

A

Input L ow Curr e nt I

IL2

VIN = 0 V; Inputs with pull-up re s is t ors -200

µ

A

Operating I

DD3.3OP

CL = 0 pF; Select @ 66 M 100 mA

Sup pl y C urr e nt

Power Down I

DD3.3PD

CL = 0 pF ; With input addres s to Vdd or GND 600

µ

A

Sup pl y C urr e nt

In put fre q ue n cy F

i

VDD = 3.3 V; 14.318 MHz

Pin Inductance L

p

in

7nH

Input Capa cita nce

1

C

IN

Logic I nputs 5 pF

C

out

Out put pin capacita nce 6 pF

C

INX

X1 & X2 pins 27 45 pF

Transition Time

1

T

trans

To 1st crossing of ta rget Fr eq. 3 mS

Settling Time

1

T

s

From 1st crossing to 1% target Fr e q. 3 mS

Clk Stabilization

1

T

STAB

From VDD = 3.3 V to 1% target Fr e q. 3 mS

Delay t

PZH,tPZH

output enable delay (a ll outputs) 1 10 nS

t

PLZ,tPZH

output disable delay ( a ll outputs) 1 10 nS

1

Gua r e ntee d by des ign, not 100% tested in produc tion.

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V

DD

+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Group Timing Relationship Table

1

puorGzHM66UPC

zHM001MARDS

zHM001UPC

zHM001MARDS

zHM331UPC

zHM001MARDS

zHM331UPC

zHM331MARDS

tesffOecnareloTtesffOecnareloTtesffOecnareloTtesffOecnareloT

MARDSotUPCsn5.2sp005sn0.5sp005sn0.0sp005sn57.3sp005

66V3otUPCsn5.7sp005sn0.5sp005sn0.0sp005sn0.0sp005

66V3otMARDSsn0.0sp005sn0.0sp005sn0.0sp005sn57.3sp005

ICPot66V3sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005

ICPotICPsn0.0sn0.1sn0.0sn0.1sn0.0sn0.1sn0.0sn0.1

TOD&BSUhcnysAA/NhcnysAA/NhcnysAA/NhcnysAA/N

7

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - 3V66

TA = 0 - 70C; VDD = 3.3 V +/-5 % ; CL = 1 0-30 pF (unless oth erw is e s ta te d)

PARA METER SYMBOL COND ITI ONS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impe da nc e R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

O utput High Cur r e nt I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V-33 -33 mA

O utput L o w Cur rent I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2 . 4 V 0.4 1.6 ns

F all T ime t

f1

1

VOH = 2.4 V, VOL = 0 . 4 V 0.4 1.6 ns

Duty Cycle d

t1

1

VT = 1.5 V 45 55 %

Skew t

sk1

1

VT = 1.5 V 175 ps

Jitter t

jcyc-cyc

VT = 1.5 V 500 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - CPU

TA = 0 - 70C, V

DDL

= 2.5 V +/-5 % ; CL = 1 0 - 20 pF (unless othe rwis e stated)

PARA METER SYMBOL COND ITI ONS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP2B

1

VO = VDD*(0.5) 13.5 45

Ω

O utput Impe da nc e R

DSN2B

1

VO = VDD*(0.5) 13.5 45

Ω

Output High Voltage V

OH2B

IOH = -1 mA 2 V

Output Low Voltage V

OL2B

IOL = 1 mA 0.4 V

O utput High Cur r e nt I

OH2B

V

OH @MIN

= 1.0V , V

OH@ MAX

= 2 . 375 V -27 -27 mA

O utput Low C urrent I

OL2B

V

OL @MIN

= 1. 2V , V

OL@ MAX

= 0. 3 V 27 30 mA

Rise Time t

r2B

1

VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 ns

F all T ime t

f2B

1

VOH = 0.4 V, VOL = 2 . 0 V 0.4 1.6 ns

Duty Cycle d

t2B

1

VT = 1.25 V 455055ns

Skew t

sk2B

1

VT = 1.25 V 175 ps

t

jcyc-cyc

1

VT = 1.25 V 250 ps

Jitter

1

G ua renteed by de s ign, not 100% te s te d in production.

8

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - IOAPIC

TA = 0 - 70C;V

DDL

= 2. 5 V +/-5%; CL = 10 - 20 pF (unless otherwise s ta ted)

PARA METER SYMBOL COND ITI O NS MIN TYP MAX U N I TS

O utput Impe da nc e R

DSP4B

1

VO = VDD*(0.5) 9 30

Ω

O utput Impe da nc e R

DSN4B

1

VO = VDD*(0.5) 9 30

Ω

Output High Voltage V

OH4\ BIOH

= -5.5 mA 2 V

Output Low Voltage V

OL4B

IOL = 9. 0 mA 0.4 V

O utput High Cur r e nt I

OH4B

V

OH@ min

= 1.4 V, V

OH@ MAX

= 2 . 5 V -36 - 21 m A

O utput Low C urrent I

OL4B

V

OL@ MIN

= 1.0 V, V

OL@ MAX=

0.2 36 31 mA

Rise Time t

r4B

1

VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 nS

F all Time t

f4B

1

VOH = 2.0 V, VOL = 0 . 4 V 0.4 1.6 nS

Duty Cycle d

t4B

1

VT = 1.25 V 45 55 %

Jitter t

jcyc-cyc

VT = 1.25 V 500 pS

1

G ua r e nte e d by d esign, not 100% te s te d in production.

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)

PARA METER SYMBOL COND ITI ONS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP3

1

VO = VDD*(0.5) 10 24

Ω

O utput Impe da nc e R

DSN3

1

VO = VDD*(0.5) 10 24

Ω

Output High Voltage V

OH3

IOH = -1 mA 2.4 V

Output Low Voltage V

OL3

IOL = 1 mA 0.4 V

O utput High Cur r e nt I

OH3

V

OH @MIN

= 2.0 V, V

OH@ MAX

=3.135 V -54 - 46 mA

Output Low Current I

OL3

V

OL@ MIN

= 1.0 V, V

OL@ MAX

=0.4 V 54 53 mA

Rise Time T

r3

1

VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns

Fa ll T ime T

f3

1

VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns

Duty Cycle D

t3

1

VT = 1.5 V 45 55 %

Skew T

sk3

1

VT = 1.5 V 250 ps

Jitter t

j

cyc-cyc VT = 1.5 V 250 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

9

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - PCI

TA = 0 - 70C; VDD = 3.3 V +/-5 % ; CL = 1 0-30 pF (unless oth erw is e s ta te d)

PARA METER SYMBOL COND ITI ONS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impe da nc e R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

O utput High Cur r e nt I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V-33 -33 mA

O utput L o w Cur rent I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2.4 V 0.5 2 ns

F all T ime t

f1

1

VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle d

t1

1

VT = 1.5 V 45 55 %

Skew t

sk1

1

VT = 1.5 V 500 ps

Jitter t

jcyc-cyc

VT = 1.5 V 500 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - 48M, REF

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise st a t e d)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utp ut Impe dance R

DSP5

1

VO = VDD*(0.5) 20 60

Ω

O utp ut Impe dance R

DSN5

1

VO = VDD*(0.5) 20 60

Ω

Output High Voltage V

OH5

IOH = 1 mA 2.4 V

Output Low Voltage V

OL5

IOL = -1 mA 0.4 V

O utput High Current I

OH5

V

OH @MIN

=1 V, V

OH@MAX

= 3.135 V -29 - 23 m A

Ou tput Low Cu rre nt I

OL5

V

OL@MIN

=1.95 V, V

OL@MIN

=0.4 V 29 27 mA

Rise Time t

r5

1

VOL = 0.4 V, VOH = 2.4 V 1.8 4 nS

Fall Time t

f5

1

VOH = 2.4 V, VOL = 0.4 V 1.7 4 nS

Duty Cycle d

t5

1

VT = 1.5 V 45 55 %

Jitter t

jcyc-cyc

1

VT = 1.5 V ; Fixed Cloc ks 500 pS

t

jcyc-cyc

1

VT = 1.5 V ; R e f Clocks

1000 pS

1

G ua renteed by design, not 100% t e sted in production.

10

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.

 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

11

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Fig. 1

Shared Pin Operation ­Input/Output Pins

The I/O pins designated by (input/output) on the ICS9250-25
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5­bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.

Via to
VDD

Clock trace to load

Series Term.Res.

Programming
Header

Via to Gnd

Device
Pad

2K 

8.2K 

Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.

12

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

13

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Group Offset Waveforms

Cycle Repeats

0ns

CPU 66MHz

CPU 100MHz

CPU 133MHz

SDRAM 133MHz

SDRAM 100MHz

3.5V 66MHz

PCI 33MHz

APIC 33MHz

REF 14.318MHz

USB 48MHz

10ns 20ns 30ns 40ns

14

ICS9250-25

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.

Ordering Information

ICS9250yF-25-T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T

MIN MAX MIN MAX

A 2.413 2.794 .095 .110

A1 0.203 0.406 .008 .016

b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420

E1 7.391 7.595 .291 .299

e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N

α

0° 8° 0° 8°

VARIATIONS

MIN MAX MIN MAX

56 18.288

18.542

.720 .730

JEDEC MO-118

DOC# 10-0034

6/1/00
REV B

N

D mm.

D (inch)

SEE VARIATIONS

SYMBOL

SEE VARIATIONS

SEE VARIATIONS

In Millimeters

COMMON DIMENSIONS

In Inches

COMMON DIMENSIONS

SEE VARIATIONS