Page 1
Integrated
Circuit
Systems, Inc.
ICS9248-97
Block Diagram
Frequency Timing Generator for PENTIUM II Systems
9248-97 Rev E 08/18/00
Pin Configuration
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Recommended Application:
Camino chipset
Output Features:
3 - CPUs @ 2.5V, up to 180MHz.
3 - IOAPIC @ 2.5V, PCI/2
3 - 3V66MHz @ 3.3V.
11 - PCIs @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz, @ 3.3V
1 - CPU/2, @ 2.5V.
Features:
Up to 180MHz frequency support
Support power management: Power down Mode
from I2C programming.
Spread spectrum for EMI control
± 0.25% center spread).
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
SEL24_48#
S DATA
SCLK
FS (4:0)
PD#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
IOAPIC (2:0)
PCICLK (9:0)
CPU/2
PCICLK_F
3V66 (2:0)
X1
X2
XTAL
OSC
CPU
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
Control
Logic
Config.
Reg.
/ 2
/ 2
REF (1:0)
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK_F
*FS1/PCICLK0
VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PCICLK7
PCICLK8
PCICLK9
VDDPCI
PD#
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU/2
CPU/2
GNDLCPU/2
CPUCLK0
VDDLCPU
CPUCLK1
CPUCLK2
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
S DATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48
ICS9248-97
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9248-97
Pin Descriptions
The ICS9248-97 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-97
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
The CPU/2 clocks are inputs to the DRCG.
General Description
Pin numbe r Pin name Type Descri p tion
1, 7, 13, 19, 25, 31 GND PWR Ground pins
2 REF0 OUT 14.318MHz reference clock outputs at 3.3V
REF1 OUT 14.318MHz reference clock outputs at 3.3V
SEL24_48 IN Logic input to select 24 or 48MHz for pin 26 output
4, 10, 16, 23,
28, 35
VDD PWR Power pins 3.3V
5 X1 IN XTAL_IN 14.318MHz crystal input
6 X2 OUT XTAL_OUT Crystal output
PCICLK_F OUT
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected b
y
the PCI_STOP# input.
FS0 IN Logic - input for frequency selection
PCICLK0 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS1 IN Logic - input for frequency selection
PCICLK1 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS2 IN Logic - input for frequency selection
PCICLK2 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS3 IN Logic - input for frequency selection
22, 21, 20, 18, 17,
15, 14
PCICLK (9:3) OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.
24 PD# IN
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
26 24_48MHz OUT
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
48MHz OUT/IN Fixed 48MHz clock output. 3.3V
FS4 IN Logic - input for frequency selection
29 SCLK IN
Clock in
p
ut of I2C input
30 SDATA IN
Data in
p
ut for I2C serial input.
32, 33, 34 3V66 (2:0) OUT
3.3V clock outputs. These outputs are stopped when CPU_STOP#
is driven active..
36 GNDLCPU PWR Ground pin for the CPUCLKs
37, 38, 40 CPUCLK (2:0) OUT Host bus clock output at 2.5V.
39 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V
41 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks.
42 CPU/2 OUT 2.5V clock outputs at 1/2 CPU frequency.
43 VDDLCPU/2 PWR Power pin for the CPU/2 clocks. 2.5V
45 GNDLAPIC PWR Ground pin for the IOAPIC outputs.
44, 46, 47 IOAPIC (2:0) OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.
48 VDDLAPIC PWR Power pin for the IOAPIC outputs. 2.5V.
27
12
3
8
9
11
Page 3
3
ICS9248-97
Functionality
FS4 FS3 FS2 FS1 FS0 CPU CPU/2 PCI 3V 6 6 IOAPI C
0 0 0 0 0 103.0 51.50 34.33 68.67 17.17
0 0 0 0 1 105.0 52.50 35.00 70.00 17.50
0 0 0 1 0 100.3 50.15 33.43 66.87 16.72
0 0 0 1 1 100.9 50.45 33.63 67.27 16.82
0 0 1 0 0 107.0 53.50 35.67 71.33 17.83
0 0 1 0 1 109.0 54.50 36.33 72.67 18.17
0 0 1 1 0 112.0 56.00 37.33 74.67 18.67
0 0 1 1 1 114.0 57.00 38.00 76.00 19.00
0 1 0 0 0 116.1 58.50 38.70 77.40 19.35
0 1 0 0 1 118.0 59.00 39.33 78.67 19.67
0 1 0 1 0 133.3 66.65 33.33 66.65 16.66
0 1 0 1 1 120.0 60.00 40.00 80.00 20.00
0 1 1 0 0 122.0 61.00 40.67 81.33 20.33
0 1 1 0 1 125.1 62.55 41.70 83.40 20.85
0 1 1 1 0 128.2 64.10 42.73 85.47 21.37
0 1 1 1 1 130.0 65.00 43.33 86.67 21.67
1 0 0 0 0 133 66.5 44.33 88.67 22.17
1 0 0 0 1 133.9 66.95 33.48 66.95 16.74
1 0 0 1 0 138 69 34.5 69 17.25
1 0 0 1 1 142 71 35.5 71 17.75
1 0 1 0 0 146 73 36.5 73 18.25
1 0 1 0 1 150 75 37.5 75 18.75
1 0 1 1 0 153 76.5 38.25 76.5 19.13
1 0 1 1 1 156 78 39 78 19.5
1 1 0 0 0 159.1 79.55 39.78 79.55 19.89
1 1 0 0 1 162 81 40.5 81 20.25
1 1 0 1 0 165 82.5 41.25 82.5 20.63
1 1 0 1 1 168 84 42 84 21
1 1 1 0 0 171 85.5 42.75 85.5 21.38
1 1 1 0 1 174 87 43.5 87 21.75
1 1 1 1 0 177 88.5 44.25 88.5 22.13
1 1 1 1 1 180 90 45 90 22.5
Page 4
4
ICS9248-97
Byte 0: Functionality and frequency select register (Default = 0)
Serial Configuration Command Bitmap
Note 1:
Default at power-up will be for latched logic inputs to define frequency.
tiBnoitpircseDDWP
tiB
)4:7,2(
2tiB
4SF
7tiB
3SF
6tiB
2SF
5tiB
1SF
4tiB
0SF
UPC2/UPCICP66V3CIPAOI
devreseR
1etoN
00000 0.30105.1533.4376.8671.71
00001 0.50105.2500.5300.0705.71
00010 54.00132.0584.3379.6647.61
00011 9.00154.0536.3372.7628.61
00100 1.70155.3507.5304.1758.71
00101 0.90105.4533.6376.2771.81
00110 0.21100.6533.7376.4776.81
00111 0.41100.7500.8300.6700.91
01000 1.61105.8507.8304.7753.91
01001 0.81100.9533.9376.8776.91
01010 3.33156.6633.3356.6666.61
01011 0.02100.0600.0400.0800.02
01100 0.22100.1676.0433.1833.02
01101 1.52155.2607.1404.3858.02
01110 12.82111.4647.2474.5873.12
01111 0.03100.5633.3476.6876.12
10000 0.33105.6633.4476.8871.22
10001 9.33159.6684.3359.6647.61
10010 0.83100.9605.4300.9652.71
10011 0.24100.1705.5300.1757.71
10100 0.64100.3705.6300.3752.81
10101 0.05100.5705.7300.5757.81
10110 0.35105.6752.8305.6731.91
10111 0.65100.8700.9300.8705.91
11000 1.95155.9787.9355.9798.91
11001 0.26100.1805.0400.1852.02
11010 0.56105.2852.1405.2836.02
11011 0.86100.4800.2400.4800.12
11100 0.17105.5857.2405.5883.12
11101 0.47100.7805.3400.7857.12
11110 0.77105.8852.4405.8831.22
11111 0.08100.0900.5400.0905.22
3tiB
stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
delbanemurtcepsdaerpS-1
0
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Page 5
5
ICS9248-97
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB041 0KLCUPC
6tiB831 1KLCUPC
5tiB731 2KLCUPC
4tiB241 2/UPC
3tiB741 0CIPAOI
2tiB641 1CIPAOI
1tiB441 2CIPAOI
0tiB-X )devreseR(
tiB#niPDWPnoitpircseD
7tiB811 6KLCICP
6tiB711 5KLCICP
5tiB511 4KLCICP
4tiB411 3KLCICP
3tiB211 2KLCICP
2tiB111 1KLCICP
1tiB91 0KLCICP
0tiB81 F_KLCICP
tiB#niPDWPnoitpircseD
7tiB431 0_66V3
6tiB331 1_66V3
5tiB231 2_66V3
4tiB-X#1SF
3tiB311FER
2tiB210FER
1tiB-X#3SF
0tiB-X#2SF
tiB#niPDWPnoitpircseD
7tiB621 zHM84_42
6tiB721 zHM84
5tiB-X#0SF
4tiB-1 )devreseR(
3tiB221 9KLCICP
2tiB121 8KLCICP
1tiB021 7KLCICP
0tiB-X#4SF
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this register
can cause malfunction
tiB#niPDWPnoitpircseD
7tiB-1 )etoN(devreseR
6tiB-1 )etoN(devreseR
5tiB-1 )etoN(devreseR
4tiB-1 )etoN(devreseR
3tiB-1 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-1 )etoN(devreseR
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Page 6
6
ICS9248-97
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
0.1 5
µ
A
Input Low Current I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5 2.0
µ
A
Input Low Current I
IL2
VIN = 0 V; Inputs with pull-up resistors -200 -100
µ
A
Operating I
DD3.3OP100CL
= 0 pF; Select @ 100 MHz 71 160 mA
Supply Current I
DD3.3OP133CL
= 0 pF; Select @ 133 MHz 76 160 mA
Input frequency F
i
VDD = 3.3 V; 11 14.318 16 MHz
Input Capacitance
1
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 36 45 pF
Transition Time
1
T
trans
To 1st crossing of target Freq. 3 ms
Settling Time
1
T
s
From 1st crossing to 1% target Freq. 5 ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq.
3ms
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - I nput/ Suppl y/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating I
DD2.5OP100CL
= 0 pF; Select @ 100 MHz 14.5 75 mA
Supply Current I
DD2.5OP133CL
= 0 pF; Select @ 133 MHz 17.5 90 mA
Power Down I
DD2.5PD
CL = 0 pF; PWRDWN# = 0 136 300
µ
A
Supply Curren
t
1
Guaranteed by design, not 100% tested in production.
Page 7
7
ICS9248-97
Group Offset
Group Offset Measurement Loads Measure Points
CPU to 3V66 0.0-1.5ns CPU leads CPU @ 20pF, 3V66 @ 30pF CPU @1.25V, 3V66 @ 1.5V
3V66 to PCI 1.5-4.0ns 3V66 leads 3V66 @ 30pF, PCI @ 30pF 3V66 @ 1.5V, PCI @ 1.5V
CPU to IOAPIC 1.5-4.0ns CPU leads CPU @ 20pF, IOAPIC @ 20pF CPU @1.25V, IOAPIC @ 1.5V
Note: 1. All offsets are to be measured at rising edges.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
VO = V
DD
*(0.5) 13.5 30 45 Ω
Output Impedance R
DSN2B
1
VO = V
DD
*(0.5) 13.5 32 45 Ω
Output High Voltage V
OH2BIOH
= -12.0 mA 2 2.24 V
Output Low Voltage V
OL2BIOL
= 12.0 mA 0.31 0.4 V
Output High Current I
OH2B
VOH = 1.7 V -31 -19 mA
Output Low Current I
OL2B
VOL = 0.7 V 19 25 mA
Rise Time t
r2B
1
VOL = 0.4 V, VOH = 2.0 V 1.47 1.8 ns
Fall Time t
f2B
1
VOH = 2.0 V, VOL = 0.4 V 1.51 1.8 ns
V
T
= 1.25 V CPU Frequencies: 100 to 159MHz 45 50.5 55
V
T
= 1.25 V CPU Frequencies: 162 to 180MHz 41 47.5 51
Skew t
sk2B
1
VT = 1.25 V 27 175 ps
Jitter, Cycle-to-cycle
t
jcyc-cyc2B
1
VT = 1.25 V
218 300 ps
1
Guaranteed by design, not 100% tested in production.
Duty Cycle
d
t2B
1
%
Electrical Characteristics - CPU/2
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
VO = V
DD
*(0.5) 13.5 30 45 Ω
Output Impedance R
DSN2B
1
VO = V
DD
*(0.5) 13.5 31 45 Ω
Output High Voltage V
OH2BIOH
= -12.0 mA 2 2.2 V
Output Low Voltage V
OL2BIOL
= 12.0 mA 0.31 0.4 V
Output High Current I
OH2B
VOH = 1.7 V -31 -19 mA
Output Low Current I
OL2B
VOL = 0.7 V 19 26 mA
Rise Time t
r2B
1
VOL = 0.4 V, VOH = 2.0 V 1.21 1.6 ns
Fall Time t
f2B
1
VOH = 2.0 V, VOL = 0.4 V 1.17 1.6 ns
Duty Cycle d
t2B
1
VT = 1.25 V 45 48.6 55 %
Jitter, Cycle-to-cycle
t
jcyc-cyc2B
1
VT = 1.25 V
227 250 ps
1
Guaranteed by design, not 100% tested in production.
Page 8
8
ICS9248-97
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
VO = V
DD
*(0.5) 12 24.19 55 Ω
Output Impedance R
DSN1
1
VO = V
DD
*(0.5) 12 23.08 55 Ω
Output High Voltage V
OH1
IOH = -11 mA 2.4 3.1 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.17 0.4 V
Output High Current I
OH1
VOH = 2.0 V -51 -22 mA
Output Low Current I
OL1
VOL = 0.8 V 16 41 mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.49 2 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.52 2 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 49 55 %
Skew
1
t
sk1
VT = 1.5 V 92 250 ps
Jitter, Cycle-to-cycle
1
T
jcyc-cyc1
VT = 1.5 V
173 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
VO = V
DD
*(0.5) 12 24 55 Ω
Output Impedance R
DSN1
1
VO = V
DD
*(0.5) 12 23 55 Ω
Output High Voltage V
OH1
IOH = -11 mA 2.4 3.1 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.16 0.4 V
Output High Current I
OH1
VOH = 2.0 V -50 -22 mA
Output Low Current I
OL1
VOL = 0.8 V 16 42 mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.87 2.5 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.57 2.5 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 49.8 55 %
Skew
1
VT = 1.5 V, PCICLK
(5:All)
600 625
V
T
= 1.5 V, PCICLK
(5: 1, 3, 7)
102 200
V
T
= 1.5 V, PCICLK
(7: 2, 4, 6, 8, 9, 10)
179 500
Jitter, Cycle-to-cycle
1
T
jcyc-cyc1
VT = 1.5 V
202 500 ps
1
Guaranteed by design, not 100% tested in production.
t
sk1
ps
Page 9
9
ICS9248-97
Electrical Characteristics - 48 MHz
TA = 0 - 70ºC; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MA X UNITS
Output Impedance R
DSP5
1
VO = VDD*(0.5) 20 47 60
Ω
Output Impedance R
DSN5
1
VO = VDD*(0.5) 20 44 60
Ω
Output High Voltage V
OH5
IOH = -16 mA 2.4 2.62 V
Output Low Voltage V
OL5
IOL = 9 mA 0.3 0.4 V
Output High Current I
OH5
VOH = 2.0 V -27 -22 mA
Output Low Current I
OL5
VOL = 0.8 V 16 22 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 2.33 4 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 2.42 4 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 51 55 %
Jitter, Cycle-to-cycle
1
T
jcyc-cyc5VT
= 1.5 V
439 500 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70ºC; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP5
1
VO = VDD*(0.5) 20 47.6 60
Ω
Output Impedance R
DSN5
1
VO = VDD*(0.5) 20 44 60
Ω
Output High Voltage V
OH5
IOH = -16 mA 2.4 2.6 V
Output Low Voltage V
OL5
IOL = 9 mA 0.3 0.4 V
Output High Current I
OH5
VOH = 2.0 V -26 -22 mA
Output Low Current I
OL5
VOL = 0.8 V 16 22 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 2.28 4 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 2.24 4 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 51.9 55 %
Jitter, Cycle-to-cycle
1
T
jcyc-cyc5
VT = 1.5 V
839 1000 ps
1
Guaranteed by design, not 100% tested in production.
Page 10
10
ICS9248-97
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP4B
1
VO = V
DD
*(0.5) 13.5 26 45 Ω
Output Impedance R
DSN4B
1
VO = V
DD
*(0.5) 13.5 31 45 Ω
Output High Voltage V
OH4B
IOH = -12.0 mA 2 2.24 V
Output Low Voltage V
OL4B
IOL = 12.0 mA 0.31 0.4 V
Output High Current I
OH4B
VOH = 1.7 V -31 -19 mA
Output Low Current I
OL4B
VOL = 0.7 V 19 26 mA
Rise Time
1
T
r4B
VOL = 0.4 V, VOH = 2.0 V 1.62 2 ns
Fall Time
1
T
f4B
VOH = 2.0 V, VOL = 0.4 V 1.57 2 ns
Duty Cycle
1
D
t4B
VT = 1.25 V 45 48.6 55 %
Skew
1
t
sk4B
VT = 1.25 V 52 250 ps
Jitter, Cycle-to-cycle
1
T
jcyc-cyc4BVT
= 1.25 V
245 500 ps
1
Guaranteed by design, not 100% tested in production.
Page 11
11
ICS9248-97
Power Management Features:
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
#DPKLCUPC2/UPCCIPAOI66V3ICPF_ICP
.FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONONO
Power Management Requirements:
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
langiSetatSlangiS
ycnetaL
fosegdegnisirfo.oN
KLCICP
#DP
)noitarepolamron(1Sm3
)nwodrewop(0.xam2
Page 12
12
ICS9248-97
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
Page 13
13
ICS9248-97
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Page 14
14
ICS9248-97
Ordering Information
ICS9248yF-97-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
V A RIA TIONS
MIN MAX MIN MAX
28 9.398
9.652
.370 .380
34 11.303
11.557
.445 .455
48 15.748
16.002
.620 .630
56 18.288
18.542
.720 .730
64 20.828
21.082
.820 .830
J E D E C M O- 118
DOC # 10-0034
6/1/00
REV B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Mill ime t e r s
COMMON DIMENSIONS
In Inc he s
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inc h)
SEE VARIATIONS
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