Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-78
Block Diagram
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Timing Generator for Pentium II Systems
9248-78 Rev A 7/21/99
Pin Configuration
Generates the following system clocks:
- 2 - CPUs @ 2.5V, up to 150MHz.
- 1 - IOAPIC @ 2.5V, PCI/2MHz.
- 9 SDRAMs (3.3V), up to150MHz.
-2 - 3V66 @ 3.3V, 2x PCIMHz.
- 8 - PCIs @ 3.3V.
- 1 - 48MHz, @ 3.3V fixed.
- 2 - REF @ 3.3V, 14.318Hz.
- 1 - 24MHz, @ 3.3V fixed.
Supports spread spectrum modulation ,
down spread 0 to -0.5%, ±0.25% center spread.
I2C support for power management.
Efficient power management scheme through PD#.
Uses external 14.138 MHz crystal.
48-Pin 300 mil SSOP
The ICS9248-78 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-78
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Power Groups
GNDREF, VDDREF = REF, Crystal
GND3V66, VDD3V66 = 3V66
GNDPCI, VDDPCI = PCICLKs
GNDCOR, VDDCOR = PLLCORE
GND48, VDD48 = 48
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU = CPUCLK
GNDLPCI, VDDLAPIC = IOAPIC
1. These pins will have 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Preliminary Product Preview
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Page 2
2
ICS9248-78
Preliminary Product Preview
Pin Descriptions
NIP
REBMUN
EMANNIPEPYTNOITPIRCSED
11FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
,81,01,9,2
73,92,52
DDVRWPylppusrewopV3.3
31XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
42XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,82,12,41,6,5
14,33
DNGRWPylppusV3.3rofsnipdnuorG
8,7)0:1(66V3TUOzHMICPX2tagninnurBUHrofstuptuokcolcV3.3
11
0KLCICP
1
TUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3
0SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL
21
1KLCICP
1
TUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3
1SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL
,61,51,31
02,91,71
)7:2(KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3
22#DPNI
otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola
ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht
.sm3nahtretaerg
32KLCSNIIfotupnikcolC
2
tupniC
42ATADSNIIroftupniataD
2
.tupnilairesC
62
zHM84TUOBSUroftuptuokcolczHM84dexiFV3.3
3SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL
72
2SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL
zHM42TUOtuptuozHM42dexifV3.3
03F_MARDSTUOIybdetceffatonMARDSgninnureerfV3.3
2
C
,63,83,93,04
13,23,43,53
)0:7(MARDSTUOstuptuoV3.3
24LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG
44,34)0:1(KLCUPCTUO.tuptuokcolcsubtsoHV5.2
74,54LDDVRWPCIPAOI,UPCrofylppyusrewopV5.2
64CIPAOITUOzHM2/ICPtagninnurstuptuokcolcV5.2
84
66V3_LESNI.ycneuqerftuptuo66V3ehtstcelesnipsihT
0FER
1
TUO.tuptuokcolcecnereferzHM813.41,V3.3
Note:
1. These pins will have 2X drive strength.
Page 3
3
ICS9248-78
Preliminary Product Preview
Frequency Selection
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
Note:
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
3SF2SF1SF0SF
UPC
zHM
MARDS
zHM
ICP
zHM
zHM66V3
zHMCIPAOI
0=66V3_LES1=66V3_LES
0000 32.00132.00114.3328.6628.6607.61
0001 09.00109.00136.3362.7662.7618.61
0010 00.50100.50100.5300.0700.0705.71
0011 98.6633.00144.3398.6698.6627.61
0100 00.02100.02100.04*00.4600.0800.02
0101 00.42100.42133.14*00.4666.2876.02
0110 03.33103.33134.44*00.4668.8812.22
0111 03.33103.33123.3356.6656.6666.61
1000 00.04100.04100.5300.0700.0705.71
100 1 00.05100.05105.73*00.4600.5757.81
1010 99.41199.41133.83*00.4666.6761.91
1011 00.0700.50100.5300.0700.0705.71
1100 00.5705.21105.73*00.4600.5757.81
1101 13.3869.42156.14*00.4613.3838.02
1110 00.0900.0900.0300.0600.0600.51
1111 00.5900.5976.1333.3633.3638.51
Page 4
4
ICS9248-78
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Page 5
5
ICS9248-78
Preliminary Product Preview
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
Page 6
6
ICS9248-78
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
tiB
noitpircseD
DWP
7tiB
murtcepSdarepSretneC%52.0±-0
0
%5.0-ot0murtcepSdaerpSnwoD-1
tiB
)4:6,2(
tiB
)4:6,2(
KLCUPC
zHM
MARDS
zHM
KLCICP
zHM
zHM66V3
zHMCIPAOI
1etoN
0=66V3_LES1=66V3_LES
000032.00132.00114.3328.6628.6607.61
100009.00109.00136.3362.7662.7618.61
010000.50100.50100.5300.0700.0705.71
110098.6633.00144.3398.6698.6627.61
001000.02100.02100.04*00.4600.0800.02
101000.42100.42133.14*00.4666.2876.02
011003.33103.33134.44*00.4668.8812.22
111003.33103.33123.3356.6656.6666.61
000100.04100.04100.5300.0700.0705.71
100100.05100.05105.73*00.4600.5757.81
010199.41199.41133.83*00.4666.6761.91
110100.0700.50100.5300.0700.0705.71
001100.5705.21105.73*00.4600.5757.81
101113.3869.42156.14*00.4613.3838.02
011100.0900.0900.0300.0600.0600.51
111100.5900.5976.1333.3633.3638.51
3tiB
stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0
4:6,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
elbanemurtcepsdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000.
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
Page 7
7
ICS9248-78
Preliminary Product Preview
Byte 1: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
tiB#niPDWPnoitpircseD
7tiB-X #3SF
6tiB-X #0SF
5tiB-X #2SF
4tiB721 )tcanI/tcA(zHM42
3tiB-1 )devreseR(
2tiB621 )tcanI/tcA(zHM84
1tiB-1 )devreseR(
0tiB031 )tcanI/tcA(F_MARDS
tiB#niPDWPnoitpircseD
7tiB021 )tcanI/tcA(7KLCICP
6tiB911 )tcanI/tcA(6KLCICP
5tiB711 )tcanI/tcA(5KLCICP
4tiB611 )tcanI/tcA(4KLCICP
3tiB511 )tcanI/tcA(3KLCICP
2tiB31
1
)tcanI/tcA(2KLCICP
1tiB211 )tcanI/tcA(1KLCICP
0tiB111 )tcanI/tcA(0KLCICP
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB131 )tcanI/tcA(7MARDS
6tiB231 )tcanI/tcA(6MARDS
5tiB431 )tcanI/tcA(5MARDS
4tiB531 )tcanI/tcA(4MARDS
3tiB631 )tcanI/tcA(3MARDS
2tiB83
1
)tcanI/tcA(2MARDS
1tiB931 )tcanI/tcA(1MARDS
0tiB041 )tcanI/tcA(0MARDS
tiB#niPDWPnoitpircseD
7tiB-0 )devreseR(
6tiB71 )tcanI/tcA(0_66V3
5tiB81 )tcanI/tcA(1_66V3
4tiB-X 66V3_LES
3tiB641 )0tcanI/tcA(CIPAOI
2tiB-X #1SF
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(0KLCUPC
Byte 4: Control Register
(1 = enable, 0 = disable)
Page 8
8
ICS9248-78
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Su pply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unles s otherwise sta ted)
PARA METER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Volta ge V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
-5 5
µ
A
Input L ow Cur rent I
IL1
VIN = 0 V; Inputs with no pull-up r e s is tors -5 2.0
µ
A
Input L ow Cur rent I
IL2
VIN = 0 V; Inputs with pull-up r e s is tors -200 -100
µ
A
Operating I
DD3.3OP
CL = 0 pF; Sele c t @ 66M 60 100 mA
Supply Current
Power Down I
DD3.3PD
CL = 0 pF; With input address to Vdd or GND 400 600
µ
A
Supply Current
Input frequency F
i
VDD = 3.3 V; 14.318 MHz
Pin Inductance L
pin
7nH
Input C a pa c ita n ce
1
C
IN
Logic Inputs 5 pF
C
out
O ut put pin c a pac ita nc e 6 pF
C
INX
X 1 & X2 pins 27 45 pF
Transition Time
1
T
trans
To 1s t c r ossing of ta r ge t Freq. 3 m s
Settling Time
1
T
s
From 1s t c rossing to 1% target Freq. ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq. 3 m s
Delay t
PZH,tPZH
output ena ble d e la y (all outputs) 1 10 ns
t
PLZ,tPZH
output disable delay ( a ll ou tputs) 1 10 ns
1
G uarenteed by des ign, not 100% teste d in production.
Page 9
9
ICS9248-78
Preliminary Product Preview
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V + /-5%; CL = 1 0-30 pF ( unle s s otherwise sta ted)
PARA METER SYMBOL CO ND ITION S MIN TYP MAX UN ITS
O utput Impeda nc e R
DSP1
1
VO = VDD*(0.5) 12 55
Ω
O utput Impeda nc e R
DSN1
1
VO = VDD*(0.5) 12 55
Ω
O utput High V olta ge V
OH1
IOH = -1 mA 2.4 V
O utput L ow Voltag e V
OL1
IOL = 1 mA 0.55 V
O utput High Curr e nt I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V-33 -33 mA
O utput L o w Current I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA
Rise Time t
r1
1
VOL = 0. 4 V, VOH = 2 . 4 V 0.4 1.6 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0 . 4 V 0.4 1.6 ns
Duty Cycle d
t1
1
VT = 1.5 V 45 55 %
Skew t
sk1
1
VT = 1.5 V 175 ps
Jitte r t
jcyc-cyc
VT = 1.5 V 500 ps
1
G ua r e nte e d by d esign, not 100% te s te d in production.
Electrical Characteristics - CPU
TA = 0 - 70C, V
DDL
= 2.5 V + /-5%; CL = 1 0 - 20 pF ( unle ss otherwise s ta te d)
PARA METER SYMBOL CO ND ITIO NS MIN TYP MAX UN ITS
O utput Impeda nc e R
DSP2B
1
VO = VDD*(0.5) 13.5 45
Ω
O utput Impeda nc e R
DSN2B
1
VO = VDD*(0.5) 13.5 45
Ω
O utput High V olta ge V
OH2B
IOH = -1 mA 2 V
O utput L ow Voltag e V
OL2B
IOL = 1 mA 0.4 V
O utput High Curr e nt I
OH2B
V
OH @MIN
= 1.0V , V
OH@ MAX
= 2 . 375 V -27 -27 mA
O utput Low Current I
OL2B
V
OL @MIN
= 1.2V , V
OL@ MAX
= 0. 3 V 27 30 mA
Rise Time t
r2B
1
VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 ns
F all Time t
f2B
1
VOH = 0.4 V, VOL = 2 . 0 V 0.4 1.6 ns
Duty Cycle d
t2B
1
VT = 1.25 V 455055ns
Skew t
sk2B
1
VT = 1.25 V 175 ps
t
jcyc-cyc
1
VT = 1.25 V 250 ps
Jitte r
1
G ua r e nte e d by d esign, not 100% te s te d in production.
Page 10
10
ICS9248-78
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;V
DDL
= 2. 5 V +/- 5% ; CL = 10 - 20 pF ( unle s s otherwise sta ted)
PARA METER SYMBOL CON DITIO N S MIN TYP MAX UNITS
O utput Impeda nc e R
DSP4B
1
VO = VDD*(0.5) 9 30
Ω
O utput Impeda nc e R
DSN4B
1
VO = VDD*(0.5) 9 30
Ω
Output High Voltage V
OH4\ B
IOH = -5.5 mA 2 V
Output Low Voltage V
OL4B
IOL = 9. 0 mA 0.4 V
O utput High Curr e nt I
OH4B
V
OH@ min
= 1.4 V, V
OH@ MAX
= 2 . 5 V -36 - 21 m A
O utput L o w Current I
OL4B
V
OL@ MIN
= 1.0 V, V
OL@ MAX=
0.2 36 31 mA
Rise Time t
r4B
1
VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 ns
F all Time t
f4B
1
VOH = 2.0 V, VOL = 0 . 4 V 0.4 1.6 ns
Duty Cycle d
t4B
1
VT = 1. 25 V 45 55 %
Jitte r t
jcyc-cyc
VT = 1. 25 V 500 ps
1
G ua r e nte e d by d esign, not 100% te s te d in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 20 - 30 pF (unles s otherwis e s tate d)
PARA METER SYMBOL CON DITI ON S MIN TYP MAX UN ITS
O utput Impeda nc e R
DSP3
1
VO = VDD*(0.5) 10 24
Ω
O utput Impeda nc e R
DSN3
1
VO = VDD*(0.5) 10 24
Ω
Output High Voltage V
OH3
IOH = -1 mA 2.4 V
Output Low Voltage V
OL3
IOL = 1 mA 0.4 V
O utput High Curr e nt I
OH3
V
OH @MIN
= 2.0 V, V
OH@ MAX
=3.135 V -54 -46 mA
O utput L ow Curr e nt I
OL3
V
OL@ MIN
= 1.0 V, V
OL@ MAX
=0.4 V 54 53 mA
Rise Time T
r3
1
VOL = 0. 4 V, VOH = 2 . 4 V 0.4 1.6 ns
Fa ll T ime T
f3
1
VOH = 2.4 V, VOL = 0 . 4 V 0.4 1.6 ns
Duty Cycle D
t3
1
VT = 1.5 V 45 55 %
Skew T
sk3
1
VT = 1.5 V 250 ps
Jitter t
j
cyc-cyc VT = 1.5 V 250 ps
1
G ua renteed by design, not 100% te sted in production .
Page 11
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ICS9248-78
Preliminary Product Preview
Elect r i cal C har acteristics - PC I
TA = 0 - 70C; VDD = 3.3 V + /-5%; CL = 1 0-30 pF ( unle s s otherwise sta ted)
PARA METER SYMBOL CO ND ITION S MIN TYP MAX UN ITS
O utput Impeda nc e R
DSP1
1
VO = VDD*(0.5) 12 55
Ω
O utput Impeda nc e R
DSN1
1
VO = VDD*(0.5) 12 55
Ω
O utput High V olta ge V
OH1
IOH = -1 mA 2.4 V
O utput L ow Voltag e V
OL1
IOL = 1 mA 0.55 V
O utput High Curr e nt I
OH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V-33 -33 mA
O utput L o w Current I
OL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA
Rise Time t
r1
1
VOL = 0. 4 V, VOH = 2.4 V 0.5 2 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns
Duty Cycle d
t1
1
VT = 1.5 V 45 55 %
Skew t
sk1
1
VT = 1.5 V 500 ps
Jitte r t
jcyc-cyc
VT = 1.5 V 500 ps
1
G ua r e nte e d by d esign, not 100% te s te d in production.
El ect r i cal Cha r acter i st i cs - 48 M, R E F
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 10 -20 pF ( unle s s othe r wise s ta te d)
PARA METER SYMBOL CON DITI ON S MIN TYP MAX UN ITS
O utput Impeda nc e R
DSP5
1
VO = VDD*(0.5) 20 60
Ω
O utput Impeda nc e R
DSN5
1
VO = VDD*(0.5) 20 60
Ω
Output High Voltage V
OH5
IOH = 1 mA 2.4 V
Output Low Voltage V
OL5
IOL = -1 mA 0.4 V
O utput High Curr e nt I
OH5
V
OH @MIN
=1 V, V
OH@MAX
= 3.135 V -29 -23 mA
O utput L o w Current I
OL5
V
OL@MIN
=1.95 V, V
OL@MIN
=0.4 V 29 27 mA
Rise Time t
r5
1
VOL = 0. 4 V, VOH = 2.4 V 1.8 4 ns
F all Time t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.7 4 ns
Duty Cycle d
t5
1
VT = 1. 5 V 45 55 %
Jitte r t
jcyc- c yc
1
VT = 1.5 V; F ix ed C loc ks 500 ps
t
jcyc-cyc
1
VT = 1.5 V; Re f Clocks 1000 ps
Skew T
sk
VT = 1. 5 V 250 ps
1
G ua r e nte e d by de s ign, not 100% tes te d in production.
Page 12
12
ICS9248-78
Preliminary Product Preview
Group Offset Waveforms
Group Skews at Common Transition Edges:
CP U & IOA PIC loa d (lumped) = 20pf; PCI, SDRAM, 3V66 LOA D (L UMPE D) = 30pf.
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU (at 66MHz) to
3V66
S
CPU1-3 V6 6
CP U @ 1.2 5V, 3V66 @ 1. 5V (Note: 180°
offset bet ween CP U & 3V6 6
0 500 ps
CPU (at 100MHz) to
SDRAM
S
CPU2-SDRAM
CP U @ 1.2 5V, SDRAM @ 1.5V (Note: 180°
offset between C PU & 66MHz
0 500 ps
3V 66 t o PCI S
3V66-PCI
3V 66 @ 1.5V, PCI @ 1.5V 1.5 2.1 4 ns
IOAPIC to PCI S
IOAPIC-PCI
IOAPIC @ 1.25V, PCI @1.5V 0 500 ps
Page 13
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ICS9248-78
Preliminary Product Preview
SSOP Package
LOBMYSSNOISNEMIDNOMMOCSNOITAIRAVDN
.NIM.MON.XAM.NIM.MON.XAM
A590.101.011.CA026.526.036.84
1A800.210.610.
2A880.090.290.
B800.010.5310.
C500.- 010.
DsnoitairaVeeS
E292.692.992.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
∝
°0°5°8
X580.390.001.
Ordering Information
ICS9248yF-78
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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