Datasheet AV9248F-61, ICS9248F-61 Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-61

Block Diagram

Frequency Timing Generator for Pentium II Systems

9248-61 Rev B 1/8/99

Pin Configuration

28 pin SSOP

Pentium is a trademark on Intel Corporation.

 Generates the following system clocks:

- 2CPU(2.5V) up to 100MHz.

- 7 PCI(3.3V) @ 33.3MHz (Includes one free running).

- 2 REF clks Fixed (3.3V) 48MHz at 14.318MHz.

 Skew characteristics:

- CPU  CPU<175ps

- PCI  PCI < 250ps

- PCI_E (early)  PCI = 2.1ns

- CPU(early)  PCI = 1.5ns  4ns

 Supports Spread Spectrum modulation for CPU and PCI

clocks, 0.5% down spread

 Efficient Power management scheme through stop clocks

and power down modes.

 Uses external 14.318MHz crystal, no external load cap

required for CL=18pF crystal.

 28 pin 209mil SSOP.

The ICS9248-61 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.

Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-61 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.

Power Groups

GNDR/C = REFCLK, CORE, Crystal
VDDCOR = Core
GNDLCPU, VDDCPU = CPU
GND48, VDD48 = 48MHz
VDDPCI, GNDPCI - PCICLK, PCICLK_F, PCICLK_E

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-61

Pin Descriptions

Pin number Pin nam e Type Descripti on

2 X1 Input 14.318 MHz c rystal input
3 X2 Output 14.318 MHz crystal output
4 PCICLK _F Output 3.3 V free running PCI clock output, will not be stopped by the P CI_STOP#
7 GNDPCI Power Ground for PCI c lock output s

8 VDDPCI Power 3. 3 V power for the PCI clock output s
12 PCICLK_E Out put Earl y PCICLK output, offset from ot her P CICLKs, stopped by PCI - STOP#
13 VDD48 Power 3. 3 V power for 48 MHz c locks

14

SEL 100_66#/

48MHz

Input

on power-on cont rol for t he frequency of clocks at the CPU & PCICLK output pins. If
logi c "0" is used the 66.6 MHz frequency i s select ed. If Logic "1" i s used, the 100
MHz f r equency is select ed. The PCI cloc k is mult iplexed to run at 33.3 MHz f or both
selects

15 GND48 Power Ground for 48 MHz cl ocks
16 DIV4# Input

Ac tive low input , enables the CPUCLK and the P CICLK to run at 1/4 of the regular
frequecies

17 PD# Input

As ynchronous act ive l ow i nput pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.

18 CPU_ST OP# Input

As ynchronous act ive l ow i nput pin used to stop the CPUCLK i n active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clock s.

19 VDDCOR Input 3.3 V power for the core
20 PCI-S TOP# Input

Sy nchronous acti ve low input used t o stop the PCICLK i n active low state. It wil l not

effect PCICLK_F or any other out puts.
21 GNDR/C Input Ground for REFCLK, Crystal & Core
22 GNDLCPU Power Ground for the CPU and Host clock outputs
25 VDDLCPU Power 2. 5 V power for the CP U and Host clock outputs

26 SPREAD# Output

power-on spread spectrum enable option. Acti ve low = spread spectrum c lock ing

enable. Act ive hi gh = spread s pectrum cloc king disable.
28 VDDR Input 3.3 V power for the REFCLK and crystal clock outputs

1,27 REF(0:1) Output 3.3V , 14. 318 MHz refer ence clock output.

23,24 CPUCLK (0:1) 0utput 2.5 V CPU and Host clock outputs

5,6,9,10, 11 PCICLK (1:4) Output 3.3 V PCI clock outputs, generating t iming requir em ents

3

ICS9248-61

Frequency Table

Power Management

ICS9248-61 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.

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4

ICS9248-61

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9248-61. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-61 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-61. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9248-61.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

5

ICS9248-61

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-61 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

6

ICS9248-61

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.

Ele ctrical Characteristics - I nput/Supply/Common Out put Parameters

TA = 0 - 70C; Supply V oltage VDD = V

DDL

= 3.3 V +/-5% (unless otherwi se stated)

PARAMETER

SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage

V

IH

2V

DD

+0.3 V

Input Low Voltage

V

IL

VSS-0.3 0.8 V

I nput H igh Current

I

IH

VIN = V

DD

0.1 5

µ

A

I nput Low Current

I

IL1

VIN = 0 V; Input s with no pull-up resistors -5 2.0

µ

A

I nput Low Current

I

IL2

VIN = 0 V; Input s with pull-up resistors - 200 -100

µ

A

Operating

I

DD3.3OP66CL

= 0 pF; Select @ 66MHz 60 180 mA

Supply Current

I

DD3.3OP100CL

= 0 pF; Select @ 100MHz 66 180 mA

Power Dow n Supply

Current

I

DD3.3PD

CL = 0 pF;
With input address to Vdd or GND 70 600

µ

A

I nput frequency

F

i

VDD = 3.3 V; 11 14.318 16 MH z

C

IN

Logic Inputs 5 pF

C

INX

X1 & X2 pins 27 36 45 pF

Transition Time

1

T

trans

To 1st crossing of target Fr eq. 3 ms

Clk Stabilization

1

T

STAB

From VDD = 3.3 V t o 1% target Fr eq. 3 ms

Skew

1

T

CPU-PCI1VT

= 1.5 V;

1.5 2.4 4 ns

1

Guarantee d by des ign, not 100% tested in producti on.

Input Capacitance

1

Elect rical C haracterist ics - Inp ut/ Su pply/ Comm on O ut put Param et ers

TA = 0 - 70 C; Suppl y Voltage VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating I

DD2.5OP66

CL = 0 pF; Select @ 66.8 MHz 16 72 mA

Supply Current I

DD2.5OP100CL

= 0 pF; Select @ 100 MHz 23 100 mA

Skew

1

t

CPU-PCI2

VT = 1.5 V; VTL = 1.25 V

1.5 3 4 ns

1

Guara ntee d by d esign, no t 100% tested in production.

7

ICS9248-61

Ele ctrical Characteristics - CP UCLK

TA = 0 - 70C; VDD = 3.3 V +/- 5 % , V

DDL

= 2.5 V +/-5%; CL = 10 - 20 pF ( u nl e ss ot herwise s t ated)

PARAMETER SYMBOL CONDITI O NS MIN TYP MAX UN ITS

Output High Voltage V

OH2B

IOH = -12.0 mA 2 2.3 V

Output Low Voltage V

OL2B

IOL = 12 mA 0.2 0.4 V

O utput High Current I

OH2B

VOH = 1 .7 V -41 -19 mA

Ou tput Low Cu rrent I

OL2B

VOL = 0.7 V 19 37 mA

Rise Time t

r2B

1

VOL = 0.4 V, VOH = 2.0 V 1.25 1.6 ns

Fall Time t

f2B

1

VOH = 2.0 V, VOL = 0 .4 V 1 1.6 ns

Duty Cycle d

t2B

1

VT = 1.25 V 454855%

Skew t

sk2B

1

VT = 1.25 V 30 175 ps

Jitter, Cycle -to-cycle t

jcyc-cyc2B

1

VT = 1.25 V 150 2 50 ps

Jitter, One Sigma t

j1s2B

1

VT = 1.25 V 40 150 ps

Jitter, Absolute

t

jabs2B

1

VT = 1.25 V

-2 50 140 +250 ps

1

G ua ranteed by de sign, not 100% t e sted in produ c t i on.

Electrical Characteristics - PCICLK

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput High Voltage V

OH1

IOH = -11 mA 2.4 3.1 V

Output Low Voltage V

OL1

IOL = 9.4 mA 0.1 0.4 V

Ou tput High Current I

OH1

VOH = 2.0 V -62 -22 mA

Output Low Current I

OL1

VOL = 0.8 V 16 57 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns

Fall Time

1

t

f1

VOH = 2.4 V , VOL = 0.4 V 1.1 2 ns

Duty Cycle

1

d

t1

VT = 1.5 V 45 50 55 %

Skew

1

t

sk1

VT = 1.5 V 140 500 ps

Jitter, Cycle -to-cycle t

j

cyc-cyc1

VT = 1.25 V 250 5 00 ps

Jitter, O ne Sigma

1

t

j1s1

VT = 1.5 V 17 150 ps

Jitter, Absolute

1

t

jabs1

VT = 1.5 V

-250 70 250 ps

1

Guara nt eed by design, not 100% tested in produc t ion.

8

ICS9248-61

Ele ctrical Characteristics - REF/48MH z

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput High Voltage V

OH5

IOH = -12 mA 2 .6 3.1 V

Output Low Voltage V

OL5

IOL = 9 mA 0.17 0.4 V

Ou tput High Current I

OH5

VOH = 2.0 V -44 -22 mA

Output Low Current I

OL5

VOL = 0.8 V 16 42 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 1.4 4 ns

Fall Time

1

t

f5

VOH = 2.4 V , VOL = 0.4 V 1.1 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 53 55 %

Jitter, O ne Sigma

1

t

j1s5

VT = 1.5 V 1 3 %

Jitter, Absolute

1

t

jabs5

VT = 1.5 V

35%

1

Guara nt eed by design, not 100% tested in produc t ion.

9

ICS9248-61

LOBMYS

NOMMOC

SNOISNEMID

SNOITAIRAV

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.NIM.MON.XAMN .NIM.MON.XAM

A860.0370.0870.041932.0442.0942.0

1A200.0500.0800.061932.0442.0942.0

2A660.0860.0070.002872.0482.0982.0
b010.0210.0510.042813.0323.0823.0
c400.0600.0800.082793.0204.0704.0

DsnoitairaVeeS03793.0204.0704.0

E502.0902.0212.0

eCSB6520.0

H103.0703.0113.0

L520.0030.0730.0

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∝

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Dimensions in inches

Ordering Information

ICS9248F-61

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX Y F - PPP

SSOP Package

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.