Page 1
Integrated
Circuit
Systems, Inc.
ICS9248-168
Third party brands and names are the property of their respective owners.
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 7 - SDRAM @ 3.3V
• 8 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 153MHz frequency support
• Support power management: CPU stop and Power down
Mode from I
2
C programming.
• Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
• Uses external 14.318MHz crystal
AMD - K7™ Clock Generator for Mobile System
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1.5X strength through I2C
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
REF0
REF
REF2
GND
GND
VDD
CPUCLK
CPUCLKT0
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
S DATA
1
2
2
2
1
ICS9248-168
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2SF1SF0SFUPCICPegatnecrePdaerpS
000 00.00133.33daerpSretneC%53.0-/+
001 33.33133.33daerpSretneC%53.0-/+
010 00.00133.33daerpSnwoD%5.0-ot0
011 33.33133.33daerpSnwoD%5.0-ot0
100 00.00133.33daerpSretneC%6.0-/+
10 1 33.33133.33daerpSretneC%6.0-/+
110 00.0900.03daerpSretneC%52.0-/+
111 00.02100.03daerpSretneC%52.0-/+
SEL24_48#
S DATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (5:0)
PCICLK (6:0)
PCICLK_F
SDRAM_F
CPUCLKT0
CPUCLK
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
Stop
Control
Logic
Config.
Reg.
/ 2
REF (2:0)
SDRAM
DRIVER
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
9248-168 Rev B 01/09/01
Page 2
2
ICS9248-168
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low .
REBMUNNIP
EMANNIPEPYTNOITPIRCSED
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34,53,03
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1XNI
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2Xmorfrotsiser
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2XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
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2SF
2,1
NIDDVotpu-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
F_KLCICPTUO
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
5
1SF
2,1
NIDDVotpu-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUOtuptuokcolcICP
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DNGRWPdnuorG
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Page 3
3
ICS9248-168
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF , Xtal
Page 4
4
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
tiBnoitpircseDDWP
,2tiB
4:7tiB
tiB
2
tiB
7
tiB
6
tiB
5
tiB
4
KLCUPC
)zHM(
KLCICP
)zHM(
daerpS
egatnecerP
devreseR
10100
00000 00.00133.33daerpSretneC%53.0-/+
00001 33.33133.33daerpSretneC%53.0-/+
00010 00.00133.33daerpSnwoD%5.0-ot0
00011 33.33133.33daerpSnwoD%5.0-ot0
00100 00.00133.33daerpSretneC%6.0-/+
00101 33.33133.33daerpSretneC%6.0-/+
00110 00.0900.03daerpSretneC%52.0-/+
00111 00.02100.03daerpSretneC%52.0-/+
01000 03.00134.33daerpSretneC%53.0-/+
01001 37.33134.33daerpSretneC%53.0-/+
01010 03.00134.33daerpSretneC%06.0-/+
01011 37.33134.33daerpSretneC%06.0-/+
01100 00.10176.33daerpSretneC%53.0-/+
01101 66.43176.33daerpSretneC%53.0-/+
01110 00.20100.43daerpSretneC%53.0-/+
01111 00.63100.43daerpSretneC%53.0-/+
10000 00.30133.43daerpSretneC%53.0-/+
1000 1 33.73133.43daerpSretneC%53.0-/+
100 10 00.40176.43daerpSretneC%53.0-/+
100 11 66.83176.43daerpSretneC%53.0-/+
10 10 0 00.50100.53daerpSretneC%53.0-/+
10 10 1 00.04100.53daerpSretneC%53.0-/+
10 1 10 00.70176.53daerpSretneC%53.0-/+
10 111 66.24176.53daerpSretneC%53.0-/+
11000 00.01176.63daerpSretneC%53.0-/+
1100 1 66.64176.63daerpSretneC%53.0-/+
110 10 00.51133.83daerpSretneC%53.0-/+
110 11 33.35133.83daerpSretneC%53.0-/+
11100 00.00133.33daerpSretneC%05.0-/+
1110 1 33.33133.33daerpSretneC%05.0-/+
11110 00.00133.33daerpSnwoD%0.1-ot0
11111 33.33133.33daerpSnwoD%0.1-ot0
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
daerpSretneC%52.0±delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Page 5
5
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB2210SF
6tiB511SF
5tiB412SF
4tiB241 X1=1X5.1=0KLCUPC
3tiB-1 devreseR
2tiB04,141 X1=1X5.1=0C/TKLCUPC
1tiB-1 devreseR
0tiB241 KLCUPC
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB41 F_KLCICP
6tiB511 6KLCICP
5tiB211 5KLCICP
4tiB111 4KLCICP
3tiB011 3KLCICP
2tiB91 2KLCICP
1tiB81 1KLCICP
0tiB51 0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB721 F_MARDS
5tiB821 5MARDS
4tiB921 4MARDS
3tiB231 3MARDS
2tiB331 2MARDS
1tiB631 1MARDS
0tiB731 0MARDS
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-1 devreseR
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB321 #84_42LES
5tiB221 zHM84
4tiB321 zHM84_42
3tiB8410FER
2tiB7411FER
1tiB6412FER
0tiB-1 devreseR
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-0 devreseR
Page 6
6
ICS9248-168
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
El ectrical Characteri stics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volta ge VDD = 3.3 V +/-5% (unless other wise state d)
PARAM ETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
5
uA
Inp ut Low C urrent I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5
uA
Inp ut Low C urrent I
IL2
VIN = 0 V; Inputs with pull-up resistors -200
uA
Operating Supply Current I
DD3.3OP
CL =20 pF; SDRAM not running 75 180
mA
Power Down PD 280 60 0 uA
Input frequency F
i
VDD = 3.3 V 12 14.318 16 MHz
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 45 pF
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to ±1% target Freq. 3 ms
Skew window
1
T
CPU-PCI window
Vt=50% CPU - 1.5V PCI; CPU Leads 250 500 ps
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Electrical Characteristics - REF
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out
p
ut Impedance
1
R
DSP5B
VO=VDD*(0.5
)
20 24 60
Ω
Out
p
ut Impedance
1
R
DSN5B
VO=VDD*(0.5
)
20 44 60
Ω
Output High Voltage V
OH5
IOH = -12 mA 2.4 V
Output Low Voltage V
OL5
IOL = 9 mA 0.4 V
Output High Current
I
OH5
VOH = 2.0 V -22
mA
Output Low Current
I
OL5
VOL = 0.8 V 16
mA
Rise Time
1
t
r5
1
VOL = 0.4 V, VOH = 2.4 V 1.7 4.0 ns
Fall Time
1
t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.5 4.0 ns
Dut
y Cy
cle
1
d
t5
1
VT = 1.5 V 45 52.8 55 %
Jitter
, Cy
cle-to-Cycle
1
t
jcy
c-cyc5
1
VT = 1.5 V
770 1000 ps
1
Guaranteed by design, not 100% tested in production.
Page 7
7
ICS9248-168
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance Z
O
1
VO=V
X
60
Ω
Output High Voltage V
OH2B
Termination to Vpull-up(external
)
11.8V
Output Low Voltage V
OL2B
Termination to Vpull-up(external
)
0.8 V
Output Low Current
I
OL2B
VOL = 0.3 V 18
mA
Rise Time
1
t
1
V
OH
= 1.2 V, VOL = 0.3V 0.5 0.9
ns
F
a
ll Tim
e
1
t
1
VOL = 0.3 V, VOH = 1.2V 0.3 0.9 ns
Differential volta
g
e-AC
1
V
DIF
N
ote 2 0.4 Vpull-up(ext) + 0.6 V
Differential volta
g
e-DC
1
V
DIF
N
ote 2 0.2 Vpull-up(ext) + 0.6 V
Diff Crossover Voltage
1
V
X
N
ote 3 1.2 0.82 1.8 V
Dut
y Cy
cle
1
d
t2B
1
VT = 50% 45 51.5 55
%
Skew window
1
t
sk2B
1
VT = 50% 200
p
s
Jitter, C
y
cle-to-cycle
1
tjcyc-cyc
2B
1
VT = V
X
125 300
p
s
Jitter, Absolute
1
tjabs
2B
1
VT = 50%
250 ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - V
DIF
specifies the minimum input differential voltages (VTR-V
CP
)
required for switching, where VTR is the "true" input Level
and V
CP
is the "complement" input level.
3 - V
p
ull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT S
Output High Voltage V
OH2B
IOH = -12.0 mA 1 1.8 V
Output Low Voltage V
OL2B
IOH = 12.0 mA 0.8 V
Output Low Current
I
OL2B
VOL = 1.7 V 18
mA
Output Low Current
I
OL2B
VOL = 0.7 V 18
mA
Rise Time
1
t
1
V
OL
= 0.4 V, VOL = 2.0V 0.9 1.6
ns
F
a
ll Tim
e
1
t
1
V
OH
= 2.0 V, VOL = 0.4V 0.8 1.6 ns
Dut
y Cy
cle
1
d
t2B
1
VT = 1.5V 45 51.5 55
%
Skew window
1
t
sk2B
1
VT = 1.5V 200
p
s
Jitter, Cycle-to-cycle
1
tjcyc-cyc
2B
1
VT = 1.5V 125 300
p
s
Jitter, Absolute
1
tjabs
2B
1
VT = 1.5V
250 ps
Notes:
1 - Guaranteed b
y
design, not 100% tested in production.
Page 8
8
ICS9248-168
Third party brands and names are the property of their respective owners.
Electrical Characteristics - PCICLK
TA = 0 - 70C; V
DD
= V
DDL
= 3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
VO=VDD*(0.5
)
12 24 55
Ω
Output Impedance R
DSN2B
1
VO=VDD*(0.5
)
12 23 55
Ω
Output High Voltage V
OH1
IOH = -11 mA 2.6 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.4 V
Output High Current
I
OH1
VOH = 2.0 V -16
mA
Output Low Current
I
OL1
VOL = 0.8 V 19
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.29 2.5 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.29 2.5 ns
Dut
y Cy
cle
1
d
t1
VT = 1.5 V 45 50.2 55 %
Skew window
1
t
sk1
VT = 1.5 V 280 400
p
s
Jitter, Cyc-to-Cyc
t
jcyc-cyc1
VT = 1.5 V
86 200 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Character i sti cs - SD R AM _OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP3
VO=VDD*(0.5
)
10 11 24
Ω
Output Impedance
1
R
DSN3
VO=VDD*(0.5
)
10 12 24
Ω
Output High Voltage V
OH3
IOH = -11 mA 2 V
Output Low Voltage V
OL3
IOL = 11 mA 0.4 V
Output High Current
I
OH3
VOH = 2.0 V -12
mA
Output Low Current
I
OL3
VOL = 0.8 V 12
mA
Rise Time
1
t
r3
1
VOL = 0.4 V, VOH = 2.4 V 0.9 1.5 ns
Fall Time
1
t
f3
1
VOH = 2.4 V, VOL = 0.4 V 0.8 1.5 ns
Dut
y Cy
cle
1
d
t3
1
VT = 1.5 V 45 51.5 55 %
Skew (ouput to output)
1
t
sk3A
VT = 1.5 V 220 250
p
s
Skew (Buffer In to output)
1
t
sk3B
VT = 1.5 V
3ns
1
Guaranteed by design, not 100% tested in production.
Page 9
9
ICS9248-168
Third party brands and names are the property of their respective owners.
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP1B
VO=VDD*(0.5
)
12 14 55
Ω
Output Impedance
1
R
DSN1B
VO=VDD*(0.5
)
12 13 55
Ω
Output High Voltage V
OH1
IOH = -11 mA 2.6 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.4 V
Output High Current
I
OH1
VOH = 2.0 V -12
mA
Output Low Current
I
OL1
VOL = 0.8 V 12
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1 .4 2.0 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1 .3 2.0 ns
Dut
y Cy
cle
1
d
t1
VT = 1.5 V 45 50.2 55 %
Skew window
1
t
sk1
VT = 1.5 V 280 400
p
s
Jitter, Cycle-to-Cycle
1
t
jcyc-cyc1
VT = 1.5 V
200 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP5B
VO=VDD*(0.5
)
20 24 60
Ω
Output Impedance
1
R
DSN5B
VO=VDD*(0.5
)
20 44 60
Ω
Output High Voltage V
OH5
IOH = -12 mA 2.4 V
Output Low Voltage V
OL5
IOL = 9 mA 0.4 V
Output High Current
I
OH5
VOH = 2.0 V -22
mA
Output Low Current
I
OL5
VOL = 0.8 V 16
mA
Rise Time
1
t
r5
1
VOL = 0.4 V, VOH = 2.4 V 1.8 4.0 ns
Fall Time
1
t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.8 4.0 ns
Dut
y Cy
cle
1
d
t5
1
VT = 1.5 V 24 48 MHz
45
53 55
%
Jitter, C
y
cle-to-Cycle
1
t
jcy
c-cyc5
1
VT = 1.5 V
150 500 ps
1
Guaranteed by design, not 100% tested in production.
Page 10
10
ICS9248-168
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
Page 11
11
ICS9248-168
Third party brands and names are the property of their respective owners.
Fig. 1
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248168 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power -On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
T o program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary . The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Page 12
12
ICS9248-168
Third party brands and names are the property of their respective owners.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-168 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
PD#
Page 13
13
ICS9248-168
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-168. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-168.
3. All other clocks continue to run undisturbed.
Page 14
14
ICS9248-168
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9248yF-168-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASI C
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.398
9.652
.370 .380
34 11.303
11.557
.445 .455
48 15.748
16.002
.620 .630
56 18.288
18.542
.720 .730
64 20.828
21.082
.820 .830
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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