Page 1
Integrated
Circuit
Systems, Inc.
ICS9248-141
Third party brands and names are the property of their respective owners.
Block Diagram
9248-141 Rev B 01/18/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KX133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - Single-ended open drain CPU clock
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management: CPU stop and Power down
Mode from I
2
C programming.
• Spread spectrum for EMI control
(± 0.25% center spread).
• Uses external 14.318MHz crystal
AMD - K7™ System Clock Chip
* Internal Pull-up Resistor of 120K to VDD
VDDREF
REF0/CPU_STOP#*
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
S DATA
SCLK
REF1/FS2*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
ICS9248-141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL24_48#
BUFFER IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_OUT
CPUCLKT (1:0)
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
S DATA
SCLK
FS (3:0)
PD#
CPU_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
SDRAM
DRIVER
3SF2SF1SF0SF
UPC
)zHM(
KLCICP
)zHM(
0000 00.0900.03
0001 00.5976.13
0010 00.10176.33
0011 00.20100.43
0100 09.00175.33
0101 00.30133.43
0110 00.50100.53
0111 00.00133.33
1000 00.70176.53
1001 00.90133.63
1010 00.01176.63
1011 00.11100.73
1100 00.31176.73
1101 00.51133.83
1110 00.71100.93
1111 03.33133.33
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
Page 2
2
ICS9248-141
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1FERDDVRWPV3.3lanimon,ylppusrewopLATX,FER
2
0FERTUO
REGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41
sdaolSUBASIrofreffub
#POTS_UPC
2,1
NI
MARDS&CKLCUPC,TKLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel"0"cigolta)0:11(
,22,61,9,3
74,54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
41,6ICPDDVRWPV3.3lanimon,KLCICPdnaF_KLCICProfylppuS
7
F_KLCICPTUO
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
EDOM
2,1
NI
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf2niP
.tupnIdehctaL
8
3SF
2,1
NIDDVotpu-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUOtuptuokcolcICP
01
#84_42LES
2,1
NItuptuo52niprofzHM84ro42tcelesottupnicigoL
1KLCICPTUO.tuptuokcolcICP
11,21,31)2:4(KLCICPTUO.stuptuokcolcICP
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
,12,02,81,71
,23,13,92,82
83,73,53,43
)0:11(MARDSTUO
nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
.)tespihcybdellortnoc(
63,03,91RDSDDVRWP.V3.3lanimon9MARDSrofylppuS
32ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
42KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
52
zHM84_42TUOtuptuokcolczHM84/zHM42
1SF
2,1
NI.tupnIdehctaL.niptcelesycneuqerF
62
zHM84TUOkcolctuptuozHM84
0SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
7284DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
04TUO_MARDSTUOreffubMARDSrofkcolcecnerefeR
14#DPNIwolevitca,pihcnwodsrewoP
24ADDVRWPV3.3erocrofylppuS
34,64)0:1(TKLCUPCTUO
niardnepoesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT"
.pu-llupV5.1lanretxenadeenstuptuo
440CKLCUPCTUO
neposihT.tuptuoUPCriaplaitnereffidfokcolc"yratnemelpmoC"
.pu-llupV5.1lanretxenasdeentuptuoniard
84
1FERTUO.kcolcecnereferzHM813.41
2SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
Page 3
3
ICS9248-141
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-141 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-141
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
7niP,EDOM
)tupnIdehctaL(
2niP
0
#POTS_UPC
)tupnI(
1
0FER
)tuptuO(
Power Groups
VDD48 = 48MHz, PLL2
VDDA = VDD for Core PLL
VDDREF = REF , Xtal
VDDPCI = PCI
VDDSDR = SDRAM
Page 4
4
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
tiBnoitpircseDDWP
,2tiB
4:7tiB
tiB
2
tiB
7
tiB
6
tiB
5
tiB
4
KLCUPC
)zHM(
KLCICP
)zHM(
daerpS
egatnecerP
devreseR
00000 00.0900.03daerpSretneC%52.0±
00001 00.5976.13daerpSretneC%52.0±
00010 00.10176.33daerpSretneC%52.0±
00011 00.20100.43daerpSretneC%52.0±
00100 09.00175.33daerpSretneC%52.0±
00101 00.30133.43daerpSretneC%52.0±
00110 00.50100.53daerpSretneC%52.0±
00111 00.00133.33daerpSretneC%52.0±
01000 00.70176.53daerpSretneC%52.0±
01001 00.90133.63daerpSretneC%52.0±
01010 00.01176.63daerpSretneC%52.0±
01011 00.11100.73daerpSretneC%52.0±
01100 00.31176.73daerpSretneC%52.0±
01101 00.51133.83daerpSretneC%52.0±
01110 00.71100.93daerpSretneC%52.0±
01111 03.33133.33daerpSretneC%52.0±
10000 00.02100.04daerpSretneC%52.0±
10001 00.52152.13daerpSretneC%52.0±
100 10 00.03105.23daerpSretneC%52.0±
100 11 37.33134.33daerpSretneC%52.0±
10100 00.53157.33daerpSretneC%52.0±
1010 1 00.73152.43daerpSretneC%52.0±
10110 00.93157.43daerpSretneC%52.0±
10111 00.00133.33daerpSretneC%52.0±
11000 00.04100.53daerpSretneC%52.0±
11001 00.34157.53daerpSretneC%52.0±
11010 00.54152.63daerpSretneC%52.0±
11011 00.84100.73daerpSretneC%52.0±
11100 00.05105.73daerpSretneC%52.0±
11101 00.55157.83daerpSretneC%52.0±
11110 66.66176.14daerpSretneC%52.0±
11111 33.33133.33daerpSretneC%52.0±
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
daerpSretneC%52.0±delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Page 5
5
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X#2SF
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-X#3SF
3tiB041 TUO_MARDS
2tiB-X #)#84_42LES(
1tiB44,341
htob(elbane0KLCUPC
dna"eurT".riaplaitnereffid
)"yratnemilpmoC
0tiB641 elbaneTKLCUPC
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X#0SF
6tiB71 F_KLCICP
5tiB-1 )devreseR(
4tiB311 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB011 1KLCICP
0tiB81 0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB821 7MARDS
6tiB921 6MARDS
5tiB131 5MARDS
4tiB231 4MARDS
3tiB431 3MARDS
2tiB531 2MARDS
1tiB731 1MARDS
0tiB831 0MARDS
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-X #EDOM
3tiB-X#1SF
2tiB-1 )devreseR(
1tiB841 1FER
0tiB210FER
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB621 zHM84
4tiB521 zHM84_42
3tiB711 11MARDS
2tiB811 01MARDS
1tiB021 9MARDS
0tiB121 8MARDS
Page 6
6
ICS9248-141
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/S upply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
5
uA
Input Low Current I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5
uA
Input Low Current I
IL2
VIN = 0 V; Inputs with pull-up resistors -200
uA
Operating Supply Current
I
DD3.3OP
CL =20 pF; SDRAM not running 75
180
mA
Power Down PD 280 600 uA
Input frequency F
i
VDD = 3.3 V 12 14.318 16 MHz
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 45 pF
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq. 3 ms
Skew window
1
T
CPU-PCI window
Vt=50% CPU - 1.5V PCI; CPU Leads 250 500 ps
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Page 7
7
ICS9248-141
Third party brands and names are the property of their respective owners.
Electrical Characteristics - REF(0:1)
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS M IN TYP MAX UNITS
Output Impedance
1
R
DSP5B
VO=VDD*(0.5) 20 24 60 Ω
Output Impedance
1
R
DSN5B
VO=VDD*(0.5) 20 44 60 Ω
Output Hi gh Voltage V
OH5
IOH = -12 mA 2.4 V
Output Low Voltage V
OL5
IOL = 9 mA 0.4 V
Output High Current
I
OH5
VOH = 2.0 V -22
mA
Output Low Current
I
OL5
VOL = 0.8 V 16
mA
Rise Time
1
t
r5
1
VOL = 0.4 V, VOH = 2.4 V 1.6 4.0 ns
Fall Time
1
t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.8 4.0 ns
Duty Cycle
1
d
t5
1
VT = 1.5 V 45 53 55 %
Jitter, Cycle-to-Cycle
1
t
jcyc-cyc5
1
VT = 1.5 V
500 1000 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Cha r a ct eristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance Z
O
1
VO=V
X
60
Ω
Output High Voltage V
OH2B
Termination to Vpull-up(external) 1 1.8 V
Output Low Voltage V
OL2B
Termination to Vpull-up(external) 0.8 V
Output Low Current
I
OL2B
VOL = 0.3 V 18
mA
V
OH
= 20%, VOL = 80% CPU0 2 3.5
CPUT1 2 3
V
OH
= 80%, VOL = 20% CPU0 1.4 1.6
CPUT1 1.1 1.2
Differential voltage-AC
1
V
DIF
Note 2 0.4 Vpull-up(ext) + 0.6 V
Differential voltage-DC
1
V
DIF
Note 2 0.2 Vpull-up(ext) + 0.6 V
Diff Crossover Vo lt a g e
1
V
X
Note 3 1.2 1.5 1.8 V
CPU0 between crossing points 47 51 57
CPUT1 @ 50% 90,100,133 MHz 47 54 57
Skew window
1
t
sk2B
1
VT = 50% 40 200 ps
Jitter, Cycle-to-cycle
1
tjcyc-cyc
2B
1
VT = V
X
150 300 ps
Jitter, Absolute
1
tjabs
2B
1
VT = 50%
140 250 ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - V
DIF
specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input Level
and V
CP
is the "complement" input level.
3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
t
r2B
1
Rise Time
1
ns
Duty Cycle
1
%
d
t2B
1
ns
t
f2B
1
Fall Time
1
Page 8
8
ICS9248-141
Third party brands and names are the property of their respective owners.
Electrical Characteristics - PCI CLK
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
Output Impedance
1
R
DSP1B
VO=VDD*(0.5) 12 14 55 Ω
Output Impedance
1
R
DSN1B
VO=VDD*(0.5) 12 13 55 Ω
Output High Voltage V
OH1
IOH = -11 mA 2.6 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.4 V
Output High Current
I
OH1
VOH = 2.0 V -12
mA
Output Low Current
I
OL1
VOL = 0.8 V 12
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.5 2.0 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.6 2.0 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 51 55 %
Skew window
1
t
sk1
VT = 1.5 V 370 400 ps
Jitter, Cycle-to-Cycle
1
t
jcyc-cyc1
VT = 1.5 V
125 200 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS
Output Impedance
1
R
DSP1B
VO=VDD*(0.5) 12 14 55 Ω
Output Impedance
1
R
DSN1B
VO=VDD*(0.5) 12 13 55 Ω
Output High Voltage V
OH1
IOH = -11 mA 2.6 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.4 V
Output High Curre nt
I
OH1
VOH = 2.0 V -12
mA
Output Low Current
I
OL1
VOL = 0.8 V 12
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.8 2.0 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.6 2.0 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 50 55 %
Jitter, Cycle-to-Cycle
1
t
jcyc-cyc1
VT = 1.5 V
125 200 ps
1
Guaranteed by design, not 100% tested in production.
Page 9
9
ICS9248-141
Third party brands and names are the property of their respective owners.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; V
DD
= 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP5B
VO=VDD*(0.5) 20 24 60 Ω
Output Impedance
1
R
DSN5B
VO=VDD*(0.5) 20 44 60
Ω
Output High Voltage V
OH5
IOH = -12 mA 2.4 V
Output Low Voltage V
OL5
IOL = 9 mA 0.4 V
Output High Current
I
OH5
VOH = 2.0 V -22
mA
Output Low Current
I
OL5
VOL = 0.8 V 16
mA
Rise Time
1
t
r5
1
VOL = 0.4 V, VOH = 2.4 V 1.3 4.0 ns
Fall Time
1
t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.3 4.0 ns
Duty Cycle
1
d
t5
1
VT = 1.5 V 24_48 MHz
45
52 55
%
Jitter, Cycle-to-Cycle
1
t
jcyc-cyc5
1
VT = 1.5 V
150 500 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP3
VO=VDD*(0.5) 10 11 24 Ω
Output Impedance
1
R
DSN3
VO=VDD*(0.5) 10 12 24 Ω
Output High Voltage V
OH3
IOH = -11 mA 2 V
Output Low Voltage V
OL3
IOL = 11 mA 0.4 V
Output High Current
I
OH3
VOH = 2.0 V -12
mA
Output Low Current
I
OL3
VOL = 0.8 V 12
mA
Rise Time
1
t
r3
1
VOL = 0.4 V, VOH = 2.4 V 0.9 1.5 ns
Fall Time
1
t
f3
1
VOH = 2.4 V, VOL = 0.4 V 0.9 1.5 ns
Duty Cycle
1
d
t3
1
VT = 1.5 V 455155%
Skew (ouput to output )
1
t
sk3A
VT = 1.5 V 220 250 ps
Skew (Buffer In to output)
1
t
sk3B
VT = 1.5 V
3ns
1
Guaranteed by design, not 100% tested in production.
Page 10
10
ICS9248-141
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
ACK
Byte 0
A
CK
Byte 1
A
CK
Byte 2
ACK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
ACK
Byte 6
A
CK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
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ICS9248-141
Third party brands and names are the property of their respective owners.
Fig. 1
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248141 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power -On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
T o program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary . The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
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ICS9248-141
Third party brands and names are the property of their respective owners.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-141 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
PD#
Page 13
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ICS9248-141
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-141. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-141.
3. All other clocks continue to run undisturbed.
Page 14
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ICS9248-141
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9248yF-141-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASI C
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.398
9.652
.370 .380
34 11.303
11.557
.445 .455
48 15.748
16.002
.620 .630
56 18.288
18.542
.720 .730
64 20.828
21.082
.820 .830
SYM BO L
SEE VARIATI O NS
SEE VARIATI O NS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
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