Datasheet AV9248F-138, ICS9248F-138 Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS9248-138

Third party brands and names are the property of their respective owners.

Block Diagram

9248- 138 Rev A 10/03/00

Recommended Application:

810/810E and Solano type chipset.

Output Features:

• 2- CPUs @ 2.5V

• 9 - SDRAM @ 3.3V, including 1 free running

• 7 - PCICLK @ 3.3V

• 1 - IOAPIC @ 2.5V,

• 3 - 3V66MHz @ 3.3V

• 2 - 48MHz, @ 3.3V fixed.

• 1 - 24/48MHz, @3.3V selectable by I

2

C

• 1 - REF @v3.3V, 14.318MHz.

Features:

• Up to 200MHz frequency support

• Support FS0-FS4 strapping status bit for I

2

C read back.

• Support power management: Through Power down
Mode from I

2

C programming.

• Spread spectrum for EMI control ( ± 0.25% center).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: < 250ps

• 3V66 – 3V66: <175ps

• PCI – PCI: <500ps

• For group skew specifications, please refer to group
timing relationship.

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
1 These are double strength.

1

1

1

*SEL24_48#/REF0

VDDREF

X1
X2

GNDREF

GND3V66

3V66-0
3V66-1
3V66-2

VDD3V66

VDDPCI

*FS0/PCICLK0

**FS1/PCICLK1

GNDPCI
PCICLK2
PCICLK3
PCICLK4

VDDPCI
PCICLK5
PCICLK6

GNDPCI

PD#

SCLK

SDATA

VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz/FS2**
48MHz/FS3*
48MHz/FS4*
VDD48

1

1

ICS9248-138

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz [1:0]
24_48MHz

CPUCLK [1:0]

2

3

2

8

7

SDRAM [7:0]

IOAPIC

PCICLK [6:0]

SDRAM_F

3V66 [2:0]

X1

X2

XTAL
OSC

CPU

DIVDER

SDRAM
DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

SDATA

SCLK

FS[4:0]

PD#

Control

Logic

Config.

Reg.

/ 2

REF0

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Additional frequencies selectable through I2C programming.

4SF3SF2SF1SF0SF

UPC

)zHM(

MARDS

)zHM(

66V3

)zHM(

KLCICP
)zHM(

CIPAOI

)zHM(
00000 76.6600.00176.6633.3376.61
00001 78.6603.00178.6634.3327.61
00010 76.8600.30176.8633.4361.71
00011 43.1700.70143.1766.5338.71
00100 00.00100.00176.6633.3376.61
00101 03.00103.00178.6634.3327.61
00110 00.30100.30176.8633.4371.71
00111 00.70100.70143.1766.5348.71
01000 33.33133.33176.6633.3376.61
0100 1 37.33137.33178.6634.3327.61
01010 33.73133.73176.8633.4371.71
01011 00.02100.02100.0600.0300.51
01100 33.33100.00176.6633.3376.61
01101 37.33103.00178.6634.3327.61
01110 33.73100.30176.8633.4371.71
01111 00.02100.0900.0600.0300.51

11010 00.06100.06100.0800.0400.02
1110 1 00.06100.02100.0800.0400.02
11011 76.66176.66143.3876.1448.02
11110 76.66100.52143.3876.1448.02

Preliminary Product Preview

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

2

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system.

Spread spectrum may be enabled through I

2

C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I

2

C interface allows changing functions, stop clock programming and frequency selection.

PIN NUMBER PIN NAME TYPE DESCRIPTION

SEL2 4_ 4 8 MHz# IN

Logic inputs frequency select I/O /US B output,
When a "0" is latched, output frequency = 48MHz
Wh en a "1 " is latched, ou t

p

ut frequency = 24MHz

REF0 OUT 14.318 MHz reference clock.

2, 10, 1 1 , 18 , 2 5,

30, 38

VDD PWR

3.3V P o wer supply for SDR A M output buffers, PCI output buffers,
reference out

p

ut buffers and 48M Hz output
3 X1 IN Crystal input,nominally 14.318MHz.
4 X2 OUT Crystal output, nominally 14 .318 MHz.

5, 6, 14, 21, 29, 34,

42

GND P W R Gro und pin for 3V outputs.

9, 8, 7 3V66 [2:0] OU T 3.3V C locks

FS0 IN Frequency s e lect p in .

PCICLK0 OUT PCI clock output

FS1 IN Frequency s e lect p in .

PCICLK1 OUT PCI clock output

20, 19, 17, 16, 15 PCICLK [6:2] OUT P C I clock outputs.

22

PD# IN

Async hrono us active low input pin used to power down the devi c e into a low
po wer state. The internal clocks ar e disabled and the VCO and th e crys tal ar e
stopped. The latency of the pow er dow n will not be greater than 3ms.

23

SCLK IN Clock input of I2C input, 5V tolerant input

24

SDATA IN Data input for I2C serial input, 5V tolerant input

FS4 IN Frequency s e lect p in .

48MH z OUT 48MHz output clocks

FS3 IN Frequency s e lect p in .

48MH z OUT 48MHz output clocks

FS2

IN Frequency select pin.

24_48MHz OUT 24 or 48MHz output

31 SDRA M _F OUT

Free running SDRAM - used for feed back to chipset, should remain on
alwa

y

s.

32, 33, 35, 36, 37,

39, 40, 41,

SD R AM [7:0] OU T SD R AM clock outputs

43 GNDLCPU PWR Ground pin for the CPU clocks.

44, 45 CPUC LK [1:0] OUT C P U clock outputs.

46 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V
47 IOA P IC OUT 2.5V clock output

1

26

28

12

13

27

3

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

I2C is a trademark of Philips Corporation

tiBnoitpircseDDWP

tiB

4:7,2

2tib7tib6tib5tib4tib

KLCUPC

)zHM(

MARDS

)zHM(

66V3

)zHM(

KLCICP
)zHM(

CIPAOI

)HM(

egatnecerPdaerpS

0000,0

4SF3SF2SF1SF0SF
00000 76.6600.00176.6633.3376.61daerpSnwoD%5.0-ot0
0000 1 78.6603.00178.6634.3327.61daerpSretneC%52.0±
00010 76.8600.30176.8633.4361.71daerpSretneC%52.0±
00011 43.1700.70143.1776.5338.71daerpSretneC%52.0±
00100 00.00100.00176.6633.3376.61daerpSnwoD%5.0-ot0
00101 03.00103.00178.6634.3327.61daerpSretneC%52.0±
00110 00.30100.30176.8633.4371.71daerpSretneC%52.0±
00111 00.70100.70143.1776.5348.71daerpSretneC%52.0±
01000 33.33133.33176.6633.3376.61daerpSnwoD%5.0-ot0
01001 37.33137.33178.6634.3327.61daerpSretneC%52.0±
01010 33.73133.73176.8633.4371.71daerpSretneC%52.0±
01011 00.02100.02100.0600.0300.51daerpSretneC%52.0±
01100 33.33100.00176.6633.3376.61daerpSnwoD%5.0-ot0
01101 37.33103.00178.6634.3327.61daerpSretneC%52.0±
01110 33.73100.30176.8633.4371.71daerpSretneC%52.0±
01111 00.02100.0900.0600.0300.51daerpSretneC%52.0±

10000 00.63100.63100.8600.4300.71daerpSretneC%52.0±
1000 1 00.04100.04100.0700.5305.71daerpSretneC%52.0±
10010 76.24176.24143.1776.5348.71daerpSretneC%52.0±
1001 1 33.54133.54176.2733.6371.81daerpSretneC%52.0±
10100 00.63100.20100.8600.4300.71daerpSretneC%52.0±
1010 1 00.04100.50100.0700.5305.71daerpSretneC%52.0±
10110 76.24100.70143.1776.5348.71daerpSretneC%52.0±
1011 1 33.54100.90176.2733.6371.81daerpSretneC%52.0±
11000 76.64176.64143.3776.6343.81daerpSretneC%52.0±
1100 1 33.35133.35176.6733.8371.91daerpSretneC%52.0±
11010 00.06100.06100.0800.0400.02daerpSretneC%52.0±
11011 76.66176.66143.3876.1448.02daerpSretneC%52.0±
11100 76.64100.01143.3776.6343.81daerpSretneC%52.0±
11101 00.06100.02100.0800.0400.02daerpSretneC%52.0±
11110 76.66100.52143.3876.1448.02daerpSretneC%52.0±
11111 00.00200.00276.6633.3376.61daerpSretneC%52.0±

3tiB

stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0

4:6,2tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

daerpSretneC%52.0±delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte 1: SDRAM Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X#2SF
6tiB-X#1SF
5tiB131 F_MARDS
4tiB231 7MARDS

3tiB331 6MARDS

2tiB531 5MARDS

1tiB631 4MARDS

0tiB731 3MARDS

Byte 4: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB621 0-zHM84
1tiB721 1-zHM84
0tiB821 zHM84_42

Byte 3: 3V66, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X#4SF
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-X#3SF
3tiB-1 devreseR
2tiB71 0-66V3
1tiB81 1-66V3
0tiB91 2-66V3

Byte 2: PCI, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1#0SF
6tiB021 6KLCICP

5tiB911 5KLCICP

4tiB711 4KLCICP

3tiB611 3KLCICP

2tiB511 2KLCICP

1tiB311 1KLCICP

0tiB211 0KLCICP

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.

Byte 5: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X #84_42LES

6tiB110FER

5tiB741 CIPAOI

4tiB441 1KLCUPC

3tiB541 0KLCUPC

2tiB931 2MARDS

1tiB041 1MARDS

0tiB141 0MARDS

TIB#NIPDWPNOITPIRCSED

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte 6: Control Register
(1= enable, 0 = disable)

Note: Dont write into this register, writing into this

register can cause malfunction

5

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Chara cteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless othe rwis e s t ate d)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Volt age V

IH

2V

DD

+0.3 V

Input L ow Volta ge V

IL

VSS-0.3 0.8 V

Input High Current I

IH

VIN = V

DD

-5 5

µ

A

Input L ow Current I

IL1

VIN = 0 V; Inputs with no pull-up resistors -5

µ

A

Input L ow Current I

IL2

VIN = 0 V; Inputs with pull-up resistors -200

µ

A

Operating I

DD3.3OPCL

= 0 pF; Sele ct @ 66M 100 mA

Supply C urrent

Power Down I

DD3.3PDCL

= 0 pF; With input address to Vdd or GND 600

µ

A

Supply C urrent

Input freque nc y F

i

VDD = 3.3 V; 14.318 MHz

Pin Inductance L

p

in

7nH

Input C a pac it anc e

1

C

IN

Logic Inputs 5 pF

C

out

Out put pin c a pa cita nc e 6 pF

C

INX

X 1 & X2 pins 27 45 pF

Transition Time

1

T

trans

To 1s t crossing of targe t Freq. 3 mS

Se ttling T ime

1

T

s

From 1st c rossing to 1% ta rget Freq. 3 mS

Clk St abiliz a tion

1

T

STAB

From VDD = 3.3 V to 1% ta rget Freq. 3 m S

Delay t

PZH,tPZH

output enable de la y (all outputs) 1 10 nS

t

PLZ,tPZH

output disable de lay (all outputs) 1 10 nS

1

G uarenteed by design, not 100% tested in production.

Group Timing Relationship Table

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V

DD

+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.

puorGzHM66UPC

zHM001MARDS

zHM001UPC

zHM001MARDS

zHM331UPC

zHM001MARDS

zHM331UPC

zHM331MARDS

tesffOecnareloTtesffOecnareloTtesffOecnareloTtesffOecnareloT

MARDSotUPCsn5.2sp005sn0.5sp005sn0.0sp005sn57.3sp005

66V3otUPCsn5.7sp005sn0.5sp005sn0.0sp005sn0.0sp005

66V3otMARDSsn0.0sp005sn0.0sp005sn0.0sp005sn57.3sp005

ICPot66V3sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005

ICPotICPsn0.0sn0.1sn0.0sn0.1sn0.0sn0.1sn0.0sn0.1

TOD&BSUhcnysAA/NhcnysAA/NhcnysAA/NhcnysAA/N

6

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical C h a ra cteristics - 3V66

TA = 0 - 70C; VDD = 3. 3 V + /- 5 % ; CL = 10-30 pF (unless o therwis e s ta ted)

PARA METER SYMBOL COND I TIO N S MIN TYP MAX UN ITS

O utput Impedance R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impedance R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

Output High Current I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 -33 mA

Output Low Current I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2. 4 V 0.5 2 ns

Fall Time t

f1

1

VOH = 2.4 V, VOL = 0. 4 V 0.5 2 ns

Duty Cycle d

t1

1

VT = 1. 5 V 45 55 %

Skew t

sk1

1

VT = 1. 5 V 175 ps

Jitter

t

jcyc-cyc

VT = 1. 5 V

500 ps

1

G uarenteed by des ign, not 100% tes ted in pr oduc tion.

Electrical Characteristics - CPU

TA = 0 - 70C, V

DDL

= 2.5 V +/-5%; CL = 1 0 - 20 pF (unless othe rwis e s ta te d)

PARA METER SYMBOL CON D ITI O NS MIN TYP MAX UNITS

O utput Impe da nc e R

DSP2B

1

VO = VDD*(0.5) 13.5 45

Ω

O utput Impe da nc e R

DSN2B

1

VO = VDD*(0.5) 13.5 45

Ω

Output High Voltage V

OH2B

IOH = -1 mA 2 V

Output Low Voltage V

OL2B

IOL = 1 mA 0.4 V

O utput High Cur r e nt I

OH2B

V

OH @MIN

= 1.0V , V

OH@ MAX

= 2 . 375 V -27 -27 mA

O utput Low C urrent I

OL2B

V

OL @MIN

= 1. 2V , V

OL@ MAX

= 0. 3 V 27 30 mA

Rise Time t

r2B

1

VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 ns

F all T ime t

f2B

1

VOH = 0.4 V, VOL = 2 . 0 V 0.4 1.6 ns

Duty Cycle d

t2B

1

VT = 1.25 V 45 55 %

Skew t

sk2B

1

VT = 1.25 V 250 ps

Jitter

t

jcyc-cyc

1

VT = 1.25 V

250 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

7

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise s ta te d)

PARA METER SYMBOL CONDITION S MIN TYP MAX UNITS

O utput Impe da nc e R

DSP3

1

VO = VDD*(0.5) 10 24

Ω

O utput Impe da nc e R

DSN3

1

VO = VDD*(0.5) 10 24

Ω

Output High Voltage V

OH3

IOH = -1 mA 2.4 V

Output Low Voltage V

OL3

IOL = 1 mA 0.4 V

O utput High Current I

OH3

V

OH @MIN

= 2.0 V, V

OH@ MAX

=3.135 V -54 - 46 mA

O utput L o w Cur rent I

OL3

V

OL@ MIN

= 1.0 V, V

OL@ MAX

=0.4 V 54 53 mA

Rise Time T

r3

1

VOL = 0. 4 V, VOH = 2 .4 V 0. 4 1.6 ns

Fa ll T ime T

f3

1

VOH = 2.4 V, VOL = 0 .4 V 0. 4 1.6 ns

Duty Cycle D

t3

1

VT = 1.5 V 45 55 %

Skew T

sk3

1

VT = 1.5 V 2 50 ps

Jitter

t

j

cyc-cyc VT = 1.5 V

250 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - IOAPIC

TA = 0 - 70C;V

DDL

= 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance R

DSP4B

1

VO = VDD*(0.5) 9 30

Ω

Output Impedance R

DSN4B

1

VO = VDD*(0.5) 9 30

Ω

Output High Voltage V

OH4\B

IOH = -5.5 mA 2 V

Output Low Voltage V

OL4B

IOL = 9.0 mA 0.4 V

Output High Current I

OH4B

V

OH@ min

= 1.0 V, V

OH@ MAX

= 2.375 V -27 -27 mA

Output Low Current I

OL4B

V

OL@ MIN

= 1.2 V, V

OL@ MAX=

0.3 V 27 30 mA

Rise Time t

r4B

1

VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns

Fall Time t

f4B

1

VOH = 2.0 V, VOL = 0.4 V 0.4 1.6 ns

Duty Cycle d

t4B

1

VT = 1.25 V 45 55 %

Skew t

sk4

1

250 ps

Jitter

t

jcyc-cyc

VT = 1.25 V

500 ps

1

Guarenteed by design, not 100% tested in production.

8

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - PCI

TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 1 0-30 pF (unless oth erwise state d)

PARA METER SYMBOL CONDITION S MIN TYP MAX UNITS

O utput Impe da nc e R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impe da nc e R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

O utput High Cur r e nt I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V-33 -33 mA

O utput L o w Cur rent I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2.4 V 0.5 2 ns

F all T ime t

f1

1

VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle d

t1

1

VT = 1.5 V 45 55 %

Skew t

sk1

1

VT = 1.5 V 5 00 ps

Jitter

t

jcyc-cyc

VT = 1.5 V

500 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - REF, 48MHz_0

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 -20 pF (unless oth er w ise sta ted)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance R

DSP5

1

VO = VDD*(0.5) 20 60

Ω

Output Impedance R

DSN5

1

VO = VDD*(0.5) 20 60

Ω

Output High Voltage V

OH5

IOH = 1 mA 2.4 V

Output Low Voltage V

OL5

IOL = -1 mA 0.4 V

Output High Current I

OH5

V

OH @MIN

=1 V, V

OH@MAX

= 3.135 V -29 -23 mA

Output Low Current I

OL5

V

OL@MIN

=1.95 V, V

OL@MIN

=0.4 V 29 27 mA

Rise Time t

r5

1

VOL = 0.4 V, VOH = 2.4 V 4 ns

Fall Time t

f5

1

VOH = 2.4 V, VOL = 0.4 V 4 ns

Duty Cycle d

t5

1

VT = 1.5 V 45 55 %

Skew T

sk

VT = 1.5 V 250 ps

t

jcy

c-cyc

1

VT = 1.5 V; Fixed Clocks 500 ps

t

jcyc-cyc

1

VT = 1.5 V; Ref C l ock s

1000 ps

1

Guarentee d by de sign, not 100% teste d in pro duc tion.

Jitter

9

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.

 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

10

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Fig. 1

Shared Pin Operation ­Input/Output Pins

The I/O pins designated by (input/output) on the ICS9248­138 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

2K 

8.2K 

Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.

11

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.

Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.

3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

CPUCLK

3V66

PCICLK

VCO

Crystal

PD#

12

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.

Ordering Information

ICS9248yF-138

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T

MIN MAX MIN MAX

A 2.413 2.794 .095 .110

A1 0.203 0.406 .008 .016

b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420

E1 7.391 7.595 .291 .299

e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N

α

0° 8° 0° 8°

VARIATIONS

MIN MAX MIN MAX

48 15.748

16.002

.620 .630

56 18.288

18.542

.720 .730

JEDEC MO-118

DOC# 10-0034

6/1/00

REV B

SYMBOL

SEE VARIATIONS

SEE VARIATIONS

In Millimeters

COMMON DIMENSIONS

In Inches

COMMON DIMENSIONS

SEE VARIATIONS

N

D mm.

D (inch)

SEE VARIATIONS