Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-127
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9248-127 Rev C 8/18/00
Pin Configuration
• Up to 124MHz frequency support.
• Spread Spectrum for EMI control 0 to -0.5% down
spread and ±0.25% center spread
• Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
• Provides the following system clocks
- 4-CPUs @ 3.3V, up to 124MHz.
- 13-SDRAMs @3.3V, up to 124MHz
(including SDRAM_F)
- 6-PCI (including 1 free running, PCICLK_F)
@3.3V, CPU/2 or CPU/3.
- 1-24MHz @3.3V fixed.
- 1-48MHz @3.3V fixed.
- 2-REF @3.3V, 14.318MHz.
• Efficient Power management scheme through PCI
and STOP CLOCKS.
48-Pin SSOP
Power Groups
VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F
VDDPCI, GNDPCI = PCICLKS, PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
* Internal Pull-up Resistor of 240K to VDD
The ICS9248-127 is the single chip clock solution for Desktop
designs using the VIA MVP4 and Aladdin 7 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
127 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
VDDREF
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SD ATA
SCLK
REF1/FS2*
VDDCPU
CPUCLK_F
CPUCLK0
GND
CPUCLK1
CPUCLK2
CLK_STOP#
GND
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24MHz/FS1*
ICS9248-127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
CPUCLK_F
CPUCLK (2:0)
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
S DATA
SCLK
FS(3:0)
MODE
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
LATCH
POR
2
3
12
5
4
4
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9248-127
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,03,72,91,41,6,1
74,63
DDVRWPylppusrewopV3.3
2
0FERTUO
REGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41
sdaolSUBASIrofreffub
#POTS_ICP
1
NI
woltupninehw,level0cigoltaskcolcKLCICPstlaH
)0=EDOM,edomelibomnI(
,22,61,9,3
44,04,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO.zHM813.41yllanimon,tuptuolatsyrC
7
F_KLCICPTUO
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
EDOM
2,1
NI
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf2nip
.tupnIdehctaL
8
3SF
1
NI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUO
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
01,11,21,31)1:4(KLCICPTUO
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
,82,12,02,81,71
,53,43,23,13,92
83,73
)0:11(MARDSTUO
nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
.)tespihcybdellortnoc(
32ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
42KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
52
zHM42TUOkcolctuptuozHM42
1SF
2,1
NI.tupnIdehctaL.niptcelesycneuqerF
62
zHM84TUOkcolctuptuozHM84
0SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
93F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI
"0"cigoltaMARDS&KLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel
54,34,24)0:2(KLCUPCTUOUPCDDVybderewop,stuptuokcolcUPC
64F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF
84
1FERTUO.kcolcecnereferzHM813.41
2SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
Page 3
3
ICS9248-127
Functionality
VDD1,2,3 = 3.3V±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
Mode Pin - Power Management Input Control
3SF2SF1SF0SF
UPC
)zHM(
ICP
)zHM(
0000 00.42133.14
0001 00.02100.04
0010 99.41133.83
0011 99.90166.63
0100 00.50100.53
0101 13.3856.14
0110 00.0800.04
0111 00.5705.73
1000 00.00133.33
100 1 91.5937.13
10 10 13.3877.72
10 11 00.7933.23
1100 00.0900.03
1101 00.0700.53
1110 28.6614.33
1111 00.0600.03
EDOM
)tupnIdehctaL(
2niP
0
#POTS_ICP
)tupnI(
1
0FER
)tuptuO(
Page 4
4
ICS9248-127
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default.
Note 1. Default at Power-up will be for latched logic inputs to define frequency.
I2C readback of the power up default indicate the revision ID code in bit 2,
6:4 as shown.
I2C is a trademark of Philips Corporation
tiBnoitpircseDDWP
7tiB
noitaludoMmurtcepSdaerpSretneC%52.0±-0
noitaludoMmurtcepSdaerpSnwoD%5.0-ot0-1
1
tiB
]4:6,2[
]4:6,2[tiB
KLCUPC
)zHM(
KLCICP
)zHM(
1etoN
010,0
000000.42133.14
100000.02100.04
010099.41133.83
110099.90166.63
001000.50100.53
101013.3856.14
011000.0800.04
111000.5705.73
000100.00133.33
100191.5937.13
010113.3877.72
110100.7933.23
001100.0900.03
101100.0700.53
011128.6614.33
111100.0600.03
3tiB
stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0
]4:6,2[tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
delbanEmurtcepSdaerpS-1
2etoN
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Note 2. To ensure normal operation, Bit 7 needs to be "0" when in non - spread spectrum
mode (Bit 1 = 0).
Page 5
5
ICS9248-127
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-X #0SFdehctaL
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-X #2SFdehctaL
6tiB641 )tcanI/tcA(F_KLCUPC
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB931 )tcanI/tcA(F_MARDS
2tiB241 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB541 )tcanI/tcA(0KLCUPC
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB711 )evitcanI/evitcA(11MARDS
6tiB811 )evitcanI/evitcA(01MARDS
5tiB021 )evitcanI/evitcA(9MARDS
4tiB121 )evitcanI/evitcA(8MARDS
3tiB821 )evitcanI/evitcA(7MARDS
2tiB921 )evitcanI/evitcA(6MARDS
1tiB131 )evitcanI/evitcA(5MARDS
0tiB231 )evitcanI/evitcA(4MARDS
Page 6
6
ICS9248-127
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(
tiB#niPDWPnoitpircseD
7tiB431 )tcanI/tcA(3MARDS
6tiB531 )tcanI/tcA(2MARDS
5tiB731 )tcanI/tcA(1MARDS
4tiB831 )tcanI/tcA(0MARDS
3tiB621 )tcanI/tcA(zHM84
2tiB521 )tcanI/tcA(zHM42
1tiB841 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
Page 7
7
ICS9248-127
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAM ETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Supply Current I
DD3.3
CL = 0 pF; Select @ 66M 77 180 mA
Input frequency F
i
VDD = 3.3 V; 14.318 MHz
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 36 45 pF
Transition Time
1
T
trans
To 1st crossing of target Freq. 1.5 3 ms
Settling Time
1
T
s
From 1st crossing to 1% target Freq. ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq. 3 ms
Skew
1
T
CPU-BUSVT
= 1.5 V;
1.0 2.2 4.0 ns
1
Guarenteed by design, not 100% tested in production.
Input Capacitance
1
Page 8
8
ICS9248-127
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
Vo =VDD*(0.5) 10 20
Ω
Output Impedance R
DSN2B
1
Vo =VDD*(0.5) 10 20
Ω
Output High Voltage V
OH2B
IOH = -12 mA 2.0 2.3 V
Output Low Voltage V
OL2B
IOL = 12 mA 0.2 0.4 V
Output High Current I
OH2B
VOH = 1.7 V -41 -19 mA
Output Low Current I
OL2B
VOL = 0.7 V 19.0 37.0 mA
Rise Time
1
t
r2B
VOL = 0.4 V, VOH = 2.4 V 0.4 1.28 2.0 ns
Fall Time
1
t
f2 B
VOH = 2.4 V, VOL = 0.4 V 0.4 1.49 2.0 ns
Duty Cycle
1
d
t2B
VT = 1.5 V 48.0 54.8 58.0
%
Skew window
1
t
sk2B
VT = 1.5 V 222 250 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2BVT
= 1.5 V
152 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP5
1
Vo =VDD*(0.5) 20 60
Ω
Output Impedance R
DSN5
1
Vo =VDD*(0.5) 20 60
Ω
Output High Voltage V
OH5
IOH = -14 mA 2.4 2.9 V
Output Low Voltage V
OL5
IOL = 6.0 mA 0.25 0.4 V
Output High Current I
OH5
VOH = 2.0 V -42 -20 mA
Output Low Current I
OL5
VOL = 0.8 V 10 18 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 1.74 4.0 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 2.05 4.0 ns
Duty Cycle
1
d
t5
VT = 1.5 V, 45 53.2 55 %
Jitter
1
t
jabs5
VT = 1.5 V
307 800 ps
1
Guaranteed by design, not 100% tested in production.
Page 9
9
ICS9248-127
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYM BOL CONDITIONS M IN TYP MAX UNITS
Output Impedance R
DSP2A
1
Vo =VDD*(0.5) 10 20
Ω
Output Impedance R
DSN2A
1
Vo =VDD*(0.5) 10 20
Ω
Output High Voltage V
OH2A
IOH = -28 mA 2.4 2.8 V
Output Low Voltage V
OL2A
IOL = 19 mA 0.3 0.4 V
Output High Current I
OH2A
VOH = 2.0 V -72 -42 mA
Output Low Current I
OL2A
VOL = 0.8 V 33 50 mA
Rise Time
1
t
r2A
VOL = 0.4 V, VOH = 2.4 V 0.5 0.97 1.6 ns
Fall Time
1
t
f2 A
VOH = 2.4 V, VOL = 0.4 V 0.5 1.07 1.6 ns
Duty Cycle
1
d
t2A
VT = 1.5 V 45 49.1 55 %
Skew Window
1
t
sk2A
VT = 1.5 V 145 250 ps
Skew (Buffer-In to SDRAM )
1
t
sk2A
VT = 1.5 V
3.55ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
Vo=V
DD
*(0.5) 12 23 55 Ω
Output Impedance R
DSN1
1
Vo=V
DD
*(0.5) 12 20 55 Ω
Output High Voltage V
OH1
IOH = -18 mA 2.4 2.9 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.2 0.4 V
Output High Current
I
OH1
VOH = 2.0 V -58 -22
mA
Output Low Current
I
OL1
VOL = 0.8 V 25 52
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.38 2.0 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.65 2.0 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 51.1 55 %
Skew window
1
t
sk1
VT = 1.5 V 236 500 ps
Jitter
t
jabs1
1
VT = 1.5 V
214 500 ps
1
Guaranteed by design, not 100% tested in production.
Page 10
10
ICS9248-127
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
Page 11
11
ICS9248-127
Fig. 1
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248127 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Page 12
12
ICS9248-127
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-127. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-127.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-127
CLK_STOP# signal. SDRAM (0:11) are controlled as shown.
5. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
IOAPIC
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
Page 13
13
ICS9248-127
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-127. It is used to turn off the PCICLK [4:0] clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-127 internally. The minimum that the PCICLK [4:0] clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency
is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCICLK
PCI_STOP#
Page 14
14
ICS9248-127
Ordering Information
ICS9248yF-127-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
MIN MA X MIN MA X
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
VARIATIONS
MIN MA X MI N MA X
28 9.398
9.652
.370 .380
34 11.303
11.557
.445 .455
48 15.748
16.002
.620 .630
56 18.288
18.542
.720 .730
64 20.828
21.082
.820 .830
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inc he s
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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