Page 1
ICS9248-126
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
9248-126 Rev C 9/6/00
Recommended Application:
Motherboard Single chip clock solution for Pentium II/III and
K6 processors, using SIS540/SIS630 style chipset.
Output Features:
• 3- CPUs @ 2.5/3.3V, up to 166MHz.
• 14 - SDRAM @ 3.3V
• 7- PCI @3.3V,
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz).
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support FS0-FS3 trapping status bit for I
2
C read back.
• Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I
2
C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 500ps
• PCI - PCI: < 500ps
• CPU - SDRAM: < 500ps
• CPU - PCI: 1 - 4ns
Functionality
CPU2.5_3.3#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (13:0)
PCICLK (6:0)
X1
X2
XTAL
OSC
PCI
CLOCK
DIVDER
CPU
CLOCK
DIVDER
SDRAM
CLOCK
DIVDER
S DATA
SCLK
FS(3:0)
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
LATCH
2
3
14
7
4
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6
VDDREF
* REF0/FS3
GND
X1
X2
VDDPCI
*PCICLK0/FS1
*PCICLK1/FS2
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDSDR
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
S DATA
SCLK
1
REF1
VDDLCPU
CPUCLK0
CPUCLK1
GND
CPUCLK2
VDDSDR
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GNDSDR
SDRAM7
SDRAM6
VDDSDR
SDRAM5
SDRAM4
VDDSDR
48MHz/FS0*
24_48MHz/CPU2.5_3.3#*
1
ICS9248-126
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3SF2SF1SF0SF
UPC
)zHM(
MARDS
)zHM(
KLCICP
)zHM(
000 0 6.660.0013.33
000 1 0.0010.0013.33
00 10 0.0510.0015.73
00 1 1 3.3310.0013.33
010 0 8.666.3314.33
010 1 0.0013.3313.33
0110 0.0010.0515.73
0111 3.3313.3313.33
10 0 0 8.668.664.33
10 0 1 0.790.793.23
10 1 0 0.070.5010.53
10 1 1 0.590.597.13
110 0 0.597.6217.13
110 1 0.2110.2113.73
1110 0.793.9212.23
111 1 2.692.691.23
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9248-126
Third party brands and names are the property of their respective owners.
The ICS9248-126 is the single chip clock solution for
Desktop/Notebook designs using the SIS 540/630 style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-126
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
General Description
Power Groups
VDDREF = REF, X1, X2
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM, supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLCPU = CPUCLKs
Pin Configuration
PIN NUMBER PIN NAME TYPE DESCRIPTION
1, 6, 15, 19, 27, 30,
36, 42
VDD PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference out
p
ut buffers and 48MHz output
REF0 OUT 14.318 MHz reference clock.
FS3 IN Frequency select pin.
3, 10, 16, 22,
33, 39, 44
GND PWR Ground pin for 3V outputs.
4 X1 IN Crystal input,nominally 14.318MHz.
5 X2 OUT Crystal output, nominally 14.318MHz.
FS1 IN Frequency select pin.
PCICLK0 OUT PCI clock outputs.
FS2 IN Frequency select pin.
PCICLK1 OUT PCI clock outputs.
14, 13, 12, 11, 9 PCICLK (6:2) OUT PCI clock outputs.
41, 40, 38, 37, 35,
34, 32, 31, 29, 28,
21, 20, 18, 17
SDRAM (13:0) OUT SDRAM clock outputs
23 SDATA I/O
Data
p
in for I2C circuitry 5V tolerant
24 SCLK IN Clock input of I2C input, 5V tolerant input
CPU2.5_3.3# IN Voltage select 2.5V when high - 3.3V when low
24_48MHz OUT Clock output for super I/O/USB default is 24MHz
FS0 IN Frequency select pin.
48MHz OUT 48MHz output clock
43, 45, 46 CPUCLK (2:0) OUT CPU clock outputs.
47 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V
48 REF1 OUT 14.318 MHz reference clock.
26
2
7
8
25
Page 3
3
ICS9248-126
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
ACK
Byte 1
AC
K
Byte 2
AC
K
Byte 3
ACK
Byte 4
AC
K
Byte 5
AC
K
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Coun
t
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte
4
ACK
Byte
5
ACK
Byte
6
ACK
Stop Bit
How to Read:
Page 4
4
ICS9248-126
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I
2
C readback for Bits 7, 2, 6:4 indicate the revision code.
I
2
C is a trademark of Philips Corporation
tiBnoitpircseDDWP
7tiB2tiB6tiB5tiB4tiBUPCMARDSICPSS
01000
1etoN
,2,7tiB
4:6tiB
0 0000 6.660.0013.33%5.0-ot0
0 0001 0.0010.0013.33%5.0-ot0
00010 0.0510.0015.73%52.0±
00011 3.3310.0013.33%5.0-ot0
00100 8.666.3314.33%5.0-ot0
00101 0.0013.3313.33%5.0-ot0
00110 0.0010.0515.73%52.0±
00111 3.3313.3313.33%5.0-ot0
01000 8.668.664.33%52.0±
01001 0.790.793.23%5.0-ot0
01010 0.070.5010.53%52.0±
01011 0.590.597.13%52.0±
01100 0.597.6217.13%52.0±
01101 0.2110.2113.73%52.0±
0 1110 0.793.9213.23%5.0-ot0
0 1111 2.692.691.23%5.0-ot0
10000 8.662.0014.33%52.0±
10001 2.0012.0014.33%52.0±
10010 0.6617.0117.72%52.0±
10011 2.0016.3314.33%52.0±
10100 0.570.0015.73%52.0±
10101 3.380.5213.13%52.0±
10110 0.5010.0410.53%52.0±
10111 6.3316.3314.33%52.0±
11000 3.0110.7418.63%52.0±
11001 0.5113.3513.83%52.0±
11010 0.0210.0210.03%52.0±
11011 0.8310.8315.43%52.0±
11100 0.0410.0410.53%52.0±
11101 0.5410.5413.63%52.0±
1 1110 5.7415.7419.63%52.0±
1 1111 0.0610.0617.62%52.0±
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:6,2,7tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Page 5
5
ICS9248-126
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )#3.3_5.2UPC(
6tiB411 )tcanI/tcA(6KLCICP
5tiB311 )tcanI/tcA(5KLCICP
4tiB211 )tcanI/tcA(4KLCICP
3tiB111 )tcanI/tcA(3KLCICP
2tiB91 )tcanI/tcA(2KLCICP
1tiB81 )tcanI/tcA(1KLCICP
0tiB71 )tcanI/tcA(0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB521 zHM84_42
6tiB621 zHM84
5tiB141 31MARDS
4tiB041 21MARDS
3tiB831 11MARDS
2tiB731 01MARDS
1tiB531 9MARDS
0tiB431 8MARDS
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1#3SF
4tiB-1#2SF
3tiB-1#1SF
2tiB-1#0SF
1tiB841 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB231 )tcanI/tcA(7MARDS
6tiB131 )tcanI/tcA(6MARDS
5tiB921 )tcanI/tcA(5MARDS
4tiB821 )tcanI/tcA(4MARDS
3tiB121 )tcanI/tcA(3MARDS
2tiB021 )tcanI/tcA(2MARDS
1tiB811 )tcanI/tcA(1MARDS
0tiB711 )tcanI/tcA(0MARDS
TIB#NIPDWPNOITPIRCSED
7tiB-1
#84_42LES
)0ottesnehwzHM84(
)1ottesnehwzHM42(
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB341 )tcanI/tcA(2KLCUPC
2tiB541 )tcanI/tcA(1KLCUPC
1tiB641 )tcanI/tcA(0KLCUPC
0tiB-1 devreseR
TIB#NIPDWPNOITPIRCSED
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this
register can cause malfunction
Page 6
6
ICS9248-126
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - I nput/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = V
DDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Operating I
DD3.3OP66CL
= 0 pF; Select @ 66MHz 148 180 mA
Supply Current I
DD3.3OP100CL
= 0 pF; Select @ 100MHz 150 180 mA
I
DD3.3OP133CL
= 0 pF; Select @ 133MHz 161 mA
Input frequency F
i
VDD = 3.3 V; 11 14.318 16 MHz
Input Capacitance
1
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 36 45 pF
Transition Time
1
T
trans
To 1st crossing of target Freq. 3 ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq. 3 ms
Skew
t
CPU-PCI
VT = 1.5 V
12.394 ns
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating I
DD2.5OP66CL
= 0 pF; Select @ 66.8 MHz 6.13 30 mA
I
DD2.5OP100CL
= 0 pF; Select @ 100 MHz 9.22 mA
Supply Current I
DD2.5OP133CL
= 0 pF; Select @ 133 MHz 11.6 mA
t
CPU-SDRAMVT
= 1.5 V; VTL = 1.25 V 273 500 ps
t
CPU-PCI
VT = 1.5 V; VTL = 1.25 V
12.254 ns
1
Guaranteed by design, not 100% tested in production.
Skew
1
Page 7
7
ICS9248-126
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2A
1
VO=VDD*(0.5) 10 36.5 40 Ω
Output Impedance R
DSN2A
1
VO=VDD*(0.5) 10 29 40 Ω
Output High Voltage V
OH1a
IOH = -20.0 mA 2 2.85 V
Output Low Voltage V
OL1
a
IOL = 12 mA 0.31 0.4 V
Output High Current I
OH1a
VOH = 2 V -45 -19 mA
Output Low Current I
OL1
a
VOL = 0.8 V 22 29 mA
Rise Time t
r1
a
1
VOL = 0.4 V, VOH = 2.4 V 0.4 1.24 2 ns
Fall Time t
f1
a
1
VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 2 ns
Duty Cycle d
t1
a
1
VT = 1.5 V 45 52.6 62 %
Skew t
sk1
a
1
VT = 1.5 V 80.8 175 ps
Jitter, Cycle-to-cycle
t
jcyc-cyc1a
1
VT = 1.5 V
128 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2A
1
VO=VDD*(0.5) 10 36.5 40
Ω
Output Impedance R
DSN2A
1
VO=VDD*(0.5) 10 29 40
Ω
Output High Voltage V
OH1B
IOH = -12.0 mA 2 2.3 V
Output Low Voltage V
OL1B
IOL = 12 mA 0.31 0.4 V
Output High Current I
OH1B
VOH = 1.7 V -39 -21 mA
Output Low Current I
OL1B
VOL = 0.7 V 19 26 mA
Rise Time t
r1B
1
VOL = 0.4 V, VOH = 2.0 V 1.03 1.6 ns
Fall Time t
f1B
1
VOH = 2.0 V, VOL = 0.4 V 1.26 1.6 ns
Duty Cycle d
t1
a
1
VT = 1.5 V 45 51.7 55 %
Skew t
sk1
a
1
VT = 1.5 V 66.1 175 ps
Jitter, Cycle-to-cycle t
jcy
c-cyc1B
1
VT = 1.25 V CPU, SDRAM Synchronous 170 250 ps
t
jcyc-cyc1B
1
VT = 1.25 V CPU, SDRAM Asynchronous
124.5 350 ps
1
Guaranteed by design, not 100% tested in production.
Page 8
8
ICS9248-126
Third party brands and names are the property of their respective owners.
Electrical Characteristics - REF_1;24/48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5%; CL = 20 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP5
1
VO=V
DD
*(0.5) Output P 20 42 60 Ω
Output Impedance R
DSN5
1VO=V
DD
*(0.5) Output N 20 43 60 Ω
Output High Voltage V
OH4
IOH = -14 mA 2.4 2.6 V
Output Low Voltage V
OL4
IOL = 6mA 0.3 0.4 V
Output High Current I
OH4
VOH = 2.0 V -26 -22 mA
Output Low Current I
OL4
VOL = 0.8 V 16 22 mA
Rise Time
1
24_48MHz
t
r4
VOL = 0.4 V, VOH = 2.4 V 1.75 4 ns
Fall Time
1
24_48MHz
t
f4
VOH = 2.4 V, VOL = 0.4 V 1.88 4 ns
Duty Cycle
1
24_48MHz
d
t4
VT = 1.5 V 45 52 55 %
Rise Time
1
REF_1
t
r4
VOL = 0.4 V, VOH = 2.4 V 2.22 4 ns
Fall Time
1
REF_1
t
f4
VOH = 2.4 V, VOL = 0.4 V 2.43 4 ns
Duty Cycle
1
REF_1
d
t4
VT = 1.5 V 45 51.1 55 %
Jitter, 24_48MHz
t
jcyc4
VT = 1.5 V
727 1000 ps
Jitter, REF_1
t
jcyc4
VT = 1.5 V
-1 1208 1500 ns
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, REF_0
TA = 0 - 70C; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
VO=V
DD
*(0.5) 12 21 55 Ω
Output Impedance R
DSP1
1
VO=V
DD
*(0.5) 12 21 55 Ω
Output High Voltage V
OH2
IOH = -18 mA 2.4 3.3 V
Output Low Voltage V
OL2
IOL = 9.4 mA 0.17 0.4 V
Output High Current I
OH2
VOH = 2.0 V -62 -22 mA
Output Low Current I
OL2
VOL = 0.8 V 16 57 mA
Rise Time
1
48MHz
t
r2
VOL = 0.4 V, VOH = 2.4 V 1.78 2 ns
Fall Time
1
48MHz
t
f2
VOH = 2.4 V, VOL = 0.4 V 1.92 2 ns
Duty Cycle
1
48MHz
d
t2
VT = 1.5 V 45 52 55 %
Rise Time
1
REF_0
tr2 V
OL
= 0.4 V, VOH = 2.4 V 1.32 2 ns
Fall Time
1
REF_0
t
f2
VOH = 2.4 V, VOL = 0.4 V 1.56 2 ns
Duty Cycle
1
REF_0
dt2 V
T
= 1.5 V 45 52.2 55 %
Jitter, 48MHz
t
jcyc2
VT = 1.5 V
500.6 700 ps
Jitter, REF_0 tjcyc2
V
T
= 1.5 V
-350 1243 1500 ps
Page 9
9
ICS9248-126
Third party brands and names are the property of their respective owners.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2A
1
VO=V
DD
*(0.5) 10 17 20 Ω
Output Impedance R
DSN2A
1
VO=V
DD
*(0.5) 10 18 20 Ω
Output High Voltage V
OH3
IOH = -25 mA 2.4 2.9 V
Output Low Voltage V
OL3
IOL = 20 mA 0.32 0.4 V
Output High Current I
OH3
VOH = 2.0 V -73 -40 mA
Output Low Current I
OL3
VOL = 0.8 V 41 50 mA
Rise Time T
r3
1
VOL = 0.4 V, VOH = 2.4 V 0.4 1.14 2 ns
Fall Time T
f3
1
VOH = 2.4 V, VOL = 0.4 V 0.4 1.38 2 ns
Duty Cycle D
t3
1
VT = 1.5 V 47 51.8 57 %
Skew
1
(0-1,2,4,5,7,10,11)
T
sk1
VT = 1.5 V 155.5 250 ps
Skew
1
(0-6,6,8,9,12,13)
T
sk1
VT = 1.5 V 298.5 500 ps
Jitter, Cycle-to-cycle
t
jcyc
VT = 1.5 V
369.17 650 ps
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; V
DDL
= 2.5 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
VO=V
DD
*(0.5) 12 21 55 Ω
Output Impedance R
DSP1
1
VO=V
DD
*(0.5) 12 21 55 Ω
Output High Voltage V
OH2
IOH = -18 mA 2.4 3.3 V
Output Low Voltage V
OL2
IOL = 9.4 mA 0.17 0.4 V
Output High Current I
OH2
VOH = 2.0 V -62 -33 mA
Output Low Current I
OL2
VOL = 0.8 V 38 43 mA
Rise Time
1
t
r2
VOL = 0.4 V, VOH = 2.4 V 1.62 2.2 ns
Fall Time
1
t
f2
VOH = 2.4 V, VOL = 0.4 V 1.81 2.2 ns
Duty Cycle
1
d
t2
VT = 1.5 V 45 49.8 55 %
Skew
1
t
sk2
VT = 1.5 V 200 500 ps
Jitter, Cycle-to-cycle
t
jcyc2
VT = 1.5 V
-350 306 350 ps
1
Guaranteed by design, not 100% tested in production.
Page 10
10
ICS9248-126
Third party brands and names are the property of their respective owners.
Fig. 1
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248126 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Page 11
11
ICS9248-126
Third party brands and names are the property of their respective owners.
Connections to VDD:
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
C3
1
Clock Load
C1
C1
2
C3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
Ferrite
Bead
VDD
C2
22µF/20V
Tantalum
Ferrite
Bead
VDD
C2
22µF/20V
Tantalum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Ground
2.5V Power Route
3.3V Power Route
3.3V Power Route
Page 12
12
ICS9248-126
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9248yF-126-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BA SIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
V A RIATIONS
MIN MAX MIN MAX
28 9.398
9.652
.370 .380
34 11.303
11.557
.445 .455
48 15.748
16.002
.620 .630
56 18.288
18.542
.720 .730
64 20.828
21.082
.820 .830
J E D E C MO- 118
DOC # 10-0034
6/1/00
REV B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeter s
COMMON DIMENSIONS
In In c he s
COMMON DIMENSIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
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