Datasheet AV9248F-112, ICS9248F-112 Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS9248-112

Third party brands and names are the property of their respective owners.

Block Diagram

9248- 112 Rev A 2/7/00

Recommended Application:

810/810E type chipset.

Output Features:

• 2- CPUs @2.5V, up to 150MHz.

• 9 - SDRAM @ 3.3V, up to150MHz including
1 free running

• 8 - PCICLK @ 3.3V

• 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz

• 2 - 3V66MHz @ 3.3V, 2X PCI MHz

• 1- 48MHz, @3.3V fixed.

• 1- 24MHz, @3.3V fixed

• 1- REF @3.3V, 14.318MHz.

Features:

• Up to 166MHz frequency support

• Support FS0-FS3 strapping status bit for I

2

C read back.

• Support power management: Through Power down
Mode from I

2

C programming.

• Spread spectrum for EMI control ( ± 0.25% center).

• Spread can be enabled or disabled to all 32 frequencies
throuth I

2

C.

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: < 250ps

• 3V66 – 3V66: <175ps

• PCI – PCI: <500ps

• CPU-SDRAM<500ps

• For group skew specifications, please refer to group
timing relationship.

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull up to VDD.
1 These are double strength.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Additional frequencies selectable through I2C programming.

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0000 08.6602.00108.6604.3307.6104.33
0001 00.8600.20100.8600.4300.7100.43
0010 03.00103.00178.6634.3327.6134.33
0011 00.30100.30176.8633.4371.7133.43
0100 37.33103.00178.6634.3327.6134.33
0101 00.54157.80105.2752.6331.8152.63
0110 37.33103.00178.6634.3327.6134.33
0111 33.73100.30176.8633.4371.7133.43
100 0 00.04100.50100.0700.5305.7100.53
100 1 00.04100.04133.3976.6433.3276.64
1010 00.81100.81176.8733.9376.9133.93
101 1 00.42100.42176.2833.1476.0233.14
1100 07.33107.33131.9875.4482.2275.44
110 1 00.73100.73133.1976.5438.2276.54
1110 00.05105.21100.5705.7357.8105.73
1111 05.2757.80105.2752.6331.8152.63

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

Preliminary Product Preview

2

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

Power Groups

GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]

The ICS9248-112 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.

Spread spectrum may be enabled through I

2

C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-112
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I

2

C interface allows changing functions,

stop clock programming and frequency selection.

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3

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

ACK

Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

ACK

Dummy Command Code

ACK

Dummy Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Write:

4

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
* These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.

I2C is a trademark of Philips Corporation

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00001 00.8600.20100.8600.4300.7100.43retneC%52.0-/+
00010 03.00103.00178.6634.3327.6134.33retneC%52.0-/+
00011 00.30100.30176.8633.4371.7133.43retneC%52.0-/+
00100 37.33103.00178.6634.3327.6134.33retneC%52.0-/+
00101 00.54157.80105.2752.6331.8152.63retneC%52.0-/+
00110 37.33103.00178.6634.3327.6134.33retneC%52.0-/+
00111 33.73100.30176.8633.4371.7133.43retneC%52.0-/+
01000 00.04100.50100.0700.5305.7100.53retneC%52.0-/+
01001 00.04100.04133.3976.6433.3276.64retneC%52.0-/+
01010 00.81100.81176.8733.9376.9133.93retneC%52.0-/+
01011 00.42100.42176.2833.1476.0233.14retneC%52.0-/+
01100 07.33107.33131.9875.4482.2275.44retneC%52.0-/+
01101 00.73100.73133.1976.5438.2276.54retneC%52.0-/+
01110 00.05105.21100.5705.7357.8105.73retneC%52.0-/+
01111 05.2757.80105.2752.6331.8152.63retneC%52.0-/+
10000 00.5705.21100.5705.7357.8105.73retneC%52.0-/+
10001 00.3800.3876.7238.3129.638.31retneC%52.0-/+
10010 00.01100.01133.3776.6333.8176.63retneC%52.0-/+
10011 00.02100.02100.0800.0400.0200.04retneC%52.0-/+
10100 00.52100.52133.3876.1438.0276.14retneC%52.0-/+
1010 1 52.9688.30152.9636.4313.7136.43retneC%52.0-/+
10110 00.0700.50100.0700.5305.7100.53retneC%52.0-/+
10111 76.6700.51176.6733.8371.9133.83retneC%52.0-/+
11000 00.54100.54176.6933.8471.4233.84retneC%52.0-/+
11001 05.6657.9905.6652.3336.6152.33retneC%52.0-/+
11010 00.05100.05100.00100.0500.5200.05*retneC%52.0-/+
11011 57.9957.9905.6652.3336.6152.33*retneC%52.0-/+
11100 00.55100.55133.30176.1538.5276.15retneC%52.0-/+
11101 05.66105.66100.11105.5557.7205.55retneC%52.0-/+
11110 33.35100.51176.6733.8371.9133.83retneC%52.0-/+
11111 00.33157.9905.6652.3336.6152.33*retneC%52.0-/+

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5

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte 1: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

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5tiB-X#2SF

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2tiB621 zHM84

1tiB-1 )devreseR(

0tiB031 F_MARDS

Byte 4: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

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6tiB81 1_66V3
5tiB71 0_66V3
4tiB-X #CIPAOI_QERF
3tiB641 CIPAOI
2tiB-X#1SF
1tiB341 1KLCUPC
0tiB441 0KLCUPC

Byte 3: PCI, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB021 7KLCICP
6tiB911 6KLCICP
5tiB711 5KLCICP
4tiB611 4KLCICP

3tiB511 3KLCICP

2tiB311 2KLCICP

1tiB211 1KLCICP

0tiB111 0KLCICP

Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB131 7MARDS

6tiB231 6MARDS

5tiB431 5MARDS

4tiB531 4MARDS

3tiB631 3MARDS

2tiB831 2MARDS

1tiB931 1MARDS

0tiB041 0MARDS

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.

Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-1 devreseR

TIB#NIPDWPNOITPIRCSED

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)

Note: Dont write into this register, writing into this

register can cause malfunction

6

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Fig. 1

Shared Pin Operation ­Input/Output Pins

The I/O pins designated by (input/output) on the ICS9248­112 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

2K W

8.2K W

Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.

7

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.

Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.

3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

8

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supp ly Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Inpu t High Volt a ge V

IH

2V

DD

+0.3 V

Input Low Voltage V

IL

VSS-0.3 0.8 V

Input High Current I

IH

VIN = V

DD

-5 5

µ

A

Input Low Current I

IL1

VIN = 0 V; Inputs with no pull-up re sistors -5 2.0

µ

A

Input Low Current I

IL2

VIN = 0 V; Inputs with pull-up resistors -200 -100

µ

A

Operati n g I

DD3.3OP

CL = 0 pF; Select @ 66M 60 100 mA

Suppl y C urre nt

Power Down I

DD3.3PDCL

= 0 pF; With i nput a dd ress t o Vdd or GND 400 600

µ

A

Suppl y C urre nt

Inpu t fre que nc y F

i

VDD = 3.3 V; 14.318 MH z

Pin Inductance L

p

in

7nH

Input Capacitance

1

C

IN

Logic Inputs 5 pF

C

o

ut

O ut put pin c a pa c i ta nc e 6 pF

C

INX

X 1 & X2 pins 27 45 pF

Transition Time

1

T

t

rans

To 1st cr o ssing of target Freq. 3 mS

Settling Time

1

T

s

From 1st cr ossing t o 1 % target Freq. 3 mS

Clk Stabilization

1

T

STAB

From VDD = 3. 3 V to 1% target Fre q. 3 mS

Delay t

PZH,tPZH

output ena b le de l a y (all output s ) 1 10 nS

t

PLZ,tPZH

output disable dela y (all output s ) 1 10 nS

1

G ua rentee d by de sign, not 100 % te sted in pr odu c tio n.

puorG

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MARDSotUPCsn5.2sp005sn0.5sp005sn0.0sp005

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66V3otMARDSsn0.0sp005sn0.0sp005sn0.0sp005

ICPot66V3sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005

ICPotICPsn0.0sn0.1sn0.0sn0.1sn0.0sn0.1

TOD&BSUhcnysAA/NhcnysAA/NhcnysAA/N

Group Timing Relationship Table

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V

DD

+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.

9

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Elect r ical C har acter i st ics - 3V66

TA = 0 - 70C; VDD = 3.3 V +/-5 % ; CL = 1 0-30 pF (unless oth erw is e s ta te d)

PARA METER SY MBOL CON D ITI O NS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impe da nc e R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

O utput High Cur r e nt I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 -33 mA

O utput L o w Cur rent I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2.4 V 0.5 2 ns

F all T ime t

f1

1

VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle d

t1

1

VT = 1.5 V 45 55 %

Skew t

sk1

1

VT = 1.5 V 175 ps

Jitter t

jcyc-cyc

VT = 1.5 V 500 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - CPU

TA = 0 - 70C, V

DDL

= 2.5 V +/-5 % ; CL = 1 0 - 20 pF (unless othe rwis e stated)

PARA METER SY MBOL CON D ITI O NS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP2B

1

VO = VDD*(0.5) 13.5 45

Ω

O utput Impe da nc e R

DSN2B

1

VO = VDD*(0.5) 13.5 45

Ω

Output High Voltage V

OH2B

IOH = -1 mA 2 V

Output Low Voltage V

OL2B

IOL = 1 mA 0.4 V

O utput High Cur r e nt I

OH2B

V

OH @MIN

= 1.0V , V

OH@ MAX

= 2 . 375 V -27 -27 m A

O utput Low C urrent I

OL2B

V

OL @MIN

= 1. 2V , V

OL@ MAX

= 0. 3 V 27 30 m A

Rise Time t

r2B

1

VOL = 0. 4 V, VOH = 2 . 0 V 0.4 1.6 ns

F all T ime t

f2B

1

VOH = 0.4 V, VOL = 2 . 0 V 0.4 1.6 ns

Duty Cycle d

t2B

1

VT = 1.25 V 455055%

Skew t

s

k2B

1

VT = 1.25 V 250 ps

Jitter

t

jcyc-cyc

1

VT = 1.25 V

250 p s

1

G ua renteed by de s ign, not 100% te s te d in production.

10

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Electrical Characteristics - IOAPIC

TA = 0 - 70C;V

DDL

= 2. 5 V + /- 5% ; CL = 10 - 20 pF (unless otherwise s ta te d)

PARA METER SY MBOL CON D I TIONS MIN TYP MAX U NITS

O utput Impe da nc e R

DSP4B

1

VO = VDD*(0.5) 9 30

Ω

O utput Impe da nc e R

DSN4B

1

VO = VDD*(0.5) 9 30

Ω

Output High Voltage V

OH4\ BIOH

= -5.5 mA 2 V

Output Low Voltage V

OL4B

IOL = 9.0 mA 0.4 V

O utput High Current I

OH4B

V

OH@ min

= 1.0 V, V

OH@ MAX

= 2 .375 V -27 -27 mA

O utput L o w Cur rent I

OL4B

V

OL@ MIN

= 1.2 V, V

OL@ MAX=

0.3 V 27 30 mA

Rise Time t

r

4B

1

VOL = 0. 4 V, VOH = 2 .0 V 0.4 1.6 ns

Fa ll T ime t

f4B

1

VOH = 2.0 V, VOL = 0 .4 V 0.4 1.6 ns

Duty Cycle d

t4B

1

VT = 1.25 V 45 55 %

Jitter t

jcyc-cyc

VT = 1.25 V 500 ps

Skew

t

sk4

1

250 p s

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)

PARA METER SY MBOL CONDITION S MIN TYP MAX UNI TS

O utput Impe da nc e R

DSP3

1

VO = VDD*(0.5) 10 24

Ω

O utput Impe da nc e R

DSN3

1

VO = VDD*(0.5) 10 24

Ω

Output High Voltage V

OH3

IOH = -1 mA 2.4 V

Output Low Voltage V

OL3

IOL = 1 mA 0.4 V

O utput High Cur r e nt I

OH3

V

OH @MIN

= 2.0 V, V

OH@ MAX

=3.135 V -54 -46 mA

Output Low Current I

OL3

V

OL@ MIN

= 1.0 V, V

OL@ MAX

=0.4 V 54 53 mA

Rise Time T

r

3

1

VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns

Fa ll T ime T

f

3

1

VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns

Duty Cycle D

t

3

1

VT = 1.5 V 45 55 %

Skew T

s

k3

1

VT = 1.5 V 250 ps

Jitter t

j

cyc-cyc VT = 1.5 V 250 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

11

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Elect r ical C har acter i st ics - PC I

TA = 0 - 70C; VDD = 3.3 V +/-5 % ; CL = 1 0-30 pF (unless oth erw is e s ta te d)

PARA METER SY MBOL CON D ITI O NS MIN TYP MAX UN I TS

O utput Impe da nc e R

DSP1

1

VO = VDD*(0.5) 12 55

Ω

O utput Impe da nc e R

DSN1

1

VO = VDD*(0.5) 12 55

Ω

Output High Voltage V

OH1

IOH = -1 mA 2.4 V

Output Low Voltage V

OL1

IOL = 1 mA 0.55 V

O utput High Cur r e nt I

OH1

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 -33 mA

O utput L o w Cur rent I

OL1

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA

Rise Time t

r1

1

VOL = 0. 4 V, VOH = 2.4 V 0.5 2 ns

F all T ime t

f1

1

VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle d

t1

1

VT = 1.5 V 45 55 %

Skew t

sk1

1

VT = 1.5 V 500 ps

Jitter t

jcyc-cyc

VT = 1.5 V 500 ps

1

G ua renteed by de s ign, not 100% te s te d in production.

Electrical Characteristics - REF, 48MHz

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise state d)

PARA METER SY MBOL CON DI TIONS MIN TYP MA X UNITS

O utp ut I mpedanc e R

DSP5

1

VO = VDD*(0.5) 20 60

Ω

O utp ut I mpedanc e R

DSN5

1

VO = VDD*(0.5) 20 60

Ω

Output High Voltage V

OH5

IOH = 1 mA 2.4 V

Output Low Voltage V

OL5

IOL = -1 mA 0.4 V

O utput High Cur r e nt I

OH5

V

OH @MIN

=1 V, V

OH@MAX

= 3.135 V - 29 -23 m A

O utput Low Cu r rent I

OL5

V

OL@MIN

=1.95 V, V

OL@MIN

=0.4 V 29 27 mA

Rise Time t

r5

1

VOL = 0. 4 V, VOH = 2.4 V 1.8 4 nS

F all Time t

f5

1

VOH = 2.4 V, VOL = 0.4 V 1.7 4 nS

Duty Cycle d

t5

1

VT = 1.5 V 45 55 %

Jitter t

jcyc-cyc

1

VT = 1.5 V; Fixed Cloc ks 500 pS

t

jcyc-cyc

1

VT = 1.5 V; R e f Clo cks 1000 pS

Skew T

sk

VT = 1.5 V 250 pS

1

G ua r e nte e d by de s ign, not 100% te s te d in production.

12

ICS9248-112

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

LOBMYSSNOISNEMIDNOMMOCSNOITAIRAVDN

.NIM.MON.XAM.NIM.MON.XAM

A590.201.011.CA026.526.036.84

1A800.210.610.

2A780.090.490.

B800.-5310.

c500.-010.
DsnoitairaVeeS
E192.592.992.

eCSB520.0
H593.-024.
h010.310.610.
L020.-040.
NsnoitairaVeeS

µ

°0- °8

48 Pin 300 mil SSOP Package

“For current dimensional specifications, see JEDEC 95.”

.093
DIA. PIN (Optional)

D/2

E/2

BOTTOM VIEW

A

2

SEE
DETAIL “A”

-E-

c

END VIEW

H

Pin 1

TOP VIEW

Index
Area

PARTING LINE

L

DETAIL “A”

A

1

-e-

B

A

SIDE VIEW

-C-

-D-

SEATING
PLANE

.004

C

Dimensions in inches

Ordering Information

ICS9248yF-112-T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T