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Integrated
Circuit
ICS9159-13
Systems, Inc.
Frequency Generator and Integrated Buffer for PENTIUM
General Description
The ICS9159-13 generates all clocks required for high
speed RISC or CISC microprocessor systems such as 486,
Pentium, PowerPC, etc. Four different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions. A test mode is provided to drive all
clocks directly.
High drive BCLK outputs provide typically greater than
1V/ns slew rate into 30pF loads. PCLK outputs provide
typically better than 1V/ns slew rate into 20pF loads while
maintaining 50±5% duty cycle.
Block Diagram
Features
Generates up to six processor and six bus clocks, plus
two reference clocks
Synchronous clocks skew matched to 250ps window
on PCLKs and 500ps window on BCLKs
Processor and bus clocks synchronized to each other,
PCLK to BCLK skew window 600ps max
Test clock mode eases system design
3.0V - 5.5V supply range
28-pin SOIC package
Pin Cnfiguration
9159-13 Rev B 060497
28-Pin SOIC
Functionality
OEN FS1 FS0 PCLK BCLK REF
1 0 0 50MHz 25 MHz 14.318 MHz
1 0 1 66.6 MHz 33.3 MHz 14.318 MHz
1 1 0 60 MHz 30 MHz 14.318 MHz
1 1 1 TCLK/2 TCLK/4 TCLK
0 X X Tristate Tristate Tristate
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of Motorola Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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ICS9159-13
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1, 8, 14, 20, 26 VDD PWR Power for logic, CPU and fixed frequency output buffers.
2X1 IN
3 X2 OUT XTAL output which includes XTAL load capacitance.
4, 11, 17, 23 GND PWR Grou nd for logic, CP U and fixed frequ ency output b uffers.
6, 7, 9, 10,
24, 25
13, 12 FS(0:1) IN
15, 16, 18, 19,
21, 22
5 OEN IN OEN tristates all outputs when low. This input has an internal pull-up device.
28, 27 REF( 0:1) OUT
PCLK(0:3) OUT
BCLK(0:5) OUT Bus clock outputs are fixed at one half the PCLK frequency.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and fee dback bias for a 12 - 16 M Hz crystal, nominall y 14.31818 MHz.
Processor clock output s which are a multiple of the i nput reference frequency as
shown in the table above.
Frequency multiplier select pins. See table above. These inputs have internal pull-up
devices.
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14 .31818 MHz.
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ICS9159-13
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V
Logic Inputs ....................................................................... GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature ............................................................. 0°C to +70°C
Storage Temperature ........................................................................... 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70° C unless otherwise stated
DC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Curr ent I
Output Low Current
Output High Curr ent
Output Low Current
Output High Curr ent
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1
1
1
1
1
1
1
1
Supply Curr ent I
IL --0.2VDD V
IH 0.7VDD --V
IL VIN=0V -28.0 -10. 5 - µA
IH V IN=VDD -5.0 - 5.0 µ A
IOL VOL=0.8V; for PCLKS & BCLKS 30.0 47.0 - mA
IOH VOL=2.0V; for PCLKS & BCLKS - -66.0 -42.0 mA
IOL VOL=0.8V; for REF CLKs 25.0 38.0 - mA
IOH VOL=2.0V; for REF CLKs - -47.0 -30.0 mA
VOL IOL=15mA; for PCLKS & BCLKS - 0.3 0.4 V
VOH IOH=-30mA; for PCLKS & BCLKS 2.4 2.8 - V
VOL IOL=12.5mA; for REF CLKs - 0.3 0.4 V
VOH IOH=-20mA; for REF CLKs 2.4 2.8 - V
DD @66.5 MHz; all outputs unloaded - 55 110 mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Electrical Characteristics at 3.3V
VDD = 3.1 3.7 V, TA = 0 70° C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Jitter, One Sigma
Jitter, Absolute
Jitter, One Sigma
Jitter, Absolute
Input Freque ncy
Logic Input Ca pacitance
1
1
1
1
1
1
1
1
1
1
1
Crystal Oscillator Capacitance
Power-on Time
Frequency Se ttling Time
Clock Skew Window
Clock Skew Window
Clock Skew Window
1
1
1
1
1
1
Tr1 20pF load, 0.8 t o 2.0V PCLK & BCL K - 0.9 1 .5 ns
Tf1 20pF load, 2.0 t o 0.8V PCLK & BCLK - 0.8 1.4 n s
Tr2 20pF load, 20 % to 80% PCLK & BCLK - 1.5 2.5 ns
Tf2 20pF load, 80 % to 20% PCLK & B CLK - 1.4 2.4 ns
Dt 20pF load @ VOUT=1.4V 45 50 55 %
Tj1s1
Tjab1
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
Tj1s2 REF CLK; Load=20pF - 1 3 %
Tjab2 REF CLK; Load=20pF -5 2 5 %
Fi 12.0 14.318 16.0 MHz
CIN Logic input pins - 5 - pF
CINX X1, X2 pins - 18 - pF
ton
ts
From VDD=1.6V to 1 st crossing of 66. 5 MHz
DD supply ramp < 40m s
V
From 1st crossing of acquisition to <
1% settling
Tsk1 PCLK to PCLK; Load=20pF; @1.4V - 150 250 ps
Tsk2 BCLK to BCLK; Load=20pF; @1.4V - 300 500 ps
Tsk3 PCLK to BCLK; Load=20pF; @1.4V - 400 600 ps
AC Characteristics
- 50 150 ps
-250 - 250 ps
-2.54.5ms
-2.04.0ms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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Electrical Characteristics at 5.0V
VDD = 4.5 5.5 V, TA = 0 70° C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICS9159-13
DC Characteristics
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Curr ent I
Output Low Current
Output High Curr ent
Output Low Current
Output High Curr ent
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1
1
1
1
1
1
1
1
Supply Curr ent I
IL --0.8V
IH 2.4 - - V
IL VIN=0V -45 -15 - µA
IH V IN=VDD -5.0 - 5.0 µ A
IOL VOL=0.8V; for PCLKS & BCLKS 36.0 62.0 - mA
IOH VOL=2.0V; for PCLKS & BCLKS - -152 -90.0 mA
IOL VOL=0.8V; for REF CLKs 30.0 50.0 - mA
IOH VOL=2.0V; for REF CLKs - -110.0 -65.0 mA
VOL IOL=20mA; for PCLKS & BCLKS - 0.25 0.4 V
VOH IOH=-70mA; for PCLKS & BCLKS 2.4 4.0 - V
VOL IOL=15mA; for REF CLKs - 0.2 0.4 V
VOH IOH=-50mA; for REF CLKs 2.4 4.7 - V
DD @66.5 MHz; all outputs unloaded - 80.0 160.0 mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Electrical Characteristics at 5.5V
VDD = 4.5 5.5 V, TA = 0 70° C
PARAMETER SYMBOL TEST CONDITIONS MIN T YP MAX UNITS
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Duty Cycle
Jitter, One Sigma
Jitter, Absolute
Jitter, One Sigma
Jitter, Absolute
Input Frequ ency
Logic Input Capa citance
1
1
1
1
1
1
1
1
1
1
1
1
Crystal OscillatorCapacitance
Power-on Time
Frequency Sett ling Time
Clock Skew Window
Clock Skew Window
Clock Skew Window
1
1
1
1
1
1
Tr1 20pF load, 0.8 to 2.0V PCLK & BCLK - 0.55 0.95 ns
Tf1 20pF load, 2.0 to 0.8V PCLK & BCLK - 0.52 0.90 ns
Tr2 20pF load, 20% to 80% P CLK & BCLK - 1.2 2.1 ns
Tf2 20pF load, 80% to 20% PC LK & BCLK - 1.1 2.0 ns
Dt1 20 pF load @ VOUT=1.4V 52 57 62 %
Dt2 20 pF load @ VOUT=50% 45 50 55 %
Tj1s1
Tjab1
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
Tj1s2 REF CLKs; Load=20pF RS=33W - 1 3 %
Tjab2 REF CLKs; Load=20pF RS=33W -5 2 5 %
Fi 12.0 14.318 16.0 MHz
CIN Logic input pins - 5 - pF
CINX X1, X2 pin s - 18 - pF
ton
ts
From VDD=1.6V to 1 st crossing of 66. 5
MHz V
From 1st crossing of acquisition to < 1%
settling
Tsk1 PCLK to PCLK; Load=20pF; @1.4V - 150 250 ps
Tsk2 BCLK to BCLK; Load=20pF; @1.4V - 300 500 ps
Tsk3 PCLK to BCLK; Load =20pF; @1.4V - 400 600 ps
AC Characteristics
DD supply ramp < 40ms
-50150ps
-250 - 250 ps
-2.54.5ms
-2.04.0ms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Ordering Information
ICS9159M-13
Example:
ICS XXXX M-PPP
LEAD COUNT 28L
DIMENSIONL 0.704
SOIC Package
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC, SOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
7
device data to verify that any information being relied upon by the customer is current
and accurate.
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