Datasheet ICS9159M-07 Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS9159-07

Frequency Generator for NexGen

General Description

The ICS9159-07 is a low-cost frequency generator designed
specifically for NexGen Nx586 systems. The integrated
buffer minimizes skew and provides the CPU clocks required
by the NexGen Nx586 microprocessor. A 14.318 MHz
XTAL oscil-lator provides the reference clock to generate
standard Nx586 frequencies. The CPU clock makes gradual
frequency transi-tions without violating the PLL timing of
internal microproc-essor clock multipliers.

Either synchronous (2XCPU/3) or asynchronous (32 MHz)
PCI bus operation can be selected. Green PC systems are
supported through doze mode.

Features

• Three CPU clocks operate up to 65 MHz at 3.3V, plus
smooth transitions

• Selection of nine frequencies, tristate

• Seven BUS clocks support sync or async bus
operation

• Integrated buffer outputs drive up to 10pF loads

• 3.13 to 5.25V (3.3±5%, 5.0±5%) supply range

• 28-pin SOIC package

• Clock duty cycles 45/55

Applications

• Ideal for NexGen Nx586 PCI-based motherboard designs

™

Nx586 Systems

Block Diagram

9159-07 Rev C 060697

NexGen is a trademark of NexGen Corporation.

ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

ICS9159-07

Pin Configuration

28-Pin SOIC

Pin Descriptions

PIN NUMBER PIN NAME TYPE DESCRIPTION

1X1 IN
2 X2 OUT XTAL output which includes XTAL load capacitance.

6,7, 9 CPU(0:2) OUT

3, 11, 23 GND PWR Device Ground.

4, 5, 14 FS(0:2) IN

8, 26 VDD PWR Positive power supply.

10 OE IN Output Enable. All outputs tristate when low.**
12 DOZE# IN Reduces CPU clock frequency to 10 MHz when at a logic low leve l.*
13 BSEL# IN Synchronous and non-synchronous bus clock selector.* ASYNC=0, SYNC=1

15, 16, 18 19,

21, 22, 27

20 V
17 GNDB PWR
24 DISK OUT Fixed 24 MHz clock (with 14. 318 MHz input).

25 KEYBD OUT Fixed 12 MHz clock (with 14.318 MHz input).
28 REF OUT

BCLK(0:6) OUT Bus clock outputs are fixed at 2 ¤3 the PCLK frequency.

B PWR Power for BUS output buffers.

DD

XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12 - 16 MHz XTAL. Normally, 14.318 MHz.

Processor clock outputs which are a multiple of the input reference frequency as
shown in the table below.

Frequency multiplier select pins. See table below. These inputs have internal pull­up devices.*

This ground return path is brought on separately to permit separating the noise
impulses from high output buffers from affecting sensitive internal circuitry.***

REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.

* Internally pulled-up.
** External pull-up resistor of 5 to 20 kW recommended due to dynamic coupling of adjacent CPU pins.
*** Ground for bus clock buffers.

2

ICS9159-07

Functionality

14.318 MHz Input, all frequencies in MHz.

OE FS2 FS1 FS0 DZE CPU (0:2)

1000165 43.3 32
1001160 40 32

1010155.5 37 32
1011151 34 32

1100146.5 31 32
1101142 28 32

1110137.5 25 32
1111135 23.3 32
1XXX010 6.6 32
0 X X X X Tristate Tristate Tristate

BSEL=1 BSEL=0

BUS 0:6

Actual CPU Frequencies

CPU Frequency (MHz) Actual Frequency (MHz)

65 64.98
60 60.03

55.5 55.50
51 51.00

46.5 46.53
42 42.00

37.5 37.48
35 35.00
10 10.00

Tristate Tristate

3

ICS9159-07

Absolute Maximum Ratings

Supply Voltage.......................................................................................................... 7.0 V

Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature .............................................................0°C to +70°C

Storage Temperature........................................................................... –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings ma y cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.

Electrical Characteristics at 3.3V

VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated

DC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage

1

1

1

1

1

1

1

1

Supply Current I

IL

IH

IL

IH

I

OL

I

OH

I

OL

I

OH

V

OL

V

OH

V

OL

V

OH

CC

VIN=0V - 25.0 -5.0 µ A
VIN=V

DD

VOL=0.8V; for PCLKS & BCLKS 30.0 47.0 - mA
VOL=2.0V; for PCLKS & BCLKS - -66.0 -42.0 mA
VOL=0.8V; for fixed CLKs 25.0 38.0 - mA
VOL=2.0V; for fixed CLKs - -47.0 -30.0 mA
IOL=15mA; for PCLKS & BCLKS - 0.3 0.4 V
IOH=-30mA; for PCLKS & BCLKS 2.4 2.8 - V
IOL=12.5mA; for fixed CLKs - 0.3 0.4 V
IOH=-20mA; for fixed CLKs 2.4 2.8 - V

CPU @65.0 MHz; BUS @ 43.3
MHz; all outputs unloaded

- - 0.2V

0.7V

DD

--V

-5.0 - 5.0 µA

- 80.0 130.0 mA

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

DD

V

4

ICS9159-07

Electrical Characteristics at 3.3V

VDD = 3.1 – 3.7 V, TA = 0 – 70°C

AC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle

CPU(0:2)

BUS(0:6)

Jitter, One Sigma

Jitter, Absolute
Input Frequency

Logic Input Capacitance
Crystal Oscillator Capacitance

Frequency Transition Time

1

1

1

1

1

1

Cycle-to-Cycle T

Jitter

1

Slew
Jitter 1Cycle-to-Cycle T

1

Slew

1

1

1

1

1

1

Frequency Transition Time (to DOZE)

Frequency Settling Time

1

CPU to CPU T
CPU to BUS(0:5) T

1

Skew

CPU to BUS(6) T
BUS(0:5) to BUS(0:5) T
BUS(0:5) to BUS(6) T

1

T
T
T
T

SR

SR
T

T

C

C

T

T

SK3S

D

jcc1

jcc2

F

INX

t

SK1

SK2

SK4

SK5

20pF load; 0.8 to 2.0V - 0.9 1.5 ns

r1

20pF load; 2.0 to 0.8V - 0.8 1.4 ns

f1

20pF load; 20% to 80% - 1.5 2.5 ns

r2

20pF load; 80% to 20% - 1.4 2.4 ns

f2

20pF load; VOUT=1.4V 45 50 55 %

t

Load=10pF -150 50 +150 ps
Load=10pF; 0.8 to 2.0V 1.0 1.6 A V/ns

1

Load=10pF -250 - 250 ps
Load=30pF; 0.8 to 2.0V 0.6 1.0 A V/ns

2

Fixed CLK; Load=20pF;

jis

Comp. to the period
Fixed CLK; Load=20pF;

jab

Comp. to the period
A 12.0 14.318 16.0 MHz

i

Logic input pins - 5 - pF

IN

-13%

-25%

X1, X2 pins - 18 - pF
Acquisition from 35 MHz

to 65 MHz (first crossing)

a1

- 0.46 1.4 ms
(and 65 to 35).
Acquisition from 10 MHz
to 65 MHz (first crossing)

a2

- 0.76 2.3 ms
(and 65 to 10)

From 1 st crossing of

s

acquisition to <1% settling.

- 400 - ms

-250 - +250

-600 200 1000

CL=10pF VO=1.5V

-900 -400 110

ps

-500 - +500

-1050 -550 250

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

5

ICS9159-07

Electrical Characteristics at 5.5V

VDD = 4.5 – 5.5 V, TA = 0 – 70°C

PARAM ETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC Characteristics

Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I

Input High Current Output
Enable Pin

Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage

2

1

1

1

1

1

1

1

1

I

IH(OE)

IL

IH

IL

IH

VIN=0V -45.0 -15. 0 A mA
VIN=VDD, other logic inputs -5.0 - 5.0 mA

VIN=VDD, OE pin -5.0 A 400.0 mA

I

OL

I

OH

I

OL

I

OH

V

OL

V

OH

V

OL

V

OH

VOL=0.8V; for PCLKS & BCLKS 36. 0 62. 0 - mA
VOL=2.0V; for PCLKS & BCLKS - -152.0 -90.0 mA
VOL=0.8V; for fixed CLKs 30.0 50.0 - mA
VOL=2.0V; for fixed CLKs - -110.0 -65.0 mA
IOL=20mA; for PCLKS & BCLKS - 0.25 0.4 V
IOH=-70mA; for PCLKS & BCLKS 2.4 4.0 - V
IOL=15mA; for fixed CLKs - 0. 2 0.4 V
IOH=-50mA; for fixed CLKs 2.4 4.7 - V

--0.8V

2.0 - - V

CPU @65.0 MHz;

Supply Current I

CC

BUS @ 43.3 MHz;

- 130. 0 220.0 mA

all outputs unloaded

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

6

Electrical Characteristics at 5.5V

VDD = 4.5 – 5.5 V, TA = 0 – 70°C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle

CPU(0:2)

BUS(0:6)

Jitter, One Sigma

Jitter, Absolute
Input Frequency

Logic Input Capacitance
Crystal Oscillator Capacitance

Frequency Transition Time

Frequency Transition Time (to DOZE)

Frequency Settling Time

Skew

1

1

1

1

1

1

Jitter

Cycle-to-Cycle T

1

Slew

1

Jitter

Cycle-to-Cycle T

1

Slew

1

1

1

1

1

1

1

1

CPU to CPU T
CPU to BUS(0:5) T

1

CPU to BUS(6) T
BUS(0:5) to BUS(0:5) T
BUS(0:5) to BUS(6) T

AC Characteristics

SR

SR
T

T

C

C

T
T
T
T

D

jcc1

jcc2

F

INX

20pF load; 0.8 to 2.0V - 0.55 0.95 ns

r1

20pF load; 2.0 to 0.8V - 0.52 0.90 ns

f1

20pF load; 20% to 80% - 1.2 2.1 ns

r2

20pF load; 80% to 20% - 1.1 2.0 ns

f2

20pF load; VOUT=1.4V 45 50 55 %

t

Load=10pF -150 50 +150 ps
Load=10pF; 0.8 to 2.0V 1.6 2.6 - V/ns

1

Load=10pF -250 - 250 ps
Load=30pF; 0.8 to 2.0V 1.0 1.6 - V/ns

2

Fixed CLK; Load=20pF;

jis

Comp. to the period
Fixed CLK; Load=20pF;

jab

Comp. to the period

i

Logic input pins - 5 - pF

IN

X1, X2 pins - 18 - pF
Acquisition from 35 MHz

T

to 65 MHz (first crossing)

a1

(and 65 to 35).
Acquisition from 10 MHz

T

to 65 MHz (first crossing)

a2

(and 65 to 10)

t

SK1

SK2

SK3S

SK4

SK5

From 1 st crossing of

s

acquisition to <1% settling.

CL=10pF VO=1.5V

ICS9159-07

-13%

-25%

12.0 14.318 16.0 MHz

- 0.50 1.5 ms

- 0.78 2.4 ms

- 400 - ms

-250 - +250

-1600 -800 0

-1750 -1250 -750

-500 - +500

-900 -400 -100

ps

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

7

ICS9159-07

Typical Timing Diagram of Outputs Showing Skew Relationship

Clock Singles

Note that the skew is rising edge to rising edge. The CPU is runniing at VCO/2 and
the BUS clock is runing at VCO/3 resulting in the output rising edges being
coincident every 3rd pulse.

8

ICS9159-07

Ordering Information

ICS9159M-07

Example:

ICS XXXX M-PPP

LEAD COUNT 28L

DIMENSIONL 0.704

SOIC P ackage

Pattern Number(2 or 3 digi t number for parts with ROM code patterns)

Package Type

M=SOIC, SOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS=Standard Device

ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all

9

device data to verify that any information being relied upon by the customer is current
and accurate.