Page 1
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9159-05
Frequency Generator for Pentium
™
/OPTi VIPER Systems
9159-05 Rev F 9/29/98
Block Diagram
The ICS9159-05 is a low cost frequency generator designed
specifically for Pentium/Pentium Pro systems. The integrated
buffer minimizes skew and provides the early CPU clock required
by some chipsets such as the OPTi VIPER. A 14.318 MHz
XTAL oscillator provides the reference clock to generate
standard Pentium frequencies. The CPU clock makes gradual
frequency transitions without violating the PLL timing of
internal micro-processor clock multipliers.
The synchronous bus frequencies are selectable as CPU for
local bus or CPU/2 for PCI bus support. Green PC systems
are supported through power-down, doze, and glitch-free
stop clock modes.
• Four CPU clocks operate up to 66.6 MHz at 3.3V with
glitch-free start and stop plus smooth transitions
• 3-6ns early CPU clock supports OPTi VIPER systems
• Selection of 6 frequencies, tristate, or power-down
• Six BUS clocks support local PCI bus operation
• Skew window between synchronous outputs
• Integrated buffer outputs drive up to 30pF loads
• 3.0V - 3.7V supply range
• 28-pin DIP or 28-pin 300-mil SOIC package
Pentium is a trademark of Intel Corporaton.
PowerPC is a trademark of Motorola Corporation.
Applications
• Ideal for green Pentium/Pentium Pro and 486 PCI
systems such as Pentium, PowerPC etc.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any
28-Pin 300-mil SOIC
Pin Configuration
Page 2
2
ICS9159-05
Functionality
Assuming 14.318 MHz input, all frequencies
in MHz. 14 MHz=14.318 MHz
Notes:
1. 000 mode powers-down the PLL sections and forces the outputs low. To ensure glitch-free start and
stop of the CPU and BUS clocks, enter 000 from 001 and exit 000 through 001.
2. Select is FS0, Fs1 = 00, 01, 10, 11.
3. F is the value of CPU, ECPU & BUS. F value is 66.6, 60, 50 or 33.3 as selected by FS(0:1).
Notes:
1. Where F is Frequency selected by FS (0:1)
2. F value is 66.6, 60, 50 or 33.3.
STOP# BSEL# DOZE# FS0 FS1
CPU (0:2)
(MHz)
ECPU
(MHz)
BUS
(0:5)
(MHz)
FIXED
(MHz)
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
0
X
X
X
X
Select
X
X
X
X
X
X
X
Select
X
X
X
F
F
F/2
F/2
Stop
Stop
Low
Tristate
F
F
F/2
F/2
Run
Stop
Low
Tristate
F
F
F/4
F/2
Run
Stop
Low
Tristate
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
L, L, 14
Tristate
STOP# BSEL# DOZE# FS0 FS1
CPU (0:2)
(MHz)
ECPU
(MHz)
BUS
(0:5)
(MHz)
FIXED
(MHz)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Select
2
Select
2
Select
2
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Select
2
Select
2
Select
2
X
X
X
66.6
60
50
33.3
66.6
60
50
33.3
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Stop
Stop
Low
Tristate
66.6
60
50
33.3
66.6
60
50
33.3
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
33.3
30
25
16.7
66.6
60
50
33.3
16.7
15
12.5
8.3
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
L, L, 14
L, L, 14
Tristate
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ICS9159-05
Pin Descriptions
Note:
1. Internally pulled-up
PIN
NUMBER
PIN NAME TYPE DESCRIPTION
8, 20, 26 VDD PWR Power for logic, C PU and fixed frequency output buffers.
1X1 IN
XTA L o r ext e rna l r efe r enc e f r equ e n cy inp u t . This inp ut inc lude s X TA L lo ad
capacitance and feedback bias for a 4-20 MHz XTAL, normally 14.318 MHz.
2 X2 O UT XTAL output which includes XTAL load ca p ac itance .
3, 11, 23, 17 GND PWR Ground for logic, CPU and fixed frequency output buffers.
6, 7, 9 CPU(0:2) OUT
Processor clock outputs which are a multiple of the input reference frequency as
shown in the ta ble.
4, 5 FS(0:1) IN
Frequency multiplier select pins. See table below. These inputs have internal pullup d e vic e s .
10 ECPU OUT Early CPU clock. Transition precedes CPU clocks.
15, 16, 18,
19,21, 22
BUS(0:5) OUT Bus clock outputs are fixed at 1/2 the PCLK frequency.
12 DOZE#
1
IN Doze mode control. Reduces CPU and BUS clock frequencies by 1/2 when low.
13 BSEL#
1
IN
BUS s e lect for BS EL = 0 , BUS = C P U/ 2
for BSEL = 1, BUS = CPU
14 STOP#
1 Stop Clock. Stops all CPU clock outputs and forces them to a logic low level
synchro nously w ith t he ir ne xt lo w le ve l t r a ns it ion .
24 KEYBD OUT 12 MHz fixed clock (with 14.318 MHz input).
25 DISK OUT 24 MHz fixed clock (with 14.318 MHz input).
27, 28 REF (0:1) OUT
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
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ICS9159-05
Absolute Maximum Ratings
Electrical Characteristics at 3.3V
Supply Voltage .......................................................................................................... 7.0 V
Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature .............................................................0°C to +70°C
Storage Temperature ........................................................................... –65°C to +150°C
VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
IL - - 0.2VDD V
Input High Voltage V
IH 0.7VDD --V
Input Low Current I
IL VIN=0V -25.0 -5 - µA
Input High Current I
IH VIN=VDD -5.0 - 5.0 µA
Output Low Current
1
IOL VOL=0.8V; for CPU & BUS 30.0 47.0 - mA
Output High Current
1
IOH VOL=2.0V; for CPU & BUS - -66.0 -42.0 mA
Output Low Current
1
IOL VOL=0.8V; for fixed CLKs 25.0 38.0 - mA
Output High Current
1
IOH VOL=2.0V; for fixed C LKs - -47.0 -30 .0 mA
Output Low Voltage
1
VOL IOL=15mA; for CPU & BUS - 0.30 .4 V
Output High Voltage
1
VOH IOH=-30mA; for CPU & BUS 2.4 2.8 - V
Output Low Voltage
1
VOL IOL=12.5mA; for fixed CLKs - 0.30 .4
Output High Voltage
1
VOH IOH=-20mA; for fixed CLKs 2.4 2.8 - V
Supply Current
I
DD
@ 66.6 MHz; all outputs
unloaded
- 55 110 mA
I
DDPD @ 000 mode (power-down) 8 20 a
I
DDS @ 001 mode (stop) 35 70 a
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ICS9159-05
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
CPU & BUS
-0.91.5ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
CPU & BUS
- 0.8 1.4 ns
Rise Time
1
Tr2
20pF load, 20% to 80%
CPU & BUS
-1.52.5ns
Fall Time
1
Tf2
20pF load, 80% to 20%
CPU & BUS
- 1.4 2.4 ns
Duty Cycle
1
Dt 20pF load @ V
OUT
=1.4V 455055%
Jitter, One Sigma
1
Tj1s1
CPU & BUS Clocks; Load=20pF,
R
S=33Ω
- 40 150 ps
Jitter, Absolute
1
Tjab1
CPU & BUS Clocks; Load=20pF,
R
S=33Ω
-300 - 300 ps
Jitter, One Sigma
1
Tj1s2 Fixed CLK; Lo ad=20pF - 1 3 %
Jitter, Absolute
1
Tjab2 Fixed CLK; Lo ad=20pF - 2 5 %
Input Freque ncy
1
Fi 4.0 14.318 20.0 MHz
Logic Input Ca pacitance
1
CIN Logic input pins - 5 - pF
Crystal Oscillator Capacitance
1
CINX X1, X2 pins - 18 - pF
Clock Skew Window
1
Tsk1 CPU to CPU; Load=20p F; @1.4V - 150 250 p s
Clock Skew Window
1
Tsk
BUS to BUS;
Load=20pF @1.4V
- 300 500 ps
Clock Skew Window
1
Tsk3
ECPU to CPU;
Load=20pF; @1.4V
3.0 - 6.0 ns
Clock Skew Window
1
TSR4
CPU to BUS;
Load=20pF; @1.4v
0.5 1.0 3.0 ns
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ICS9159-05
28-Pin DIP Package
ICS XXXX N-PPP
Example:
Package Type
N=DIP (Plastic)
Device T ype (consists of 3 or 4 digit numbers)
ICS=Standard Device
Prefix
Ordering Information
ICS9159N-05
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
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7
ICS9159-05
SOIC Package
LEAD COUNT 28L
DIMENSIONL 0.704
ICS XXXX M-PPP
Example:
Package Type
M=SOIC, SOP
Device Type (consists of 3 or 4 digit numbers)
ICS=Standard Device
Prefix
Ordering Information
ICS9159M-05
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any
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