Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-82
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9148-82 Rev A 3/25/99
Pin Configuration
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = AGP (1:2)
VDD5 = Fixed PLL, 48MHz , AGP0
VDDL = CPUCLK (0:2)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-82 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-82
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 3AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 100MHz
- 1 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- CPU(early) PCI : 1-4ns, Center 2.6ns
- AGP - PCI: 500ps
Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9148-82
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
11DDVRWPV3.3lanimon,ylppusrewopLATX,)2:0(feR
2
0FERTUO.kcolcecnereferzhM813.41
5.2_#3.3UPC
2,1
NI
V3.3=WOL,UPCV5.2=hgiH.V5.2roV3.3si2LDDVrehtehwsetacidnI
UPC
1
tupnidehctaL.
2
,72,22,61,9,3
54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
62DDVRWPV3.3lanimon,)5:0(KLCICPdnaF_KLCICProfylppuS
7
F_KLCICPTUO
wekssn4-1htiwsKLCUPChtiwsuonorhcnyS.tuptuokcolcICPgninnureerF
#POTS_ICPybdetceffatonsisihT)ylraeUPC(
1SF
2,1
NI
ehtsnimretedsnipSFrehtohtiwgnolA.tupnIdehctaL.niptcelesycneuqerF
.seicneuwerfPGA&ICP,MARDS,UPC
8
0KLCICPTUO )ylraeUPC(wekssn4-1htiwsKLCUPCsuonuorhcnyS.stuptuokcolcICP
2SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
31,21,11,01)4:1(KLCICPTUO )ylraeUPC(wekssn4-1htiwsKLCUPCsuonuorhcnyS.stuptuokcolcICP
415DDVRWP0PGA,zHM84,LLPdexifrofylppuS
51NIREFFUBNI.sreffubMARDSrofniptupnI
71
#POTS_UPC
1
NI
eliboMni(woltupninehw,level0cigoltaskcolc)3:0(KLCUPCstlaH
)0=EDOM,edoM
11MARDSTUOtuptuokcolcMARDS
81
#POTS_ICP
1
NI
,edomelibomnI(woltupninehw,level0cigoltaskcolc)5:0(KLCICPstlaH
)0=EDOM
01MARDSTUOtuptuokcolcMARDS
,43,23,13,92,82
83,73,53
)9:0(MARDSTUO.stuptuokcolcMARDS
02
#POTS_PGANI
tupninehwlevel"0"cigoltaskcolc)2:1(PGAstlahtupnisuonorhcnysasihT
0PGAtceffatonseoD)0=EDOM,edoMeliboMni(wol
9MARDSTUOtuptuokcolcMARDS
12
#DPNI
lanretni&latsyrc,OCVehtspotStupninwoDrewoPsuonorehcnysasihT
)0=EDOM,edoMeliboMnI(.woL,evitcanehwskcolc
8MARDSTUOtuptuokcolcMARDS
63,03,913DDVRWP
,skcolczHM84,eroCUPC,)11:0(MARDSrofylppuS
.V3.3lanimon
32ATADSNIIroftupniataD
2
.tupnilairesC
42KLCSNIIfotupnikcolC
2
tupniC
52
0PGATUO
ybdetceffatoN.4DDVybderewop,tuptuotroPcihparGdecnavdA
#POTS_PGA
EDOM
2,1
NI
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf12&02,81,71niP
.tupnIdehctaL
62
zHM84TUO.gnimitBSUrofkcolctuptuozHM84
0SF
2,1
NI
ehtsnimretedsnipSFrehtohtiwgnolA.tupnIdehctaL.niptcelesycneuqerF
.seicneuwerfPGA&ICP,MARDS,UPC
44,34,14)3:0(KLCUPCTUOwoL=#POTS_UPCfiwoL.2LDDVybderewop,stuptuokcolcUPC
0421MARDSTUO.tuptuokcolcMARDSkcabdeeF
24LDDVRWPlanimonV3.3roV5.2rehtie,)3:0(UPCrofylppuS
74,64)2:1(PGATUO.4DDVybderewop,stuptuotroPcihparGdecnavdA
844DDVRWP)2:0(PGArofylppuS
Page 3
3
ICS9148-82
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, V
DDL
= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
5.2_#3.3UPC
leveltupnI
)ataDdehctaL(
rofdetceleSreffuB
:tanoitarepo
1DDVV5.2
0DDVV3.3
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
52niP,EDOM
)tupnIdehctaL(
71niP81niP02niP12niP
0
#POTS_UPC
)TUPNI(
#POTS_ICP
)TUPNI(
#POTS_PGA
)TUPNI(
#DP
)TUPNI(
1
11MARDS
)TUPTUO(
01MARDS
)TUPTUO(
9MARDS
)TUPTUO(
8MARDS
)TUPTUO(
#POTS_PGA#POTS_UPC#POTS_ICP
,PGA
KLCUPC
stuptuO
KLCICP
)5:0(
,F_KLCICP
zHM84,FER
MARDSdna
latsyrC
CSO
OCV)2:1(PGA
101 woLdeppotSgninnuRgninnuRgninnuRgninnuRgninnuR
111 gninnuRgninnuRgninnuRgninnuRgninnuRgninnuR
110 gninnuRwoLdeppotSgninnuRgninnuRgninnuRgninnuR
011 gninnuRgninnuRgninnuRgninnuRgninnuRwoLdeppotS
2SF1SF0SF
MARDS,UPC
)zHM(
ICP
)zHM(
PGA
)zHM(
CIPAOI,FER
)zHM(
111 0013.336.66813.41
110 52.5957.135.36813.41
101 3.383.336.66813.41
100 570306813.41
011 575.7357813.41
010 5.8652.435.86813.41
001 8.664.338.66813.41
000 090306813.41
Page 4
4
ICS9148-82
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
AC
K
Byte 2
ACK
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
Page 5
5
ICS9148-82
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
I2C is a trademark of Philips Corporation
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use Bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
tiBnoitpircseDDWP
7tiB
noitarepolamronrof0ebtsuM
0
noitaludoMmurtcepSdaerpS%52.0±-0
noitaludoMmurtcepSdaerpS%6.0±-1
tiB
4:6
4tiB5tiB6tiB
111
011
101
001
110
010
100
000
kcolCUPC
001
52.59
3.38
57
57
5.86
8.66
09
ICP
3.33
57.13
3.33
03
5.73
52.43
4.33
03
PGA
6.66
5.36
6.66
06
57
5.86
8.66
06
1etoN
3tiB
,tceleserawdrahybdetcelessiycneuqerF-0
stupnIdehctaL
)evoba(4:6tiBybdetcelessiycneuqerF-1
0
2tiB
noitarepolamronrof0ebtsuM
0
.epytdaerpsretnecmurtcepSdaerpS-0
.epytdaerpsnwodmurtcepSdaerpS-1
1tiB
lamroN-0
delbanEmurtcepSdaerpS-1
0
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB041 )tcanI/tcA(21MARDS
3tiB-1 )devreseR(
2tiB141 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(0KLCUPC
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Page 6
6
ICS9148-82
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB821 )tcanI/tcA(7MARDS
6tiB921 )tcanI/tcA(6MARDS
5tiB131 )tcanI/tcA(5MARDS
4tiB231 )tcanI/tcA(4MARDS
3tiB431 )tcanI/tcA(3MARDS
2tiB531 )tcanI/tcA(2MARDS
1tiB731 )tcanI/tcA(1MARDS
0tiB831 )tcanI/tcA(0MARDS
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB521 )evitcanI/evitcA(0PGA
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB711
)tcanI/tcA(11MARDS
)ylnOedoMpotkseD(
2tiB811
)tcanI/tcA(01MARDS
)ylnOedoMpotkseD(
1tiB021 )tcanI/tcA(9MARDS
0tiB121 )tcanI/tcA(8MARDS
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 )tcanI/tcA(1PGA
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 )tcanI/tcA(2PGA
0tiB21 )tcanI/tcA(0FER
Byte 6: Optional Register for Possible
Furture Requirements
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for futue
applications.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB-1 )devreseR(
0tiB-1 )devreseR(
Page 7
7
ICS9148-82
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-82. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-82.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Page 8
8
ICS9148-82
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-82. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-82 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Page 9
9
ICS9148-82
Pins 2, 7, 8, 25 & 26 on the ICS9148-82 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Shared Pin Operation Input/Output Pins
Fig. 1
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Page 10
10
ICS9148-82
Fig. 2a
Fig. 2b
Page 11
11
ICS9148-82
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage V
DD, VDDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
0.1 5
µ
A
Input Low Current I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5 2.0
µ
A
Input Low Current I
IL2
VIN = 0 V; Inputs with pull-up resistors -200 -100
µ
A
Operati ng I
DD3.3OP66CL
= 0 pF; Select @ 66.8MHz 112
Supply Current I
DD3.3OP100CL
= 0 pF; Select @ 100MHz 141
Input f requency F
i
VDD = 3.3 V; 12 14.318 16 MHz
Input Capacitance
1
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 36 45 pF
Transition Time
1
T
Tran s
To first crossing of target Freq. 0.65 2 ms
Settling Time
1
T
S
From fi rst c ross i ng to 1% of t arget Fr eq. 0. 36 3 ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target Freq. < 2 2 ms
T
CPU-PCI1
VT=1.5 V; VTL=1.25 V; f=66/100 MHz 1 2. 45 4 ns
Skew
1
T
CPU-PCI1
VT=1.5 V;VTL=1.25 V; f=83/75 MHz 1 3.8 4 ns
T
AGP-PCI1
VT = 1.5 V; AGP leads
390 500 ps
1
Guar antee d by design, not 100% tes ted in production.
mA160
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating I
DD2.5OP66
CL = 0 pF; Select @ 66.8 MHz 14 20
Supply Current I
DD2.5OP100CL
= 0 pF; Select @ 100 MHz 18 20
T
CPU-PCI1
VT=1.5 V; VTL=1.25 V; f=66/100 MHz 1 2.45 4 ns
T
CPU-PCI1
VT=1.5 V;VTL=1.25 V; f=83/75 MHz 1 3.8 4 ns
T
AGP-PCI1
VT=1.5 V; AGP Leads
220 500 ns
1
Guar anteed by de sign, not 100% tested in product ion.
mA
Skew
1
Page 12
12
ICS9148-82
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH2B
IOH = -8.0 mA 2 2.2 V
Output Low Voltage V
OL2B
IOL = 12 mA 0.3 0.4 V
Output High Current I
OH2B
VOH =1.7 V -20 -16 mA
Output Low Current I
OL2B
VOL = 0.7 V 19 26 mA
Rise Time t
r2B
1
VOL = 0.4 V, VOH = 2.0 V 1.5 1.8 ns
Fall Time t
f2B
1
VOH = 2.0 V, VOL = 0.4 V 1.6 1.8 ns
Duty Cycle d
t2B
1
VT = 1.25 V 40 50 55 %
Skew t
sk2B
1
VT = 1.25 V 60 250 ps
Jitter, Single Edge
Displacement
tj
srd2B
1
VT = 1.25 V 200 250 ps
Jitter, One Sigma t
j
1σ2B
1
VT = 1.25 V 31 150 ps
Jitter, Absolute
t
jabs2B
1
VT = 1.25 V
-250 160 +250 ps
1
Guaranteed by design, not 100% tested in pr oduction.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Vol tage V
OH1
IOH = -28 mA 2.4 3 V
Output Low Voltage V
OL1
IOL = 23 mA 0.34 0.4 V
Output High Current I
OH1
VOH = 2.0 V -60 -40 mA
Output Low Current I
OL1
VOL = 0.8 V 41 53 mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.7 2 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 51 55 %
Skew
1
t
sk1
VT = 1.5 V 60 250 ps
Jitter, One Sigma
1
t
j
1σ1a
VT = 1.5 V, Synchronous 28 150 ps
t
j
1σ1b
VT = 1.5 V, Asynchronous 98 250 ps
Jitter, Absolute
1
t
j
abs1a
VT = 1.5 V, Synchronous -250 107 250 ps
t
jabs1b
VT = 1.5 V, Asynchronous
-650 200 650 ps
1
Guaranteed by design, not 100% tested in production.
Page 13
13
ICS9148-82
Electrical Characteristics - S D RAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH3
IOH = -28 mA 2.4 2.8 V
Output Low Voltage V
OL3
IOL = 23 mA 0.35 0.4 V
Output High Current I
OH3
VOH = 2.0 V -63 -40 mA
Output Low Current I
OL3
VOL = 0.8 V 41 51 mA
Rise Tim e T
r3
1
VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns
Fall Time T
f3
1
VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns
Duty Cycle D
t3
1
VT = 1.5 V 455455%
Skew
1
T
sk1
VT = 1.5 V 200 500 ps
Propagati on Delay
T
prop
VT = 1.5 V
46ns
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNIT S
Output High Voltage V
OH1
IOH = -28 mA 2.4 3 V
Output Low Voltage V
OL1
IOL = 23 mA 0.2 0.4 V
Output High Current I
OH1
VOH = 2.0 V -60 -40 mA
Output Low Current I
OL1
VOL = 0.8 V 41 50 mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.3 2 ns
Duty Cycle
1
d
t1
VT = 1.4 V, CPU @ 100MHz 45 50 55 %
Skew
1
t
sk1
VT = 1.5 V 130 250 ps
Jitter, One Sigma
1
t
j
1σ1a
VT = 1.5 V, Synchronous 2 3 %
t
j
abs1a
VT = 1.5 V, Synchronous -5 2.5 5 %
t
jabs1b
VT = 1.5 V, Asynchronous
-6 4.5 6 %
1
Guaranteed by design, not 100% tested in production.
Jitter, Absolute
1
Page 14
14
ICS9148-82
Electrical Characteristics - REF0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
Output High Volt age V
OH5
IOH = -16 mA 2.4 2.6 V
Output Low Volt age V
OL5
IOL = 9 mA 0.26 0.4 V
Output High Current I
OH5
VOH = 2.0 V -32 -22 mA
Output Low Curre nt I
OL5
VOL = 0.8 V 16 27 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 1.3 4 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 2 4 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 55 5 7 %
Jitter, One Sigma
1
t
j1s5
VT = 1.5 V 0.22 3 %
Jitter, Absolute
1
t
jabs5
VT = 1.5 V
-5 0.63 5 %
1
Guaranteed by design, not 100% tested in production.
Page 15
15
ICS9148-82
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Page 16
16
ICS9148-82
SSOP Package
LOBMYS SNOISNEMIDNOMMOC SNOITAIRAV D N
.NIM.MON.XAM.NIM.MON.XAM
A590.101.011.CA026.526.036.84
1A800.210.610.
2A880.090.290.
B800.010.5310.
C500.- 010.
DsnoitairaVeeS
E292.692.992.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
∝
°0°5°8
X580.390.001.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS9148yF-82
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP
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