Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-93
Advance Information
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9148-93 Rev - 1/22/99
Pin Configuration
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, ±0.6%
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-93 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-93
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0).
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Page 2
2
ICS9148-93
Advance Information
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
11DDVRWPV3.3lanimon,ylppusrewopLATX,)2:0(feR
2
0FERTUO.kcolcecnereferzHM813.41
5.2_#3.3UPC
2,1
NI
V3.3=WOL,UPCV5.2=hgiH.V5.2roV3.3si2LDDVrehtehwsetacidnI
UPC
1
tupnidehctaL.
2
,72,22,61,9,3
54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
41,62DDVRWPV3.3lanimon,)5:0(KLCICPdnaF_KLCICProfylppuS
7
F_KLCICPTUO
wekssn4-1htiwsKLCUPChtiwsuonorhcnyS.tuptuokcolcICPgninnureerF
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ehtsenimretedsnipSFrehtohtiwgnolA.tupnIdehctaL.niptcelesycneuqerF
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.tupnidehctalLES_DSehtybdetcelessiycneuqerF.tuptuokcolcMARDS
ycneuqerfUPC=ycneuqerfMARDSsesuacnorewopta1=LES_DS
ycneuqerfPGA=ycneuqerfMARDSsesuacnorewopta0=LES_DS
81
#POTS_ICP
1
NI
nehw,level0cigoltaskcolc)5:0(KLCICPstlahtupnisuonorhcnysasihT
)0=EDOM,edomelibomnI(woltupni
01MARDSTUO
.tupnidehctalLES_DSehtybdetcelessiycneuqerF.tuptuokcolcMARDS
ycneuqnerfUPC=ycneuqerfMARDSsesuacnorewopta1=LES_DS
ycneuqerfPGA=ycneuqerfMARDSsesuacnorewopta0=LES_DS
,13,92,82,12,02
83,73,53,43,23
)9:0(MARDSTUO
.tupnidehctalLES_DSehtybdetcelessiycneuqerF.stuptuokcolcMARDS
ycneuqerfUPC=ycneuqerfMARDSsesuacnorewopta1=LES_DS
ycneuqerfPGA=seicneuqerfMARDSsesuacnorewopta0=LES_DS
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,skcolczHM84,42dnaeroCUPC,)11:0(MARDSrofylppuS
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Page 3
3
ICS9148-93
Advance Information
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, V
DDL
= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
5.2_#3.3UPC
leveltupnI
)ataDdehctaL(
rofdetceleSreffuB
:tanoitarepo
1DDVV5.2
0DDVV3.3
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
52niP,EDOM
)tupnIdehctaL(
71niP81niP
0
#POTS_UPC
)TUPNI(
#POTS_ICP
)TUPNI(
1
11MARDS
)TUPTUO(
01MARDS
)TUPTUO(
#POTS_UPC#POTS_ICP
,PGA
KLCUPC
stuptuO
KLCICP
)5:0(
,F_KLCICP
,FER
zHM84/42
MARDSdna
latsyrC
CSO
OCV
01 woLdeppotSgninnuRgninnuRgninnuRgninnuR
11 gninnuRgninnuRgninnuRgninnuRgninnuR
10 gninnuRwoLdeppotSgninnuRgninnuRgninnuR
2SF1SF0SF
)zHM(UPC
)zHM(MARDS
)zHM(ICP)zHM(PGA
000 00.0900.0300.06
001 28.6614.3328.66
010 94.8652.4394.86
011 00.575.7300.57
100 00.5700.0300.06
101 13.3823.3346.66
110 52.5957.1305.36
111 00.00133.3366.66
Page 4
4
ICS9148-93
Advance Information
Byte0: Functionality and Frequency Select Register
(default = 0)
Serial Configuration Command Bitmap
General I
2
C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
Send the address D2
(H)
.
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3
(H)
.
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
rotareneGkcolC
)stib7(sserddA
KCA
stib8+
ymmud
edocdnammoc
KCA
stib8+
etyBymmud
tnuoc
KCA
etyBataD
1
KCA
etyBataD
N
KCA
#W/R&)0:6(A
2D)H(
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KCA
etyB
tnuoC
KCA
etyBataD
1
KCA
etyBataD
N
#W/R&)0:6(A
3D)H(
I2C is a trademark of Philips Corporation
Note 1. Default at Power-up will be for latched logic inputs,
as defined by Bit 3.
tiBnoitpircseDDWP
7tiB
noitaludoMmurtcepSdaerpS%52.0±-0
noitaludoMmurtcepSdaerpS%6.0±-1
0
tiB
4:6
)4:6(tiBUPC
MARDS
)zHM(
ICP
)zHM(
PGA
)zHM(
XXX
1etoN
00000.0900.0300.06
10028.6614.3328.66
01094.8652.4394.86
11000.5705.7300.57
00100.5700.0300.06
10113.3823.3346.66
01152.5957.1305.36
11100.00133.3366.66
3tiB
,tceleserawdrahybdetcelessiycneuqerF-0
ylnosnip)2:0(SF
IybseicneuqerftceleS-1
2
C
0
daerpSretneC-0
daerpSnwoD-1
0
1tiB
noitarepolamroN-0
delbanEmurtcepSdaerpS-1
0
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Page 5
5
ICS9148-93
Advance Information
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 )tcanI/tcA(3KLCUPC
2tiB141 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(0KLCUPC
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB71 )tcanI/tcA(F_KLCICP
5tiB511 )tcanI/tcA(0PGA
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
tiB#niPDWPnoitpircseD
7tiB821 )tcanI/tcA(7MARDS
6tiB921 )tcanI/tcA(6MARDS
5tiB131 )tcanI/tcA(5MARDS
4tiB231 )tcanI/tcA(4MARDS
3tiB431 )tcanI/tcA(3MARDS
2tiB531 )tcanI/tcA(2MARDS
1tiB731 )tcanI/tcA(1MARDS
0tiB831 )tcanI/tcA(0MARDS
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB711
)tcanI/tcA(11MARDS
)ylnOedoMpotkseD(
2tiB811
)tcanI/tcA(01MARDS
)ylnOedoMpotkseD(
1tiB021 )tcanI/tcA(9MARDS
0tiB121 )tcanI/tcA(8MARDS
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 )tcanI/tcA(1PGA
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
Page 6
6
ICS9148-93
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-93. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-93.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Page 7
7
ICS9148-93
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-93. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-93 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Page 8
8
ICS9148-93
Advance Information
Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-93 serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Shared Pin Operation Input/Output Pins
Fig. 1
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Page 9
9
ICS9148-93
Advance Information
Fig. 2a
Fig. 2b
Page 10
10
ICS9148-93
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Elect rical Characteri st ics - Input /Supply/Com m on Output Param et ers
TA = 0 - 70C; Supply Voltage VDD = V
DDL
= 3 .3 V +/-5% (unless ot he rwise stated)
PARA METER SYMBOL COND ITI ON S MIN TY P MAX UNI TS
Input High Vo lt a ge V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
0.15mA
Input Low Cur rent I
IL1
VIN = 0 V; Inputs with no pull-up resis tors -5 2. 0 mA
Input Low Cur rent I
IL2
VIN = 0 V; Inputs with pull-up resis tors -200 -100 mA
Oper ating I
DD3.3O PCL
= 0 pF; 66.8 MHz 100 160 mA
Supply C urrent
Input frequency F
i
VDD = 3.3 V; 14.318 MH z
Input C a pa cit anc e
1
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 36 45 pF
Transition Time
1
T
trans
To 1st crossing of target F req. 2 ms
Se tt ling T ime
1
T
s
From 1st c rossing to 1% target Freq. ms
Clk S ta bilization
1
T
STAB
From VDD = 3.3 V to 1% ta rget Freq. 2 ms
Skew
1
T
CPU-SDRAM1VT
= 1.5 V; S DRAM L e a ds -500 200 500 ps
T
CPU-PCI1VT
= 1.5 V; CPU Le ads
12.84 ns
1
G ua ranteed by design, not 100% tested in production.
Electric al Characterist ics - Input/Supply/Common Output Param eters
TA = 0 - 70C; S uppl y Voltage VDD = 3.3 V +/-5% , V
DDL
= 2.5 V + /-5% (unl e s s otherwise s t a te d)
PARAMETER SYMBOL COND ITI ON S MIN TYP MAX UNITS
Operating I
D D2.5OP
CL = 0 pF; 66.8 MHz 10 20 mA
Suppl y Cu rrent
T
CPU-SDRAM2VT
= 1.5 V; VTL = 1 .25 V; SDRAM Leads -50 0 200 500 ps
T
CPU-PCI2VT
= 1.5 V; VTL = 1.25 V; CPU Leads
12.74 ns
1
G ua ranteed by d e sign, not 100% tested i n production.
Skew
1
Page 11
11
ICS9148-93
Advance Information
Ele ctri cal Characteri stics - C PU
TA = 0 - 70C; VDD = V
DDL
= 3.3 V + /-5%; CL = 10 - 20 pF (unless otherwise stated)
PARA METER S Y MBOL COND ITI ON S MIN TYP MAX UNITS
Output High Voltage V
OH2AIOH
= -28 mA 2.5 2.6 V
Output Low Voltage V
OL2AIOL
= 27 m A 0.35 0.4 V
O utpu t High Current I
OH2A
VOH = 2.0 V -29 -23 mA
O utput Low Curre nt I
OL2A
VOL = 0.8 V 33 37 mA
Rise Time t
r2A
1
VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns
Fall Time t
f2A
1
VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns
Duty Cycle d
t2A
1
VT = 1.5 V 45 50 55 %
Skew t
sk2A
1
VT = 1.5 V 50 250 ps
Jitter, One Sigma t
j1s2A
1
VT = 1.5 V 65 150 ps
Jitter, Absolute
t
jabs2A
1
VT = 1.5 V
-25 0 165 250 ps
1
G ua ranteed by design, no t 100 % t ested in production.
Ele ct rical Ch aracter i stics - CP U
TA = 0 - 70C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 10 - 20 pF (unless otherw ise state d)
PARA METER SY MBOL CONDITIONS MIN TYP MAX UNITS
Ou tput High Volt a ge VOH2B I
OH
= -8 mA 2 2.2 V
Output Low Voltage VOL2B I
OL
= 12 m A 0.3 0.4 V
Output High Current IOH2B V
OH
= 1.7 V -20 -16 mA
O utput Low Current IO L2B V
OL
= 0.7 V 19 26 mA
Rise Time
tr2B
1
VOL = 0.4 V, VOH = 2.0 V 1.5 1.8 ns
Fall Time
tf2B
1
VOH = 2.0 V, VOL = 0.4 V 1.6 1.8 ns
Duty Cycle
dt2B
1
VT = 1.25 V 404755%
Skew
tsk2B
1
VT = 1.25 V 60 250 ps
Jitter, Single Ed ge
Displacement
2
tjsed2B
1
VT = 1.25 V 200 250 ps
Jitter, One Sigma
tj1s2B
1
VT = 1.25 V 65 150 ps
Jitter, Absolute
tjabs2B
1
VT = 1.25 V -300 160 300 ps
1
G ua ranteed b y de sign, not 100% t e sted in production.
2
Edge displac e ment of a period re la tive to a 10- c loc k-cycle rolling average period.
Page 12
12
ICS9148-93
Advance Information
Ele ctri cal Characteri stics - P CI
TA = 0 - 70C; VDD = V
DDL
= 3.3 V + /-5%; CL = 30 pF (unless otherwise state d)
PARA METER SYMBOL CON DI TIO NS MIN TYP MAX UNITS
Ou t put High Voltage V
OH1IOH
= -28 mA 2.4 3 V
Output Low Voltage V
OL1IOL
= 23 mA 0.2 0.4 V
O ut put High Current I
OH1
VOH = 2 .0 V -60 - 40 mA
Output Low Current I
OL1
VOL = 0.8 V 41 50 mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns
Duty Cycle d
t1
1
VT = 1.5 V 45 51 55 %
Skew t
sk1
1
VT = 1.5 V 130 250 ps
Jitter, One Sigma
1
t
j1s1a
VT = 1.5 V, synchronous 40 1 50 ps
t
j1s1b
VT = 1.5 V, asynch ronous 200 250 ps
Jitter, Absolute
1
tab
s1aVT
= 1.5 V, synchronous - 250 135 250 ps
t
jabs1bVT
= 1.5 V, asynch ronous
-650 500 650 ps
1
G ua ranteed by de sign, not 100 % t ested in production.
Ele ctrical Characteristics - SDR A M
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 30 p F
PARA METER SYMBOL COND ITI ON S MIN TYP MAX UNITS
O utput High Vol ta ge V
OH1IOH
= -28 mA 2.4 3 V
Output Low Voltage V
OL1IOL
= 23 mA 0.2 0.4 V
Ou tput High Current I
OH1
VOH = 2 .0 V -60 - 40 mA
Output Low Current I
OL1
VOL = 0.8 V 41 50 mA
Rise Time
1
T
r1
VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns
Fall T im e
1
T
f1
VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns
Duty Cycle
1
D
t1
VT = 1.5 V 45 50 55 %
Skew
1
T
sk1
VT = 1.5 V 200 500 ps
Jitter, One Sigma
1
T
j1s1
VT = 1.5 V 50 150 ps
Jitter, Absolute
1
T
jabs1
VT = 1.5 V (with synchronous PCI) - 25 0 +250 ps
Jitter, Absolute
1
T
jabs1
VT = 1.5 V (with a synchronous PCI)
-400 400 ps
1
G ua ranteed by d e sign, not 100% tested i n production.
Page 13
13
ICS9148-93
Advance Information
Ele ctrical Character istics - AGP
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 30 p F (unless otherwise state d)
PARA METER SYMBOL CONDI TIO N S MIN TYP MAX UNITS
O utput High Volta ge V
OH1IOH
= -28 mA 2. 4 3 V
Output Low Voltage V
OL1
IOL = 23 mA 0.2 0.4 V
Ou t put High Current I
OH1
VOH = 2 .0 V -60 - 40 mA
Output Low Current I
OL1
VOL = 0.8 V 41 50 mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 1 2 ns
Duty Cycle d
t1
1
VT = 1.4 V 45 49 55 %
Skew t
sk1
1
VT = 1.5 V 130 250 ps
Jitter, One Sigma
1
t
j
1s1
VT = 1.5 V 2 3 %
Jitter, Absolute
1
t
abs1a
VT = 1.5 V, synchronous -5 2.5 5 %
t
jabs1b
VT = 1.5 V, asynchronous
-6 4.5 6 %
1
G ua ranteed by d e sign, not 100% tested i n production.
Ele ctri cal Characteri stics - 24M H z, 48MHz, R EF0
TA = 0 - 70C; VDD = V
DDL
= 3.3 V + /-5%; CL = 10 -20 pF (unless otherwise stated)
PARA METER SYMBOL CONDITI O NS MIN TYP MAX UNITS
Ou t put High V ol t age V
OH5IOH
= -16 mA 2.4 2.6 V
Output Low Voltage V
OL5IOL
= 9 mA 0.3 0.4 V
Output High Current I
OH5
VOH = 2 .0 V -32 -22 mA
Output Low Current I
OL5
VOL = 0.8 V 16 25 mA
Rise Time t
r5
1
VOL = 0.4 V, VOH = 2.4 V 2 4 ns
Fall Time t
f5
1
VOH = 2.4 V, VOL = 0.4 V 1.9 4 ns
Duty Cycle d
t5
1
VT = 1.5 V 45 54 57 %
Jitter , One Sigm a t
j1s5
1
VT = 1.5 V 1 3 %
Jitter, Abs olute
t
jabs5
1
VT = 1.5 V
-5 - 5 %
1
G ua ranteed by design, no t 100 % t ested in production.
Page 14
14
ICS9148-93
Advance Information
SSOP Package
Ordering Information
ICS9148F-37
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX F - PPP
LOBMYS SNOISNEMIDNOMMOC SNOITAIRAV D N
.NIM.MON.XAM.NIM.MON.XAM
A590.101.011.CA026.526.036.84
1A800.210.610.
2A880.090.290.
B800.010.5310.
C500.- 010.
DsnoitairaVeeS
E292.692.992.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
∝
°0°5°8
X580.390.001.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
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