Datasheet AV9148F-08, ICS9148F-08 Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9148-08

Block Diagram

Frequency Generator & Integrated Buffers for PENTIUM/Pro

TM

9148-08 Rev A 092297P

Pin Configuration

 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
 2.5V or 3.3V outputs; CPU, IOAPIC
 20 ohm CPU clock output impedance
 20 ohm PCI clock output impedance
 Skew from CPU (earlier) to PCI clock - 1 to 4 ns,

center 2.6 ns.
 No external load cap for CL=18pF crystals
 ±250 ps CPU, PCI clock skew
 400ps (cycle to cycle) CPU jitter
 Smooth frequency switch , with selections from 50 to 83.3

MHz CPU.
I2C interface for programming
 2ms power up clock stable time
 Clock duty cycle 45-55%.
 48 pin 300 mil SSOP package
 3.3V operation, 5V tolerant input.

48-Pin SSOP

Power Groups

VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)

* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs

The ICS9148-08 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.

Features include four CPU, seven PCI and Twelve SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Plus the IOAPIC output powered by
VDDL1. One 48 MHz for USB, and one 24 MHz clock for
Super IO. Spread Spectrum built in ±1.5% modulation to
reduce the EMI. Serial programming I2C interface allows
changing functions, stop clock programing and Frequency
selection. Rise time adjustment for VDD at 3.3V or 2.5V CPU.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PCI, CPU, DIMM). The
add on card might have a pull up or pull down.

High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into
20pF loads while maintaining 50±5% duty cycle. The REF
and 24 and 48 MHz clock outputs typically provide better
than 0.5V/ns slew rates.

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

2

ICS9148-08

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic high to VDD or logic low to GND.

PIN NUMBER PIN NAME TYPE DESCRIPTION

1 VDD1 PW R Ref (0:1), XTAL power supply, nominal 3.3V
2

REF0 OUT 14.318 MHz reference clock.
CPU3.3#_2.5

1,2

IN

Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU,
LOW=3.3V CPU

1

. Latched input

2

3,9,16,22,27,

33,39,45

GND PWR Ground

4X1 IN

Crystal input, has internal load cap (33pF) and feedba ck
resistor from X2

5X2 OUT

Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)

6,14 VDD2 PW R Supply for PCIC LK_F and PCICLK (0:5), nominal 3.3V

7

PCICLK_F

OUT

Free running PCI clock

FS1

1, 2

IN

Frequency select pin. Latched Input

8

PCICLK0

OUT

PCI clock output.

FS2

1, 2

IN

Frequency select pin. Latched Input

10, 11, 12, 13

PCICLK(1:4)

OUT

PCI clock outputs.

15

PCICLK5

OUT

PCI clock output. (In desktop mode, MODE=1)

PCI_STOP#

1

IN

Halts PCICLK(0:5) clocks at logic 0 level, w hen input low (In
mobile mode, MODE=0)

17, 18, 20, 21,

28, 29, 3 1, 32,

34, 35,37,38

SDRAM (0:11)

OUT

SDRAM clock outputs.

19,30,36

VDD3

PWR

Supply for SDRAM (0:11), PLL core and 24,48MHz clocks,
nominal 3.3V

23

SDATA

IN

Data input for I2C serial input.

24

SCLK

IN

Clock input of I2C input

25

24MHz

OUT

24MHz output clock

MODE

1, 2

IN

Pin 15, pin 46 function select pin, 1= Desktop Mode, 0=Mobile M ode.
Latched Input.

26

48MHz

OUT

48MHz output clock

FS0

1, 2

IN

Frequency select pin. Latched Input

40, 41, 43, 44

CPUCLK(0:3)

OUT

CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low

42

VDDL2

PWR

Supply for CPU (0:3), either 2.5V or 3.3V nominal

46

REF1 OUT

14.318 MHz reference clock , (in Desktop Mode, MODE =1) This
REF output is the STRONGER buffer for ISA BUS loads.

CPU_STOP#

1

IN

Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in
Mobile Mode, MODE= 0)

47 IOAPIC OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1.
48 VD DL 1 P W R Supply for IOAPIC, either 2.5 or 3.3V nominal

3

ICS9148-08

Functionality

VDD1,2,3 = 3.3V±5%, V

DDL

1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C

Crystal (X1, X2) = 14.31818MHz

CPU3.3#_2.5

Input level

(Latch ed Data )

Buffer Selected for

operation at:

12.5V VDD

03.3V VDD

CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.

Power Management Functionality

FS2 FS1 FS0

CPU,

SDRAM(MHz)

PCICLK

(MHz)

REF, IOAPIC

(MHz)
0 0 0 50.0 25.0 (1/2 CPU) 14.318
0 0 1 75.0 30 (CPU/2.5) 14.318
0 1 0 83.3 33.3 14.318
0 1 1 68.5 34.25 (1/2 CPU) 14.318

1 0 0 55.0 27.5 (1/2 CPU) 14.318
1 0 1 75.0 37.5 (1/2 CPU) 14.318

1 1 0 60.0 30.0 (1/2 CPU) 14.318
1 1 1 66.8 33.4 (1/2 CPU) 14.318

Mode Pin - Power Management Input Control

MODE, Pin 25
(Latched Input)

Pin 46 Pin 15

0

CPU_STOP#

(INPUT)

PCI_STOP#

(INPUT)

1

REF1

(OUTPUT)

PCICLK5

(OUTPUT)

CPU_STOP# PCI_STOP#

CPUCLK

Outputs

PCICLK

(0:5)

PCICLK_F,

REF,

24/48MHz

and SDRAM

Crystal

OSC

VCO

0 1 Stopp ed Low Running Running Running R unning
1 1 Running Running Running Running Running
1 0 Running Stopped Low Running Running Running

4

ICS9148-08

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

General I

2

C serial interface information

I2C is a trademark of Philips Corporation

A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with

an acknowledge bit between each byte.

B. The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.

C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

D. The input is operating at 3.3V logic levels.

E. The data byte format is 8 bit bytes.

F. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.

G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

to a 1 (Enabled output state)

Then Byte 0, 1, 2, etc in
sequence until STOP.

Byte 0, 1, 2, etc in sequence until STOP.

Clock Generator
Address (7 bits)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

D2

(H)

Clock Generator

Address (7 bits)

ACK

Byte 0 ACK By te 1 ACK

A(6:0) & R/W#

D3

(H)

Note 1. Default at Power-up will be for

latched logic inputs to define
frequency. Bits 4, 5, 6 are default to
000, and if bit 3 is written to a 1 to
use Bits 6:4, then these should be
defined to desired frequency at same
write cycle.

Note: PWD = Power-Up Default

Bit Description PWD

Bit 7

0 - ±1.5% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation

0

Bit 6:4

Bit6 Bit5 Bit4

111
110
101
100
011
010
001
000

CPU clo ck

66.8

60.0

75.0

55.0

68.5

83.3

75.0

50.0

PCI

33.4(1/2 CPU)

30.0 (1/2 CPU)

37.5 (1/2 CPU)

27.5 (1/2 CPU)

34.5 (1/2 CPU)

33.3

30.0 (CPU/2.5)

25.0 (1/2 CPU)

Note1

Bit 3

0 - Frequency is se lected by hardware s elect, Latched I nputs
1 - Frequency is selected by Bit 6:4 (above)

0

0 - Spread Spectr um center spread t ype.
1 - Spread Spectrum down spread type.

0

Bit 1

0 - Normal
1 - Spread Spectrum Enabled

0

Bit 0

0 - Running
1- Tristate all outputs

0

5

ICS9148-08

Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. PCICLK5 only in Desktop Mode

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Bit Pin # PWD Description

Bit 7 - 1 (Reserved)
Bit 6 - 1 (Reserved)
Bit 5 - 1 (Reserved)
Bit 4 - 1 (Reserved)
Bit 3 40 1 CPUCLK3 (Act/Inact)
Bit 2 41 1 CPUCLK2 (Act/Inact)
Bit 1 43 1 CPUCLK1 (Act/Inact)
Bit 0 44 1 CPUCLK0 (Act/Inact)

Bit Pin # PWD Description

Bit 7 - 1 (Reserved)
Bit 6 7 1 PCICLK_F (Act/Inact)

Bit 5 15 1

PCICLK5 (Act/Inact)

(Desktop only )
Bit 4 14 1 PCICLK4 (Act/Inact)
Bit 3 12 1 PCICLK3 (Act/Inact)
Bit 2 11 1 PCICLK2 (Act/Inact)
Bit 1 10 1 PCICLK1 (Act/Inact)
Bit 0 8 1 PCICLK0 (Act/Inact)

Bit Pin # PWD Description

Bit 7 28 1 SDRAM7 (Act/Inact)
Bit 6 29 1 SDRAM6 (Act/Inact)
Bit 5 31 1 SDRAM5 (Act/Inact)
Bit 4 32 1 SDRAM4 (Act/Inact)
Bit 3 34 1 SDRAM3 (Act/Inact)
Bit 2 35 1 SDRAM2 (Act/Inact)
Bit 1 37 1 SDRAM1 (Act/Inact)
Bit 0 38 1 SDRAM0 (Act/Inact)

Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching. These outputs are designed to be
configured at power-on and are not expected to be
configured during the normal modes of operation.

Bit Pin # PWD Descr iption

Bit 7 - 1 (Reserved)
Bit 6 - 1 (Reserved)
Bit 5 - 1 (Reserved)
Bit 4 - 1 (Reserved)
Bit 3 17 1 SDRAM11 (Act/Inact)
Bit 2 18 1 SDRAM10 (Act/Inact)
Bit 1 20 1 SDRAM9 (Act/Inact)
Bit 0 21 1 SDRAM8 (Act/Inact)

Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from
switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the
normal modes of operation.

2. REF1 only in Desktop Mode

Bit Pin # PWD Descr iption

Bit 7 - 1 (Reserved)
Bit 6 - 1 (Reserved)
Bit 5 - 1 (Reserved)
Bit 4 47 1 IOAPIC0 (Act/Inact)
Bit 3 - 1 (Reserved)
Bit 2 - 1 (Reserved)
Bit 1 46 1 REF1 (Act/Inact )
Bit 0 2 1 REF0 (Act/Inact)

Bit Pin # PWD Description

Bit 7 - 1 (Reserv ed)
Bit 6 - 1 (Reserv ed)
Bit 5 - 1 (Reserv ed)
Bit 4 - 1 (Reserv ed)
Bit 3 - 1 (Reserv ed)
Bit 2 - 1 (Reserv ed)
Bit 1 - 1 (Reserv ed)
Bit 0 - 1 (Reserv ed)

Note: PWD = Power-Up Default

Byte 6: Optional Register For Possible Future Requirements

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.

6

ICS9148-08

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS9148-08. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU
clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS9148-08.

3. All other clocks continue to run undisturbed. (including SDRAM outputs).

7

ICS9148-08

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.

3. All other clocks continue to run undisturbed.

4. CPU_STOP# is shown in a high (true) state.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9148-08. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-08 internally. The minimum that the PCICLK (0:5) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock
off latency is one PCICLK clock.

8

ICS9148-08

Pins 2, 7, 8, 25 and 26 on the ICS9148-08 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.

To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic

1) power supply or the GND (logic 0) voltage potential. A
10 Kilohm(10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load
on the output clock during the subsequent operating
period.

Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the devices internal logic. Figs. 2a and b provide
a single resistor loading option where either solder spot tabs

Shared Pin Operation ­Input/Output Pins

Fig. 1

or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as possible,
as it passes through the programming resistor pad(s).

9

ICS9148-08

Fig. 2a

Fig. 2b

10

ICS9148-08

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.

Electrical Characteristics - I nput/S upply/Com m on Out put Parameters

TA = 0 - 70C; Supply Voltage VDD = V

DDL

= 3.3 V +/-5% (unless other wise stated)

PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS

Input H igh Voltage V

IH

2V

DD

+0.3 V

Input L ow Voltage V

IL

VSS-0.3 0.8 V

Input High Current I

IH

VIN = V

DD

0.1 5 µA

Input L ow C urrent I

IL1

VIN = 0 V ; Inputs with no pul l- up r esi stors -5 2 µA

Input L ow C urrent I

IL2

VIN = 0 V ; Inputs with pull-up resistors -20 0 -1 00 µA

Oper ating I

DD3.3OPCL

= 0 pF; Select @ 66MHz 100 160 mA

Supply C urrent

Inp ut Fr eque nc y F

i

VDD = 3.3 V 12 14.318 16 MHz

Input Capaci tance

1

C

IN

L ogi c I nputs 5 pF

C

INX

X1 & X2 pins 27 36 45 pF

Transition Time

1

T

trans

To 1 st crossing of target Freq. 2 ms

Clk Stabilization

1

T

STAB

From VDD = 3.3 V to 1% target Freq. 2 ms

Skew

1

t

CPU-SDRAM1

VT = 1.5 V 500 ps

t

CPU-P CI1VT

= 1.5 V

12.64ns

1

Guara nte e d by de si g n, no t 100% te sted in production.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5% (unless otherwise stated)

PARAMETER

SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Supply

Current

I

DD2.5OP

CL = 0 pF; Select @ 66.8 MHz 8 20 mA

Skew

1

t

CPU - SD RAM2VT

= 1.5 V; VTL = 1.25 V 800 ps

t

CPU -P CI2

VT = 1.5 V; VTL = 1.25 V

14ps

1

Guaranteed by design, not 100% tested in pr oduction.

11

ICS9148-08

Ele ctrical Charact eristics - CP U

TA = 0 - 70C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Imp eda nc e

1

R

DSP2B

VO = VDD*(0.5) 13.5 45 Ohm

O utput Imp eda nc e

1

R

DSN2B

VO = VDD*(0.5) 13.5 45 Ohm

O utput High Vol ta ge V

OH2BIOH

= -8 mA 2 2.2 V

Output Low Voltage V

OL2BIOL

= 12 mA 0.3 0.4 V

Ou tput High Curr e nt I

OH2B

VOH = 1.7 V -20 -16 m A

Output Low Current I

OL2B

VOL = 0.7 V 19 26 mA

Rise Time

1

t

r2B

VOL = 0.4 V, VOH = 2.0 V 2.2 2.5 ns

Fall Time

1

t

f2B

VOH = 2.0 V , VOL = 0.4 V 1.1 1.6 ns

Duty Cycle

1

d

t2B

VT = 1.25 V 45 55 %

Skew

1

t

sk2B

VT = 1.25 V 250 ps

Jitter , Cycle-to- c ycle

1

t

jcyc-cyc2BVT

= 1.25 V 200 300 ps

Jitter , One Sigma

1

t

j1s2B

VT = 1.25 V 50 150 ps

Jitter, Absolute

1

t

jabs2B

VT = 1.25 V

-250 +250 ps

1

Guarant eed by design, no t 100% te sted in production.

Ele ctrical Charact eristics - PC I

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Imp eda nc e

1

R

DSP1

VO = VDD*(0.5) 10 24 Ohm

O utput Imp eda nc e

1

R

DSN1

VO = VDD*(0.5) 10 24 Ohm

O utput High Vol ta ge V

OH1

IOH = -28 mA 2.4 3 V

Output Low Voltage V

OL1

IOL = 23 mA 0.2 0.4 V

Ou t put High Curr ent I

OH1

VOH = 2.0 V -60 -40 m A

Output Low Current I

OL1

VOL = 0.8 V 41 50 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.6 2 ns

Fall Time

1

t

f1

VOH = 2.4 V , VOL = 0.4 V 1.2 2 ns

Duty Cycle

1

d

t1

VT = 1.5 V 45 51 55 %

Skew

1

t

sk1

VT = 1.5 V 100 250 ps

Jitter , One Sigma

1

t

j1s1

VT = 1.5 V 100 300 ps

Jitter , Absolute

1

t

jabs1

VT = 1.5 V

-500 500 ps

1

Guarant eed by design, no t 100% te sted in production.

12

ICS9148-08

Ele ctrical Charact eristics - SD RAM

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Imp eda nc e

1

R

DSP1

VO = VDD*(0.5) 10 24

Ω

O utput Imp eda nc e

1

R

DSN1

VO = VDD*(0.5) 10 24

Ω

O utput High Vol ta ge V

OH1

IOH = -28 mA 2.4 3 V

Output Low Voltage V

OL1

IOL = 23 mA 0.2 0.4 V

Ou t put High Curr ent I

OH1

VOH = 2.0 V -60 -40 m A

Output Low Current I

OL1

VOL = 0.8 V 41 50 mA

Rise Time

1

T

r1

VOL = 0.4 V, VOH = 2.4 V 1.6 2 ns

Fall Time

1

T

f1

VOH = 2.4 V , VOL = 0.4 V 1.2 2 ns

Duty Cycle

1

D

t1

VT = 1.5 V 45 52 55 %

Skew

1

T

sk1

VT = 1.5 V 150 250 ps

Jitter , One Sigma

1

T

j1s1

VT = 1.5 V 50 150 ps

Jitter , Absolute

1

T

jabs1

VT = 1.5 V

-250 +250 ps

1

Guarant eed by design, no t 100% te sted in production.

Electrical Characteristics - IOAPIC

TA = 0 - 70C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Impe da nc e

1

R

DSP4B

VO = VDD*(0.5) 13.5 45 Ohm

O utput Impe da nc e

1

R

DSN4B

VO = VDD*(0.5) 13.5 45 Ohm

O utput High Volt ag e V

OH4BIOH

= -8 mA 2 2.2 V

Output Low V oltage V

OL4BIOL

= 12 mA 0.3 0.4 V

Ou tput High Current I

OH4B

VOH = 1.7 V -20 -16 m A

Output Low Current I

OL4B

VOL = 0.7 V 19 26 mA

Rise Time

1

T

r4B

VOL = 0.4 V, VOH = 2.0 V 1.4 1.7 ns

Fall Time

1

T

f4B

VOH = 2.0 V , VOL = 0.4 V 1.3 1.6 ns

Duty Cycle

1

D

t4B

VT = 1.25 V 50 60 %

Jitter , One Sigma

1

T

j1s4B

VT = 1.25 V 1 3 %

Jitter , Absolute

1

T

jabs4B

VT = 1.25 V

-5 5 %

1

Guarant e e d by de sign, no t 100% tested in production.

13

ICS9148-08

Electrical C haracteristics - 24,48MHz, REF(0:1)

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Impe da nc e

1

R

DSP5

VO = VDD*(0.5) 20 60 Ohm

O utput Impe da nc e

1

R

DSN5

VO = VDD*(0.5) 20 60 Ohm

O utput High Volt age V

OH5

IOH = -16 mA 2.4 2.6 V

Output Low Voltage V

OL5

IOL = 9 mA 0.3 0.4 V

Ou tput High Curre nt I

OH5

VOH = 2.0 V -32 -22 m A

Output Low Current I

OL5

VOL = 0.8 V 16 25 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 1.7 4 ns

Fall Time

1

t

f5

VOH = 2.4 V , VOL = 0.4 V 1.6 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 53 55 %

Jitter , One Sigma

1

t

j1s5

VT = 1.5 V 1 3 %

Jitter , Absolute

1

t

jabs5

VT = 1.5 V

38%

1

Guarant e e d by de sign, no t 100% tested in production.

14

ICS9148-08

SSOP Package

Ordering Information

ICS9148F-08

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX F - PPP

SYMBOL CO MMON DIMENSIONS VARIATIONS D N

MIN. NOM. MAX. MIN. NOM. MAX.

A .095 .101 .110 AC .620 .625 .630 48
A1 .008 .012 .016
A2 .088 .090 .092

B .008 .010 .0135

C.005- .010

D See Variations

E .292 .296 . 299

e0.025 BSC

H .400 .406 .410

h .010 .013 .016
L .024 .032 .040
N See Variations

∝

0° 5° 8°

X .085 .093 .100

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.