Page 1
Integrated
Circuit
Systems, Inc.
Pentium/ProTM System Clock Chip
General Description Features
The ICS9148-02 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four CPU, seven PCI and eight SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Additionally, the device meets the Pentium
power-up stabilization, which requires that CPU and PCI
clocks be stable within 2ms after power-up.
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP#
will stop PCICLK (0:5) clocks. CPU and IOAPIC output
buffer strength controlled by CPU 3.3_2.5# pin to match
VDDL voltage.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs typically
provide better than 0.5V/ns slew rates.
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O
Supports single or dual processor systems
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Two fixed outputs separately selectable as
24 or 48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP
Output enable register
for serial port control: 1 = enable
ICS9148-02
0 = disable
The ICS9148-02 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Block Diagram
Pentium is a trademark on Intel Corporation.
Pin Configuration
48-Pin SSOP
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C
Crystal (X1, X2) = 14.31818 MHz
LES
00603
16.663.33
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KLCICP
)zHM(
9148-02 Rev C 1/26/99
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Page 2
ICS9148-02
Pin Descriptions
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Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
2
Page 3
Power-On Conditions
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ICS9148-02
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Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced
are on the MODE pin as shown in the table below.
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3
Page 4
ICS9148-02
T echnical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from Ground
to this level. For the actual guaranteed high and low voltage
levels for the Clocks, please consult the DC parameter table
in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies
will have a voltage swing from Ground to this level. For the
actual Guaranteed high and low voltage levels of these
Clocks, please consult the DC parameter table in this Data
Sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. See the data tables for the value of this
capacitor.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor that is connected to ground. See the Data
Sheet for the value of this capacitor.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which
are in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks are controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing
of the SDRAMs output is controlled by the supply voltage
that is applied to VDD3 of the device, operates at 3.3 volts.
48/24MHzA, B
This is a fixed frequency Clock output that is typically used
to drive Super I/O devices. Outputs A and B are defined as
24 or 48MHz by I2C register (see table).
IOAPIC
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level
swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
REF(0:1)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and
X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING,
and will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the
current PCI specification. They run at 1/2 CPU frequency.
SELECT 66.6/60MHz#
This Input pin controls the frequency of the Clocks at the
CPU, PCICLK and SDRAM output pins. If a logic 1 value
is present on this pin, the 66.6 MHz Clock will be selected.
If a logic 0 is used, the 60MHz frequency will be selected.
MODE
This Input pin is used to select the Input function of the I/
O pins. An active Low will place the I/O pins in the Input
mode and enable those stop clock functions.
4
Page 5
T echnical Pin Function Descriptions
CPU 3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic 0 (ground) will indicate
2.5V operation and a logic 1 will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I2C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
ICS9148-02
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
5
Page 6
ICS9148-02
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
rotareneGkcolC
)stib7(sserddA
#W/R&)0:6(A
2D)H(
KCA
ymmudstib8+
edocdnammoc
KCA
ymmudstib8+
tnuocetyB
Then Byte 0, 1, 2, etc in
KCA
sequence until STOP.
B. The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
rotareneGkcolC
)stib7(sserddA
#W/R&)0:6(A
3D)H(
KCA0etyBKCA1etyBKCA
Byte 0, 1, 2, etc in sequence until STOP.
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)
Note: PWD = Power-Up Default
TIB#NIPNOITPIRCSEDDWP
7tiB- devreseR0
6tiB- noitarepolamronrof0ebtsuM0
5tiB-
4tiB
3tiB32zHM42=0,zHM84=1)tceleSycneuqerF(zHM42/841
2tiB22zHM42=0,zHM84=1)tceleSycneuqerF(zHM42/841
1tiB
1tiB
0tiB
-
1
1
0
0
)%6.0=1%8.1=0(
0tiB
etatS-irT-1
edomtseT-1
epytslortnoC,murtcepSdaerpSnI
)daerpsnwod=1,deretnec=0(
noitarepolamroN-0
(default on Bits 3, 2 = 1)
gnidaerpSslortnoC,murtcepSdaerpSnI
elbanEmurtcepSdaerpS-0
6
0
0
0
0
I2C is a trademark of
Philips Corporation
Page 7
Select Functions
ICS9148-02
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edomtseT2/KLCT
1
1
4/KLCT
1
2/KLCT
1
KLCT
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
Byte 1: CPU, 24/48 MHz Clock Register
TIB#NIPDWPNOITPIRCSED
7tiB321 )tcanI/tcA(zHM42/84
6tiB221 )tcanI/tcA(zHM42/84
5tiB-1 devreseR
4tiB-1 devreseR
3tiB831 )tcanI/tcA(3KLCUPC
2tiB931 )tcanI/tcA(2KLCUPC
1tiB141 )tcanI/tcA(1KLCUPC
0tiB241 )tcanI/tcA(0KLCUPC
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 2: PCICLK Clock Register
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB81 )tcanI/tcA(F_KLCICP
5tiB611 )tcanI/tcA(5KLCICP
4tiB411 )tcanI/tcA(4KLCICP
3tiB311 )tcanI/tcA(3KLCICP
2tiB211 )tcanI/tcA(2KLCICP
1tiB111 )tcanI/tcA(1KLCICP
0tiB91 )tcanI/tcA(0KLCICP
Notes: 1 = Enabled; 0 = Disabled, outputs held low
zHM42
noitceleS
1
KLCT
1
4/KLCT
zHM84
noitceleS
1
2/KLCT
Byte 3: SDRAM Clock Register
TIB#NIPDWPNOITPIRCSED
7tiB621 )tcanI/tcA(7MARDS
6tiB721 )tcanI/tcA(6MARDS
5tiB921 )tcanI/tcA(5MARDS
4tiB031 )tcanI/tcA(4MARDS
3tiB231 )tcanI/tcA(3MARDS
2tiB331 )tcanI/tcA(2MARDS
1tiB531 )tcanI/tcA(1MARDS
0tiB631 )tcanI/tcA(0MARDS
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Byte 4: SDRAM Clock Register
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-1 devreseR
Notes: 1 = Enabled; 0 = Disabled, outputs held low
7
Page 8
ICS9148-02
Byte 5: Peripheral Clock Register
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB541 )tcanI/tcA(0CIPAOI
3tiB-1 devreseR
2tiB-1 devreseR
1tiB11 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Byte 6: Optional Register for Future
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-1 devreseR
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Power Management
Clock Enable Configuration
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,MARDS
#POTS_UPC#POTS_ICP#NWD_RWPKLCUPCKLCICP
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011 woLzHM03/3.33gninnuRgninnuRgninnuR
10 1 zHM06/6.66woLgninnuRgninnuRgninnuR
111 zHM06/6.66zHM03/3.33gninnuRgninnuRgninnuR
,FER
,sCIPAOI
AzHM42/84
BzHM42/84
latsyrCsOCV
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9148-02 Power Management Requirements
ycnetaL
LANGISETATSLANGIS
#POTS_UPC)delbasiD(0
#POTS_ICP)delbasiD(0
#NWD_RWP)noitarepOlamroN(1
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
2
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8
Page 9
ICS9148-02
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9148-02. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is
100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than
4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-02.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-02. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-02 internally. The minimum that the PCICLK (0:5) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
(Drawing shown on next page.)
9
Page 10
ICS9148-02
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the ICS9148-02 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power
on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
10
Page 11
ICS9148-02
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Charact eristics - Input/Supply/ Com m on Output Paramete rs
TA = 0 - 70C; Supply Voltage VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
In put Low Vol t a ge V
Input High Current I
Input Low Current I
Input Low Current I
Operating I
IH
IL
IH
IL1
IL2
DD3.3OP
Su pply C urrent
Power Down I
DD3.3PDCL
Su pply C urrent
Input freque nc y F
Input Capacitance
Transi ti on Time
Settling Tim e
Clk Stabilization
Skew
1
Guar anteed by design, not 100% tested in produc t ion.
1
1
1
1
1
i
C
IN
C
INX
T
trans
T
s
T
STAB
T
CPU-SDRAM1VT
T
CPU-PCI1VT
= 3.3 V +/-5% (unless otherwise stated)
DDL
2V
+0.3 V
DD
VSS-0.3 0.8 V
VIN = V
DD
0.1 5
VIN = 0 V; Inputs with no pull-up resi stors -5 2.0
VIN = 0 V; Input s with pull -up resistors -200 -100
µ
µ
µ
CL = 0 pF; Select @ 66M 60 100 mA
= 0 pF; With input address to Vdd or GND 400 600
µ
VDD = 3.3 V; 14.318 MHz
Logic Inputs 5 pF
X1 & X2 pins 27 36 45 ps
To 1st crossi ng of tar get Freq. 3 ms
From 1st cr ossing to 1% target F req. ms
From VDD = 3.3 V to 1% target Freq. 3 ms
= 1.5 V 200 500 ps
= 1.5 V;
1.5 3.2 4.5 ns
A
A
A
A
Electri cal Characteristics - I nput/Suppl y/Common Out put Parameters
TA = 0 - 70C; Supply Vol ta ge VDD = 3.3 V +/-5%, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating I
DD2.5OPCL
= 0 pF; Select @ 66M 5 20 m A
Supply Current
Power Down I
DD2.5PDCL
= 0 pF; 0.21 1.0
Supply Current
1
Skew
1
Guar a nt eed by design, not 100% tested in produc tion.
T
CPU-SDRAM2VT
T
CPU-PCI2VT
= 1.5 V; VTL = 1.25 V; SDRAM Leads 150 500 ps
= 1.5 V; VTL = 1.25 V; CPU L eads
= 2.5 V +/-5% (unless otherwise stated)
DDL
11
A
µ
12.84ns
Page 12
ICS9148-02
Ele ctrical C haracterist ics - C PU
TA = 0 - 70C; VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Frequency F
O ut put Impedance R
O ut put Impedance R
O utput High Voltage V
Output Low Voltage V
Ou t put Hig h Current I
Output L ow Current I
Rise Time t
Fall Time t
Duty Cycle d
Skew t
Jitter t
1
Guar a nt eed by design, not 100% tested in produc t ion.
= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
DDL
O2
1
DSP2A
DSN2A
OH2AIOH
OL2A
OH2A
OL2A
r2A
f2A
t2A
sk2A
t
jcyc-cyc2A
j1s2A
t
jabs2A
VO = VDD*(0.5) 10 20
1
VO = VDD*(0.5) 10 20
= -28 mA 2.4 2.5 V
IOL = 27 mA 0.35 0.4 V
VOH = 2.0 V -52 -48 mA
VOL = 0.8 V 49.3 59 mA
1
VOL = 0.4 V, VOH = 2.4 V 1.1 2.85 ns
1
VOH = 2.4 V, VOL = 0.4 V 0.95 2.85 ns
1
VT = 1.5 V 45 51 55 %
1
VT = 1.5 V 80 250 ps
1
VT = 1.5 V 170 250 ps
1
VT = 1.5 V 60 150 ps
1
VT = 1.5 V
60 66 MHz
-250 100 +250 ps
Ω
Ω
Ele ctrical C haracterist ics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Freque nc y F
O ut put Impedanc e R
O ut put Impedanc e R
O utput High Voltage V
Output Low Voltage V
Ou t put Hig h Current I
Output L ow Current I
Rise Time t
Fall Time t
Duty Cycle d
Skew t
Jitter t
1
Guar a nt eed by design, not 100% tested in production.
O2
DSP2B
DSN2B
OH2BIOH
OL2B
OH2B
OL2B
r2B
f2B
t2B
sk2B
t
jcyc-cyc2B
j1s2B
t
jabs2B
= 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
DDL
60 66 MHz
1
VO = VDD*(0.5) 10 25
1
VO = VDD*(0.5) 10 25
= -13.0 mA 2 2.2 V
IOL = 14 mA 0.3 0.4 V
VOH = 1.7 V -20 -16 mA
VOL = 0.7 V 22 26 mA
1
VOL = 0.4 V, VOH = 2.0 V 1.42 1.6 ns
1
VOH = 2.0 V , VOL = 0.4 V 0.95 1.6 ns
1
VT = 1.25 V 45 49.5 55 ns
1
VT = 1.25 V 60 250 ps
1
VT = 1.25 V 150 250 ps
1
VT = 1.25 V 80 150 ps
1
VT = 1.25 V
-250 80 +250 ps
Ω
Ω
12
Page 13
ICS9148-02
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Freque nc y F
O ut put Impedanc e R
O ut put Impedanc e R
O utput High Voltage V
Output Low Voltage V
Ou t put Hig h Current I
Output L ow Current I
Rise Time t
Fall Time t
Duty Cycle d
Skew t
Jitter t
1
Guar a nt eed by design, not 100% tested in production.
= 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
DDL
O1
1
DSP1
DSN1
OH1
OL1
sk1
j1s1
t
jabs1
OH1
OL1
r1
f1
t1
VO = VDD*(0.5) 12 55
1
VO = VDD*(0.5) 12 55
IOH = -14.5 m A 2.4 2.7 V
IOL = 9.4 mA 0.2 0.4 V
VOH = 2.0 V -47 -22 mA
VOL = 0.8 V 17.1 47.5 mA
1
VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns
1
VOH = 2.4 V , VOL = 0.4 V 1.1 2 ns
1
VT = 1.5 V 45 51 55 %
1
VT = 1.5 V 100 500 ps
1
VT = 1.5 V 50 150 ps
1
VT = 1.5 V
30 - 33 MHz
-250 120 250 ps
Ω
Ω
Ele ctrical Characteristics - SDRAM
TA = 0 - 70C; VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Frequency F
O ut put Impedance R
O ut put Impedance R
Output High Voltage V
Output Low Voltage V
Ou tput High Current I
O ut put Low Current I
Rise Time T
Fall Time T
Duty Cycle D
Skew T
Jitter T
1
Guar anteed by design, not 100% tested in production.
= 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise state d)
DDL
O3
1
VO = VDD*(0.5) 10 24
1
VO = VDD*(0.5) 10 24
IOH = -24 mA 2.4 2 .5 V
IOL = 23 mA 0.35 0.4 V
VOH = 2.0 V -47 -40 mA
VOL = 0.8 V 41 47.5 mA
1
VOL = 0.4 V , VOH = 2.4 V 1.45 1.7 ns
1
VOH = 2.4 V, VOL = 0.4 V 1.2 1.5 ns
1
VT = 1.5 V 45 51 55 %
1
VT = 1.5 V 80 500 ps
1
VT = 1.5 V 40 150 ps
1
VT = 1.5 V
T
DSP3
DSN3
OH3
OL3
OH3
OL3
r3
f3
t3
sk3
j1s3
jabs3
60 66 MHz
-250 - 250 ps
Ω
Ω
13
Page 14
ICS9148-02
Ele ctri ca l Charact eristics - REF0
TA = 0 - 70C; VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Frequency F
O ut put Impedance R
O ut put Impedance R
O utput High Voltage V
Output Low Voltage V
Ou t put Hig h Current I
Output L ow Current I
Rise Time T
Fall Time T
Duty Cycle D
Jitter T
1
Guar enteed by de sign, not 100% tested in produc t ion.
= 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
DDL
O7
VO = VDD*(0.5) 10 24
VO = VDD*(0.5) 10 24
IOH = -24 mA 2.4 2.5 V
IOL = 23 mA 0.35 0.4 V
VOH = 2.0 V -47 -40 mA
VOL = 0.8 V 41 47.5 mA
1
VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns
1
VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns
1
VT = 1.5 V 45 52 45 %
1
VT = 1.5 V 150 350 ps
1
VT = 1.5 V
T
DSP7
DSN7
OH7
OL7
OH7
OL7
r7
f7
t7
j1s7
jabs7
14.318 MHz
-600 - 600 pS
Ω
Ω
Ele ctri ca l Charact eristics - 24M, 48M, REF1
TA = 0 - 70C; VDD = V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
O ut put Frequency F
O ut put Frequency F
O ut put Frequency F
O ut put Impedance R
O ut put Impedance R
O utput High Voltage V
Output Low Voltage V
Ou t put Hig h Current I
Output L ow Current I
Rise Time t
Fall Time t
Duty Cycle d
Jitter t
1
Guar enteed by de sign, not 100% tested in produc t ion.
= 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stat e d)
DDL
O24M
O48M
OREF
1
DSP5
DSN5
OH5
OL5
OH5
OL5
j1s5A
t
j1s5B
t
jabs5A
t
jabs5B
r5
f5
t5
VO = VDD*(0.5) 20 60
1
VO = VDD*(0.5) 20 60
IOH = -16 mA 2.4 2.5 V
IOL = 9 mA 0.2 0.4 V
VOH = 2.0 V -29 -22 mA
VOL = 0.8 V 16 25 mA
1
VOL = 0.4 V, VOH = 2.4 V 1.8 4 ns
1
VOH = 2.4 V, VOL = 0.4 V 1.7 4 ns
1
VT = 1.5 V 45 51 55 %
1
VT = 1.5 V; Fix ed Clocks 50 150 pS
1
VT = 1.5 V ; Ref Clocks 150 350
1
VT = 1.5 V; Fix ed Clocks -250 120 250
1
VT = 1.5 V; Ref Clocks
24 MHz
48 MHz
14.318 MHz
-600 - 600 pS
Ω
Ω
14
Page 15
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
ICS9148-02
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
15
Page 16
ICS9148-02
SSOP Package
LOBMYS SNOISNEMIDNOMMOC SNOITAIRAV D N
A590.101.011.CA026.526.036.84
1A800.210.610.DA027.527.037.65
2A880.090.290.
B800.010.5310.
C500.600.5800.
DsnoitairaVeeS
E292.692.992.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
∝
X580.390.001.
.NIM.MON.XAM.NIM.MON.XAM
°0°5°8
Ordering Information
ICS9148F-02
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
This table in inches
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
16
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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