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Integrated
Circuit
Systems, Inc.
ICS9147-06
Frequency Generator & Integrated Buffers for PENTIUM
General Description Features
The ICS9147-06 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro. Two different reference frequency multiplying
factors are externally selectable with smooth frequency
transitions. Glitch-free Stop clock control is provided for
CPU and BUS clocks. Complete chip low current mode is
achieved with the Power Down# pin.
High drive BUS outputs typically provide greater than 1 V/
ns slew rate into 30pF loads. CPU outputs typically provide
better than 1V/ns slew rate into 20pF loads while
maintaining
outputs typically provide better than 0.5V/ns slew rates.
Separate buffer supply pins VDDL allow for nominal 3.3V
voltage or reduced voltage swing (from 2.9 to 2.5V) for
CPU (1:4) and IOAPIC outputs.
50±
5% duty cycle. The REF and IOAPIC clock
Block Diagram
Generates five processor, eight bus, four 14.31818 MHz,
two 48 MHz clocks for USB support and one 24 MHz
clock.
CPU to BUS clock skew 1 to 4ns (CPU early)
Synchronous clocks skew matched to 250ps window on
CPU and 500ps window on BUS.
Selectable multiplying ratios
Glitch free stop clock controls CPUEN and BUSEN
3.0V 3.7V supply range, 2.5V to VDD supply range for
CPU (1:4) clocks and IOAPIC clock.
48-pin SSOP package
Pin Configuration
TM
9147- 06 RevA 5/29/97P
48-Pin SSOP
Pentium is a trademark of Intel Corporation
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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ICS9147-06
Functionality
PD# BUSEN CPUEN FS1 FS0
11100Tristate Tristate Tristate Tristate Tristate
11101603014.31818 24 48
1111066.633.314.31818 24 48
11111REF/2REF/4REFREF/4REF/2
1 1 0 X X LOW Running 14.31818 24 48
1 0 1 X X Running LOW 14.31818 24 48
0XXXXLOWLOWLOWLOWLOW
CPU (1:4)
CPUH
BUS
REF
IOAPIC
24
(MHz)
48
(MHz)
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1, 2, 47 REF1, REF2, REF3 OUT 14.318 MHz reference clo ck out puts.
3, 10, 18, 24, 30, 32,
37, 43, 44
4X1 IN
5 X2 OUT Crystal out put, has inter nal crystal load capacitor
8, 9, 11, 12, 13, 14,
16, 17
26, 27 FS (0:1) IN Select pin for enablin g CPU a nd BUS clock f requenci es.*
7, 15, 21, 25, 34, 48 VDD3 PWR Core and Buf fer output clock power supply.
22, 23 48M (1:2) OUT 48 MHz clock output
28 PD# I N
29 CP U EN IN
36 CPUH OU T 3.3 (VDD3 dependent) CPU c lock output
38, 39, 41, 42 CPU (1:4) OUT
6BUSEN IN
45 IOAPIC OUT
40, 46 VDDL P WR
33 24M OUT 24 MHz clock output
GND PWR Ground.
Crystal input, has internal crystal load capacitor, and feedback resistor
from X2. Nominally 14.31818MHz.
BUS (1:8) OUT BUS clock out puts, ope rates synchronously at CP U/2.
Device power down input, stops outputs low and shuts off crystal
oscillator and PLLs when low.*
Output enable for all CPU cloc ks, a l ogic low will Stop low all CPU
clocks.*
CPU clock out put c locks, ope rates at VDDL s upply voltage (with
IOAPIC), e ither nominal 3.3V VDD or reduced voltage 2.9 t o 2.5V.
Output enable for all BUS clock, a logic low will stop Low all Bus
clocks.*
IOAPIC clock output. ( 14.318 MHz), operates at VDDL supply voltage
with CPU (1: 4), eithe r nomin al 3.3V VDD o r reduced vo ltage
2.9 to 2.5V.
Power supply for CPU and IOAPIC block buffers, operates at nominal
3.3V VDD or reduced volt age 2.9 to 2.5V.
* Has internal pull-up to V
DD3
.
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ICS9147-06
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
V
DDL=VDD3
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Current
Output High Current
Output Low Vo ltage V
Output High Voltage V
Output Low Vo ltage
Output High Voltage
Output Low Vo ltage
Output High Voltage
Supply Current
Supply Current
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
=3.0 3.7 V, TA = 0 70° C unless otherwise stated
DC C haracteristics
PAR AMET ER SYM BOL TEST C ONDI TIONS MIN T YP M AX UNIT S
V
V
I
I
OH1
I
I
OH2
I
I
OH3
V
V
V
V
I
I
IL
IH
I
IL
I
IH
OL1
OL2
OL3
OL1
OH1
OL2
OH2
OL3
OH3
DD
DD
VIN=0V -28.0 -10.5 - µA
VIN=VDD -5.0 - 5.0 µA
VOL=0.8V;
for CPUH, BUS & REF1
(and CPU & IOAPIC at VDDL= 3.0
to 3.7V)
VOH= 2.0 V;
for CPUH, BUS & REF1
(and CPU & IOAPIC at VDDL = 3.0
to 3.7V)
VOL=0.8V; REF (2:3), 24, 48 CLKs - 26.0 - mA
VOH=2.0V; REF (2:3), 24, 48 CLKs - -21.0 - mA
VOL=0.8V; for CPUL at
VDDL = 2.5V
VOH = 1.7V; f or CP UL at
VDDL = 2.5V
IOL = 10mA;
for CPUH, BUS & REF1
(an d CP U L at VDD L = 3.0 t o 3. 7V )
IOH = -10mA;
for CPUH, BUS & REF
(an d CP U L at VDD L = 3.0 t o 3. 7V )
IOL = 8m A - 0.25 0.4 V
IOH = -8mA 2.4 2.6 - V
IOL = 8 mA; for CPUL at
VDDL = 2.5V
IOH = -8mA; for CPUL at
VDDL = 2.5V
@66.6 M Hz; all outputs unloaded - 70 140 mA
PD# 230 500 µA
- - 0.2VDD V
0.7V
DD
- 33.0 - mA
--28.0- mA
-26-mA
-24-mA
- 0 .22 0.4 V
2.4 2.8 - V
- 0 .2 5 0.4 V
2.1 2.25 - V
--V
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ICS9147-06
Electrical Characteristics at 3.3V
V
DDL=VDD3
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Duty Cycle D
Jitter, One Sigma
Jitter, Absolute
Jitter, One Sigma
Jitter, Absolute
Input Frequency
Logic Input Capacitance
Oscillator Input Capacitance
Power-on Time
Clock Skew
Clock Skew
Clock Skew
Clock Skew
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
=3.0 3.7 V, TA = 0 70° C unless otherwise stated
AC Characte ristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Tr1
Tf1
Tr2
Tf2
Tr1
Tf1
Tr2
Tf2
Tr3
Tf3
Tr4
Tf4
Dt1 20pF load @ VOUT=1.4V 45 50 55 %
Tjis1
Tjab1
Tjis2 REF1; Load = 47pF - 55 250 ps
Tjab2 REF1; Load = 47pF -500 200 500 ps
Fi 12.0 14.318 16.0 MHz
CIN Logic input pins - 5 - pF
CIN X X1, X2 pins - 18 - pF
ton
Tsk1
Tsk2 BUS to BUS; Load=20pF; @1.4V - 300 500 ps
Tsk3
Tsk4 CPU @ 2. 5 to CPUH @ 3.3V
sk5 CPU @ 2. 5V to BUS @ 3.3V
T
sk6 REF @ 3. 3V to IOAPIC @ 2.5V
T
20pF load, 0.8 to 2.0V
CPU, BUS & REF1
20pF load, 2.0 to 0.8V
CPU, BUS & REF1
20pF load, 20% to 80%
CPU, BUS & REF1
20pF load, 80% to 20%
CPU, BUS & REF1
30pF load, 0.8 to 2.0V
CPU, BUS & REF1
30pF load, 2.0 to 0.8V
CPU, BUS & REF1
30pF load, 20% to 80%
CPU, BUS & REF1
30pF load, 80% to 20%
CPU, BUS & REF1
20pF load, 0.8 to 2.0V
24 & 48 clocks & REF (2:3)
20pF load, 2.0 to 0.8V
24 & 48 clocks & REF (2:3)
20pF load, 0.4 to 2.0V , CPU with
VDDL = 2.5V and IOAPIC
20pF load, 2.0 to 0.4V, CPU with
VDDL = 2.5V and IOAPIC
t2 REF (1:3) 40 45 50 %
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
-250 - 250 ps
From VDD=3.0V to 1st crossing of
66.6 MHz VDD supply ramp < 1 ms
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
CPU to BUS; Load=20pF; @1.4V
(CPU is early) (All at 3.3V)
-0.91.5ns
- 0. 8 1.4 ns
-1.52.5ns
- 1. 4 2.4 ns
-0.91.5ns
- 0. 8 1.4 ns
-1.52.5ns
- 1. 4 2.4 ns
--- ns
-- ns
- - 1.6 ns
- - 1.6 ns
- 50 150 ps
-1.53.0 ms
- 150 250 ps
13.3 4 ns
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Recommended PCB Layout for ICS9147-06
ICS9147-06
NOTE:
This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of
components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible
to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced
with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the
dif ferent Vdd planes.
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ICS9147-06
SYMBOL COMMON DIMENSIONS VARIATIONS D N
A .095 .101 .110 AC .620 .625 .630 48
A1 .008 .012 . 016
A2 .088 .090 . 092
B .008 .010 .0135
C .005 - .010
D See Variations
E .292 .296 . 299
e 0.025 BSC
H .400 .406 .410
h .010 .013 . 016
L .024 .032 . 040
N See Variations
∝
X .085 .093 .100
MIN. NOM. MAX. MIN. NOM. MAX.
0° 5° 8°
Ordering Information
ICS9147F-06
Example:
ICS XXXX F - PPP
SSOP Package
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
6
device data to verify that any information being relied upon by the customer is current
and accurate.
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