can accept most standard differential input levels. The
ICS8344I is designed to translate any differential signal levels to LVCMOS levels. The low impedance L VCMOS outputs
are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of
the dual clock input. The dual clock inputs also facilitate board
level testing. ICS8344I is characterized at full 3.3V , full 2.5V
and mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344I ideal for those clock distribution applications demanding well defined performance and repeatability .
The ICS8344I is a low voltage, low skew fanout
buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs
FEATURES
• 24 L VCMOS outputs, 7Ω typical output impedance
• 2 selectable differential clock input pairs for redundant clock
applications
• CLKx, nCLKx pair can accept the following differential input
levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL
• Maximum output frequency up to 100MHz
• Translates any single-ended input signal to L VCMOS with
resistor bias on nCLK input
• Multiple output enable pins for disabling unused outputs in
reduced fanout applications
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-24
ICS8344I
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage T emperature, T
DD
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only . Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
ods may affect product reliability.
4.6V
-0.5V to VDD + 0.5V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0lfpm)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for extended peri-
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
9
Page 10
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
V
V
DD
DDO
LVCMOS
VDD = +1.65V
V
= +1.65V
DDO
GND = -1.65V
V
DDO
SCOPE
Qx
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
SCOPE
LVCMOS
V
= +1.25V
DDO
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
10
Qx
Page 11
Integrated
Circuit
Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
V
V
DD
DDO
LVCMOS
VDD = +2.05V
V
= +1.25V
DDO
GND = -1.25V
Qx
FIGURE 1C - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
V
DD
SCOPE
CLK0, CLK1
nCLK0, nCLK1
GND
Qx
Qy
VPP
Cross Points
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
tsk(o)
FIGURE 3 - O UTPUT SKEW
V
CMR
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
11
Page 12
Integrated
Circuit
Systems, Inc.
P ART 1
Qx
P ART 2
Qy
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
Clock Inputs
and Outputs
CLK0, CLK1
nCLK0, nCLK1
Q0 - Q23
70%
30%
trisetfall
FIGURE 5 - INPUTAND OUTPUT RISEAND FALL TIME
V
/2
DDOx
tp
LH
tp
HL
FIGURE 6 - PROPAGATION DELAY
70%
30%
V
SWING
CLK0, CLK1,
Q0 - Q23
nCLK0, nCLK1
Pulse Width
t
PERIOD
t
odc =
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
PW
t
PERIOD
FIGURE 7 - odc & t
12
PERIOD
Page 13
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
APPLICA TION INFORMATION
WIRINGTHE DIFFERENTIAL INPUTTO ACCEPT SINGLE ENDED LEVELS
ICS8344I
Figure 8
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
= 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
DD
CLK_IN
CLK_IN
C1
C1
0.1uF
0.1uF
R1
1K
R11K
V_REF
V_REF
R2
1K
R21K
VDD
VCC
+
+
-
-
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
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Integrated
Circuit
Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θ
TRANSISTOR COUNT
The transistor count for ICS8344I is: 1,449
VS
. AIR FLOW TABLE
JA
q
Single-Layer PCB, JEDEC Standard Test Boards67.8°C/W55.9°C/W50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards47.9°C/W42.1°C/W39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
by V elocity (Linear Feet per Minute)
JA
0200500
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
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Page 15
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-L VCMOS FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
LOBMYS
N
A
1A
2A
b
c
D
1D
2D
E
1E
2E
e
L
q
ccc
Reference Document: JEDEC Publication 95, MS-026
MUMINIMLANIMONMUMIXAM
84
50.051.0
53.104.154.1
71.022.072.0
90.002.0
54.006.057.0
°
0
SRETEMILLIMNISNOISNEMIDLLA
CCB
06.1
CISAB00.9
CISAB00.7
05.5
CISAB00.9
CISAB00.7
05.5
CISAB5.0
7
°
80.0
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8344BYIwww.icst.com/products/hiperclocks.htmlREV. A AUGUST 9, 2001
16
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