The ICS671-01 is a low phase noise, high speed
PLL based, 8 output, low skew zero delay buffer
and multiplier. Based on ICS’s proprietary low
jitter Phase Locked Loop (PLL) techniques, the
device provides eight low skew outputs at speeds
up to 160 MHz at 3.3 V. The ICS671-01 includes
a bank of six outputs running at either x2 or x4
mode, one output running at either x2, x4, or x5
mode, and one more output running at either x1,
x2, or x4 mode. For normal operation, output
clock CLK8 is tied to the FBIN pin.
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
Block Diagram
Features
• Packaged in 16 pin narrow SOIC
• Clock outputs from 5 to 160 MHz
• Zero input-output delay
• Integrated x2 or x4 selections, and x5 for CLK7
• Eight low-skew (<250 ps) outputs
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• 3.3 V to 5 V operating voltage
CLKIN
FBIN
S1, S0
CLK1
CLK2
CLK3
x2, x4, or x5
PLL
2
Control
Logic
CLK4
CLK5
CLK6
CLK7
CLK8
MDS 671-01 B1Revision 051700 Printed 11/15/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 2
ICS671-01
Zero Delay, Low Skew Buffer and Multipler
Pin Assignment
ICS671-01
16
1
CLK1
2
3
VDD
GND
CLK3
CLK4
S0
4
5
6
7
8
16 pin narrow (150 mil) SOIC
Output Clock Mode Select Table
S1S0CLK1:6CLK7CLK8Input range
00Tri-state (high impedance) Tri-state (high impedance)Tri-state (high impedance)01x2x5x15 to 30 MHz
10x 2x2x215 to 80 MHz
11x4x 4x47.5 to 40 MHz
15
14
13
12
11
10
9
FBINCLKIN
CLK8
CLK7CLK2
VDD
GND
CLK6
CLK5
S1
Pin Descriptions
NumberName TypeDescription
1CLKINIClock Input.
2, 3, 6, 7,
10, 11
4, 13VDDPPower supply. Connect both pins to same voltage (either 3.3 V or 5 V).
5, 12GNDPConnect to ground.
8S0ISelect input 0. See table above.
9S1ISelect input 1. See table above.
14CLK7IClock Output 7. See table above.
15CLK8IClock Output 8. See table above. Normally use this clock as feedback.
16FBINIFeedback Input. Connect to CLK8 under normal operations.
CLK1:6OClock Outputs 1:6. See above table.
Key: I = Input; O = output; P = power supply connection.
External Components
The ICS671-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND
on pins 13 and 12, as close to the device as possible. A series termination resistor of 33 Ω may be used close
to each clock output pin to reduce reflections.
MDS 671-01 B2Revision 051700 Printed 11/15/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 3
ICS671-01
Zero Delay, Low Skew Buffer and Multipler
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDDReferenced to GND-0.57V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Electrostatic DischargeMIL-STD-8832000V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Junction temperature150°C
Storage temperature-65150°C
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD3.135.50V
Input High Voltage, VIH, CLKIN pin onlyVDD/2+1VDD/2V
Input Low Voltage, VIL, CLKIN pin onlyVDD/2VDD/2-1V
Input High Voltage, VIH2V
Input Low Voltage, VIL0.8V
Output High Voltage, VOHIOH=-25mA2.4V
Output Low Voltage, VOLIOL=25mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-8mAVDD-0.4V
Short Circuit CurrentEach output±50mA
Input CapacitanceS0, S1, FBIN7pF
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock FrequencySee table on page 2580MHz
Output Clock FrequencySee table on page 25160MHz
Output Clock Rise Time, CL=30pF0.8 to 2.0V1.5ns
Output Clock Fall Time, CL=30pF2.0 to 0.8V1.5ns
Output Clock Duty Cycle, VDD=3.3VAt VDD/2405060%
Device to Device Skew, equally loadedrising edges at VDD/2700ps
Output to Output Skew, equally loadedrising edges at VDD/2250ps
Input to Output Skew, FBIN to CLK8rising edges at VDD/2±350ps
Maximum Absolute Jitter300ps
Cycle to Cycle Jitter, 30pF loads 500ps
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With CLKIN = 20 MHz, FBIN to CLK8, all outputs at 40 MHz.
3. With CLKIN = 80 MHz, FBIN to CLK8, all outputs at 160 MHz.
No Load, S1=1, S0=025mA
No Load, S1=1, S0=074mA
MDS 671-01 B3Revision 051700 Printed 11/15/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 4
Zero Delay, Low Skew Buffer and Multipler
Package Outline and Package Dimensions
(
For current dimensional specifications, see JEDEC Publication No. 95.)
ICS671M-01TICS671M-01tape and reel16 pin SOIC0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 671-01 B4Revision 051700 Printed 11/15/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
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