The ICS604 is the most cost effective way to
generate high quality, high frequency clocks for
Intel’s latest generation of graphics controllers. It
provides 48 MHz for the graphics controller, a
24.576 MHz clock for video or audio, as well as a
14.31818 MHz buffered output for the system
clock. Using patented Phase-Locked-Loop (PLL)
techniques, the ICS604 requires only a standard
fundamental mode, inexpensive crystal.
ICS makes additional devices to meet multiple
graphic system requirements. If the 24.576 MHz
clock is not needed, use the ICS513. If additional
frequencies are required for different video
encoders and decoders, see the ICS614-01.
Features
• Packaged as 8 pin SOIC or die
• Compatible with Intel graphics controllers
• Zero ppm synthesis error on 48 MHz output
• Input frequency of 14.31818 MHz
• Output clock frequencies of 48 MHz,
24.576 MHz, plus 14.31818 MHz Reference
output
• Low jitter
• Operating voltages of 3.0 to 5.5 V
• Full CMOS-level outputs with 25 mA drive
capability at TTL levels
• Advanced, low power CMOS process
Block Diagram
14.318 MHz
crystal or clock
X1/ICLK
X2
VDDC GND
Crystal
Oscillator
PLL
Clock
Synthesis
and Control
Circuitry
VDDIO
Output
Buffer
Output
Buffer
Output
Buffer
48 MHz
24.576 MHz
14.318 MHz
MDS 604 A1Revision 022499 Printed 11/14/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
Page 2
Pin Assignment
PRELIMINARY
PRELIMINARY
INFORMATION
INFORMATION
Intel Graphics Clock Source
ICS604
X1/ICLK
VDDC
GND
14.3M
18
2
3
4
7
6
5
X2
VDDIO
24.576M
48M
Pin Descriptions
NumberName TypeDescription
1X1/ICLKXICrystal connection for 14.31818 MHz crystal, or clock input.
2VDDCPConnect to +3.3V or +5V. +5 V recommended for lowest output noise (jitter).
3GNDPConnect to ground.
414.3MOBuffered crystal oscillator output clock.
548MO48.0 MHz clock output for Intel graphics controller.
624.576MO24.576 MHz clock output.
7VDDIOPConnect to +3.3 V or +5 V. Cannot be greater than VDDC.
8X2XOCrystal connection for 14.31818 MHz crystal. Leave unconnected for clock input.
Key: I = Input; O = output; XI, XO = crystal connections; P = power supply connection
External Components / Crystal Selection
The ICS604 requires 0.01 µF decoupling capacitors to be connected between VDDC and GND, and
between VDDIO and GND. They must be connected close to the ICS604 to minimize lead inductance.
No external power supply filtering is required for this device. A 33 Ω terminating resistor can be used next
to the output pins when driving 50 Ω lines. The total on-chip crystal capacitance is approximately 6 pF,
and a parallel resonant, fundamental mode crystal should be used. Crystal capacitors should be connected
from each of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF)
of these crystal caps should be = (CL-6)*2, where CL is the crystal load capacitance in pF. For a clock
input, connect to X1 and leave X2 unconnected (no capacitors on either).
MDS 604 A2Revision 022499 Printed 11/14/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
Page 3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDDC = 5 V unless otherwise noted)
AC CHARACTERISTICS (VDDC = 5 V unless otherwise noted)
PRELIMINARY
INFORMATION
INFORMATION
ICS604
Intel Graphics Clock Source
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply Voltage, VDDC or VDDIOReferenced to GND7V
InputsReferenced to GND-0.5VDDC+0.5V
Clock OutputsReferenced to GND-0.5VDDC+0.5V
Ambient Operating Temperature070C
Soldering TemperatureMax of 10 seconds260C
Storage temperature-65150C
Input Frequency, crystal input14.31818MHz
Input Frequency, clock input14.31818MHz
Actual mean frequency error vs target48.0 MHz0ppm
24.576 MHz32ppm
Output Clock Rise Time0.8 to 2.0V1ns
Output Clock Fall Time2.0 to 0.8V1ns
Output Clock Duty Cycleat VDDIO/24060%
Absolute Clock Period Jitter, deviation48.0 MHz±250ps
from mean. VDDC = 5 V, VDDIO = 3.3 V24.576 MHz±125ps
Absolute Clock Period Jitter, deviation48.0 MHz±350ps
from mean. VDDC = 3.3 V, VDDIO = 3.3 V 24.576 MHz±160ps
One Sigma Clock Period Jitter,48.0 MHz90ps
VDDC = 5 V, VDDIO = 3.3 V24.576 MHz40ps
One Sigma Clock Period Jitter,48.0 MHz110ps
VDDC = 3.3 V, VDDIO = 3.3 V24.576 MHz50ps
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25 C.
MDS 604 A3Revision 022499 Printed 11/14/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
Page 4
PRELIMINARY
Inches
Millimeters
PRELIMINARY
Package Outline and Package Dimensions
EH
INFORMATION
INFORMATION
Intel Graphics Clock Source
8 pin SOIC
ICS604
Q
Pin 1
e
D
SymbolMinMaxMinMax
A0.0550.0681.3971.7272
b0.0130.0190.3300.483
D0.1850.2004.6995.080
h x 45°
A
c
b
E0.1500.1603.8104.064
H0.2250.2455.7156.223
e
h0.0150.381
Q0.0040.010.1020.254
While the information presented herein has been checked for both accuracy and reliability, ICS assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 604 A4Revision 022499 Printed 11/14/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
Ordering Information
Part/Order NumberMarkingPackageTemperature
ICS604MICS604M8 pin SOIC0 - 70 C
ICS604MTICS604M8 pin SOIC on tape and reel0 - 70 C
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