Datasheet ICS574M, ICS574MT Datasheet (ICST)

Zero Delay, Low Skew Buffer

PLL-based zero delay buffer for high speed
applications. Based on ICS’s proprietary low jitter
Phase Locked Loop (PLL) techniques, the device
provides four low skew outputs at speeds up to 160
MHz at 3.3 V. When one of the outputs is connected
directly to FBIN, the rising edge of each output is
aligned with the rising edge of the input clock. External
delay elements connected in the feedback loops will
cause the outputs to occur before the inputs by the
amount of propagation delay of the external element.

ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.

Description Features

ICS574

The ICS574 is a low jitter, low-skew, high performance

Block Diagram

• Packaged in 8 pin narrow SOIC

• Zero input-to-output delay

• Four 1X outputs

• Output to output skew is less than 150 ps

• Output clocks up to 160 MHz at 3.3 V

• External feedback path for output edge placement

• Spread Smart™ technology works with spread
spectrum clock generators

• Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V

• Advanced, low power, sub-micron CMOS process

• Operating voltage from 3.0 to 5.5 V

FBIN

CLKIN

MDS 574 B 1 Revision 051801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone] • www.icst.com

PLL

CLK1
CLK2
CLK3
CLK4

Pin Assignment

ICS574

Zero Delay, Low Skew Buffer

CLKIN

CLK1
CLK2

GND

1 8
2

3
4

Standard 8 pin SOIC

FBIN

7

CLK4

6

CLK3

5

VDD

Pin Descriptions

Number Name Type Description

1 CLKIN I Clock input. Connect to input clock source.

2, 3, 6, 7 CLK1:4 O Four clock outputs.

5 VDD P Power supply. Connect both pins to same voltage (either 3.3V or 5V).
4 GND P Connect to ground.
8 FBIN I Feedback input.

Key: I = Input; O = output; P = power supply connection.

External Components

The ICS574 requires a minimum number of external components for proper operation. Decoupling capacitors of

0.1µF should be connected between VDD and GND on pins 4 and 5, as close to the device as possible. A series
termination resistor of 33 Ω may be used close to the pin for each clock output to reduce reflections.

MDS 574 B 2 Revision 051801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone] • www.icst.com

ICS574

Maximum

ABSOLUTE MAXIMUM RATINGS (note 1)

DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

Zero Delay, Low Skew Buffer

Electrical Specifications

Parameter Conditions Minimum Typical

Supply voltage, VDD Referenced to GND -0.5 7 V
Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V
Electrostatic Discharge MIL-STD-883 2000 V
Ambient Operating Temperature 0 70 °C
Soldering Temperature Max of 10 seconds 260 °C
Junction temperature 150 °C
Storage temperature -65 150 °C

Operating Voltage, VDD 3.00 5.50 V
Input High Voltage, VIH VDD/2+1 V
Input Low Voltage, VIL VDD/2-1 V
Output High Voltage, VOH IOH=-18 mA 2.4 V
Output Low Voltage, VOL IOL=18 mA 0.4 V
Output High Voltage, VOH, CMOS level IOH=-5 mA VDD-0.4 V

Operating Supply Current, IDD (Note 2)
Short Circuit Current Each output ±65 mA

Input Capacitance 7 pF

No Load 36 mA

Units

Input Clock Frequency FBIN to CLK1 20 160 MHz
Output Clock Frequency FBIN to CLK1 20 160 MHz
Output Clock Rise Time, CL=30pF 0.8 to 2.0V 1.5 ns
Output Clock Fall Time, CL=30pF 2.0 to 0.8V 1.5 ns
Output Clock Duty Cycle, VDD=3.3V At 1.4V 40 50 60 %
Device to Device Skew, equally loaded rising edges at VDD/2 700 ps
Output to Output Skew, equally loaded rising edges at VDD/2 150 ps
Maximum Absolute Jitter 150 ps
Cycle to Cycle Jitter, 30pF loads 66.67 MHz outputs 250 ps

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the

device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.

2. With CLKIN = 160 MHz, FBIN to CLK4

Using Spread Spectrum Input Clocks

The ICS574 uses ICS’ Spread Smart technology, allowing it to accurately track (pass through) any clocks that
implement spread spectrum techniques.

MDS 574 B 3 Revision 051801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone] • www.icst.com

Zero Delay, Low Skew Buffer

Inches

Millimeters

Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)

8 pin SOIC

Symbol Min Max Min Max

A 0.0532 0.0688 1.35 1.75

A1 0.0040 0.0098 0.10 0.24

E H

INDEX

AREA

h x 45°

D

B 0.0130 0.0200 0.33 0.51
C 0.0075 0.0098 0.19 0.24
D 0.1890 0.1968 4.80 5.00
E 0.1497 0.1574 3.80 4.00

e

H 0.2284 0.2440 5.80 6.20

h 0.0099 0.0195 0.25 0.50
L 0.0160 0.0500 0.41 1.27

ICS574

A1 C

e

B

A

L

Ordering Information

Ordering Information

Part/Order Number Marking Shipping packaging Package Temperature

ICS574M ICS574M tubes 8 pin SOIC 0-70 °C

ICS574MT ICS574M tape and reel 8 pin SOIC 0-70 °C

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems,
Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third
parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or
other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the
right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.

MDS 574 B 4 Revision 051801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone] • www.icst.com