The ICS542 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
156 MHz, and produces a divide by 2, 4, 6, 8, 12,
or 16 of the input clock. There are two outputs on
the chip, one being a low-skew divide by two of
the other. So, for instance, if a 100 MHz clock is
used, the ICS542 can produce low skew 50 MHz
and 25 MHz clocks, or low skew 25 MHz and
12.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS542 is a member of the ICS
ClockBlocks™ family of clock building blocks.
See the ICS541 and ICS543 for other clock
dividers, and the ICS501, 502, 511, 512 and 525
for clock multipliers.
Features
• Packaged as 8 pin SOIC
• ICS’ lowest cost clock divider
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 156 MHz
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V
Block Diagram
S1, S0
Input Clock
VDD GND
2
Divider and
Selection
Circuitry
Output
Buffer
÷2
Output
Buffer
OE (both outputs)
CLK
CLK/2
MDS 542 B1Revision 050400 Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
0 = connect directly to ground.
1 = connect directly to VDD.
8 pin SOIC
Pin Descriptions
NumberName TypeDescription
1ICLKCIClock input.
2VDDPConnect to +3.3V or +5V.
3GNDPConnect to ground.
4S0ISelect 0 for output clock. Connect to GND or VDD. Internal pull-up.
5S1ISelect 1 for output clock. Connect to GND or VDD. Internal pull-up.
6OEIOutput Enable. Tri-states both output clocks when low. Internal pull-up.
7CLK/2OClock output per Table above. Low skew divide by two of pin 8 clock.
8CLKOClock output per Table above.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS542 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS542 to minimize lead inductance. No external power supply filtering is
required for this device. A 33 Ω series terminating resistor can be used next to each output pin. If a 3.3 V
input clock is applied to the ICLK pin, with the ICS542 at 5 V, the clock must be AC coupled.
MDS 542 B2Revision 050400 Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Page 3
ICS542
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Clock Divider
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply Voltage, VDDReferenced to GND7V
InputsReferenced to GND-0.5VDD+0.5V
Clock OutputReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070C
Soldering TemperatureMax of 10 seconds260C
Storage temperature-65150C
Input Frequency, clock inputat VDD = 5V0156MHz
Input Frequency, clock inputat VDD = 3.3V0156MHz
Skew of output clocksrising edges at VDD/2500ps
Output Clock Rise Time0.8 to 2.0V1ns
Output Clock Fall Time2.0 to 0.8V1ns
Output Clock Duty Cycleat VDD/24549 to 5155%
MDS 542 B3Revision 050400 Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Page 4
Package Outline and Package Dimensions
Inches
Millimeters
EH
INDEX
AREA
12
h x 45°
D
ICS542
Clock Divider
8 pin SOIC
SymbolMinMaxMinMax
A0.05320.06881.351.75
A1
D0.18900.19684.805.00
H0.22840.24405.806.20
0.00400.00980.100.24
B0.01300.02000.330.51
C
0.00750.00980.190.24
E0.14970.15743.804.00
e
h0.00990.01950.250.50
L0.01600.05000.411.27
A1C
A
e
B
L
Ordering Information
Part/Order NumberMarkingPackageTemperature
ICS542MICS542M8 pin SOIC0 to 70 °C
ICS542MTICS542M8 pin SOIC on tape and reel0 to 70 °C
While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock
does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments.
ClockBlocks is a trademark of ICS
MDS 542 B4Revision 050400 Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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